JPH09293043A - Stream data transfer device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To control data transfer at a storage device side regardless of the state of an input/output port and to easily test the state of a DMA operation by detecting a frame signal which is inputted from the input/output port and inputting data indicating a frame in place of data. SOLUTION: When the order of data in the frame is outputted, the value of a frame data counter 35 is outputted in placed of stream data which is inputted from the port. The frame data counter 35 successively executes counting in accordance with data transfer after resetting by a frame pulse. Therefore, when the input of stream data is checked, an operation for fetching data by DMA can be checked regardless of the data state at a port side. In this case, data stored in a memory can be easily checked since a number is given to order. A pseudo frame input operation is also enabled even at the time of the state without no port signals at all.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a stream data transfer device for inputting / outputting continuous media data such as video information to / from an input / output port.

[0002]

2. Description of the Related Art A distribution system for video information such as moving images is
A demand type service that distributes video information to a large number of users in response to requests from each user is provided. In such a system, a mass storage device is used to store continuous media information such as video data called a stream. As for the video information stored in the mass storage device, the portion corresponding to the request of each user is read and the video information is distributed through the channels. Here, a channel refers to a logical or physical resource of the system that is not common to each user but is individually assigned to each user, and an input / output port for data distribution to each user. Say.

The data transfer in such a distribution system has the following features. First, in reading data such as video information from a large-capacity storage device, it is necessary to continuously read data blocks of a large size at a high data transfer rate. Here, the block is read as a unit because it is more efficient to read continuous data from a hard disk device or an optical disk device used as a mass storage device, and the average data transfer rate can be increased. The data transfer rate is a value indicating the amount of data transferred per unit time.

Second, the data transfer rate of user-side channel output is lower than the data transfer rate that can be output from the mass storage device for one user. For example, as a mass storage device, FastWide
There is a hard disk drive with an interface of SCSI standard, and the data transfer rate is 20MB /
s. The video information is usually compressed and stored like MPEG. For example, if the data is based on the MPEG1 standard, the data transfer rate is 1.5 Mbps (= 0.1).
875 MB / s). For higher quality compressed video, stream data having a high data transfer rate of about 30 Mbps (= 3.75 MB / s) may be used. In any case, the stream data of a plurality of video information can be distributed to each user from one mass storage device.

It should be noted that such video information is usually 3 times per second.
It consists of 0 frames, and in data transfer,
It is appropriate to manage each frame collectively to facilitate data management. A frame signal is also used on the input / output port of the server system to indicate such a frame delimiter. This can be indicated by a frame symbol in the data or a frame signal other than the data line.

In addition to the distributed output of the video information, the video information is input from an external device such as a VCR and stored in the mass storage device when the video information is edited. Even in the case of such an input, the data transfer rate is the same as in the case of the output, only the direction of the data is changed.

An example of a conventional multi-stream data transfer device is shown in FIGS. 9 to 11. FIG. 9 is a diagram showing an overall configuration of a system for outputting and inputting video information using the multi-stream data transfer device.

A CPU 10, a memory 11, a SCSI interface 13, and stream interfaces 50a, b, c, d are connected to the system bus 12.
The system bus is, for example, PCI (Peripheral Component) which is a local bus standard.
An Interconnect bus is used. This P
The CI bus has a width of 32 bits or 64 bits and an operating frequency of 33 MHz, and in the case of 32 bits 33 MHz, a data transfer performance of 133 MB / s is possible. As a large-capacity storage device, four HDD (hard disk devices) 14a, b, c, d are connected to the SCSI interface 13.

There are displays 16a, b as output destinations of stream data, and video cassette recorders (VCR) 17a, c as input sources of stream data. Stream interfaces 50a, b, c, d are provided for connection to respective devices. Connect each.

Stream interfaces 50a, b,
A digital signal transmission interface such as IEEE 1394, which is a standard for serial digital transmission, is used from c and d to each device. With IEEE 1394, the maximum transmission speed of about 100 Mbps is possible.
Video information up to 30 Mbps can be transmitted with a sufficient margin.

FIG. 10 shows the stream interface 5.
It is a figure showing composition of a bus controller in 0a, b, c, and d. The bus controller controls data transfer to the system bus 12.

The address counter 54 for DMA generates the address of the memory 11 and the data counter 5
6, the data length to be transferred is counted. PCI
Since the address and the data are multiplexed on the bus, they are selected by the selector 53 in a time division manner and given to the system bus 12.

Next, the data transfer procedure will be described. First, H
DD 14a, b, c, d and input / output ports 25a, b,
Between c and d, data is temporarily stored in the memory 11 and a part of the memory 11 is used as a buffer for data transfer. If this buffer has a double buffer configuration,
For example, in the case of output, data is read from the HDDs 14a, b, c, d to the memory 11 and data is read from the memory 11 and the input / output port 25a,
Data output to b, c, and d can be executed in parallel. At this time, two types of data transfer are system bus 1
2, the system bus 12 is used in a time division manner, and the SCSI interface 13 and the stream interfaces 50a, 50b, 50c, 50c, 50d, and 50d take the right to use the system bus for data transfer.

Next, regarding the data transfer between the memory 11 and the stream interfaces 50a, b, c, d,
Data transfer is performed by the DMA method. CPU1
Stream interface 50a, b, c, d from 0
On the other hand, a DMA command including the above-mentioned address and data length is set. In the case of input, the stream interface 50a, b, c, d is instructed by the CPU 10.
Is started, the stream interface 50
The a, b, c, d take in data from the input / output ports 25a, b, c, d and store the data in the memory area indicated by the DMA address counter 54. Further, in the case of output, when the CPU 10 activates the stream interfaces 50a, b, c, d, the stream interfaces 50a, b, c, d are read from the area of the memory 11 indicated by the DMA address counter 54. Is read out and a stream is output from the input / output ports 25a, b, c, d.

The interface units 50a, 50b,
As another example of the connection of the system bus 12 with c and d, there is a configuration as shown in FIG. In this figure, a plurality of stream interfaces 50a, b,
c and d are connected via a bus bridge 51. Usually, the system bus 12 has restrictions such as the number of slots, and the number of connectable devices may be limited. A large number of stream interfaces 50a, b, c, d can be connected through the bus bridge 51. The interface on the secondary side of the bus bridge 51 at this time also operates according to the same protocol as the system bus 12.

As described above, according to the conventional data input / output method, it is possible to input or output video information to each channel without interruption by executing the DMA operation of a plurality of stream interfaces.

[0017]

However, the conventional stream data transfer system has the following problems.

First, when a data error occurs when inputting data from the input / output port, it is not possible to identify in which part the error occurred only by looking at the data stored in the memory. For example, it is difficult to identify even an error caused by software for inputting stream data. In addition, as an error caused by hardware, a frame delimiter is necessary to perform some input / output operation even if there is a data error, but if the frame signal is not detected correctly, it is impossible to transfer at all. Become.

Secondly, when developing a stream data transfer device, an internal block of the stream data transfer device is divided into a plurality of blocks. For example, in the case of a block for inputting / outputting data to / from an input / output port and a bus control block for accessing a storage device via a system bus, the state of inputting / outputting data can be achieved only after all blocks are completed. In such a case, concurrent development of software and hardware cannot be performed.

Therefore, according to the present invention, in order to solve the above problems, the data transfer control on the storage device side can be performed regardless of the state of the input / output port, and the state of the DMA operation can be easily tested. It is an object of the present invention to provide a stream data transfer device capable of performing the above.

[0021]

In order to achieve the above object, a stream data transfer apparatus according to the present invention comprises n sets of input / output ports for inputting / outputting continuous media data in which frame delimiters are indicated by frame signals. , A data input / output device for inputting / outputting to / from n sets of input / output ports and a storage means for storing continuous media data. The data input / output device corresponds to n sets of input / output ports. A set of buffer means and one of the buffer means
A data transfer control means for transferring data between the storage means and the storage means, and a mode for inputting / outputting data according to a frame signal input to the input / output port;
A mode for inputting / outputting frame data in accordance with the pseudo frame signal output from the counting means for generating a pseudo frame signal at fixed time intervals and a burst transfer for continuously transferring data when storing the data in the storage means are performed. There is one mode in which the position information of the storage means is stored in place of the data from the output port, the frame signal input from the input / output port is detected, and the data indicating the frame is input instead of the data. And a mode in which the value of the counting means for counting the order of the data in the frame is stored in the storage means.

[0022]

Embodiments of the present invention will be described below in detail with reference to the drawings.

(Configuration) FIG. 1 is a configuration diagram of a video server system according to an embodiment of the present invention. A CPU 10, a memory 11, a SCSI interface 13, and a stream interface 15 are connected to a common system bus 12. Under the control of the CPU 10, each of the interfaces 13 and 15 is a DMA (Direct Memory).
y access) data transfer with the memory 11 is executed. SC of SCSI interface 13
In the example of this figure, four HDDs (hard disk devices) 14a, b, c, d are connected to the SI bus. The example of the stream interface 15 in this figure has four ports, two of which are the display 1
6a and 6b are connected and stream data is output and displayed on the screen. VCRs (video cassette recorders) 17a and 17b are connected to the remaining two ports to capture stream data.

FIG. 2 shows the stream interface 15.
It is a figure which shows the concrete structure of. The DMA controller 21 connected to the system bus 12 is the system bus 1
2 memory access control and input / output side port 25
Control a, b, c, d. In the case of this example,
The DMA controller 21 has four buffers 23a,
b, c, d are connected to each of the buffers 23a, b,
The I / O controllers 24a, b, and
c and d are connected. Of these, two sets of buffers 23a,
b and the I / O controllers 24a and 24b are for output, and the other two sets are for input.

The output I / O controllers 24a and 24b are
The data from the buffers 23a and 23b is input / output port 25
The I / O controllers 24c and d for input perform the process of outputting to a and b, and perform the process of taking out the data from the signal lines of the input / output ports 25c and d and writing the data into the buffers 23c and d.

As the buffer, a FIFO memory is used, or a field memory (field memory) is used.
Use a memory called y). The FIFO memory is a first-in first-out memory and can transfer the input and output completely asynchronously for any number of data. The field memory can perform first-in first-out operation almost like a FIFO memory, but is usually used for writing and reading video information in frame units. A field memory is suitable for inputting and outputting a video stream. However, in the field memory, complete asynchronous input / output cannot be performed for all the data in the memory, so that writing and reading must be overlapped at each frame for data transfer. In the case of a video stream, since it is also continuous data, there is usually no interruption in both input data and output data.

FIG. 3 is a diagram showing a specific configuration of the DMA controller 21. Bus controller 37 is DMA
The entire controller 21 is controlled. System bus 1
2 and the buses of the buffers 23a, b, c, d (BD0, B
Between the D1, BD2, BD3) 22a, b, c, d, a tri-state buffer 30 for performing bus control and selectors 31, 32 are connected. The selector 32 performs a process of selecting the BD2 (22c) and BD3 (22d) buses, and performs data transfer corresponding to the input port. The selector 31 outputs the output of the selector 32 from the buffers 23c and 23d and the DMA address counter 33 and DM.
A data counter 34, frame data counter 35,
Select the frame mark 36.

The frame pulse (FP) 41 is input from the port side, selected as the output of the internal pseudo frame signal generation circuit 39, and given to the bus controller 37.

FIG. 4 shows a memory area in the memory 11 which is a target of DMA data transfer. Memory 1
A buffer area for temporarily storing the stream data is secured above 1, and DMA data transfer is executed to this buffer area. The buffer area is specified by the start address of this area and the size of the area. These are the start address and the data length, respectively. The DMA controller 21 stores these two pieces of information in C
When it is set by PU10 and activated, it transfers data.

(Operation) The operation will be described below with reference to FIGS. 5 to 8 in accordance with the configuration of FIGS. 1 to 4 described above.

First, the overall operation of the video server system will be described with reference to FIG. In the system shown in FIG. 1, the operation of outputting the data stored in the mass storage device through the stream interface 15 will be described.

The video data stored in the HDDs 14a, b, c, d are once read from the HDDs 14a, b, c, d and then stored in the buffer area in the memory 11. This process is performed by the SC instructed by the CPU 10.
The SI interface 13 executes.

The video data is usually composed of 30 frames per second, and in the case of a stream having a data transfer rate of 30 Mbps, it has a size of 125 KB per frame. When managing the buffer on a frame-by-frame basis, it is first read into the buffer area in the memory 11 and then transferred to the stream interface 15. If the buffer area in the memory 11 is managed by the double buffer method, 1
The SCSI interface 13 uses one buffer of the double buffer and the stream interface 15 uses the other buffer for each frame cycle, so that the processing of the two interfaces can be executed in parallel. Similarly, the input / output ports 25a, 25b,
Even when stream data is input from c and d, the directions of output and data transfer are only reversed. The stream data taken in from each port is temporarily stored in the buffer area on the memory by the stream interface 15, and then stored in the HDDs 14a, b, c, d by the DMA of the SCSI interface 13.

The DMA operation is performed by the DMA address counter 3
3 and the DMA data counter 34. At this time, as the data transfer progresses, the data counter 3
The transfer is continued until the value of 3 decreases and becomes 0.

Next, the system bus 1 for the memory 11
The data transfer operation on the H. 2 will be described with reference to FIG.

As a system bus, PCI (Periph)
eral Component Intercone
When using ct), the memory address and the data are multiplexed. Therefore, the system bus 12
First, an address is output on the 32 bits of to specify the location of the memory 11. Data is subsequently sent out after this address, and is sequentially accessed from the position designated by the address of the memory 11. Such data transfer is called burst transfer. That is, in one burst transfer, it is determined that the head is an address and the rest is data. Therefore, the address at this time is only the head value, and during one bus transaction, it is possible to access only consecutive addresses from the address head value. The burst transfer length is determined by the burst counter 40.

At the beginning of one transaction, the device that is the master of the bus outputs a bus request (REQ), and after the bus use permission (GNT) is returned, the bus access is started.

In normal stream data transfer, 125 KB is continuously transmitted, for example, in the case of one frame having 125 KB.
Sequential access is suitable, as long as they are sequentially stored in the area. Actually, on the system bus 12, one burst transfer is divided into units of several to several tens of continuous data. This allows a large number of devices (CPU 10, memory 11, SCSI interface 13, stream interface 1) on the system bus 12.
Even if 5) is connected, burst transfer is performed while sequentially assigning the system bus 12 to the device issuing the REQ, so that data transfer can be efficiently performed using the system bus 12.

Next, setting and operation of each mode in stream data transfer will be described.

The modes of data transfer are as follows. In a mode in which output to an external device and input from an external device are performed, each I / O controller 24
While a, b, c, d become active, according to the frame signal from each port 25a, b, c, d,
The DMA controller 21 controls the start of data transfer. The FP selector 41 selects the FP signal 41. Further, for the output port, the data value of the AD bus is output to the buffers 23a and 23b, and for the input port, the data from the buffers 23c and 23d is selected.
It is supplied to AD through 2, 31.

In the address value write mode at the time of data input, the selector 31 selects the DMA address counter 33 instead of the values of the BDs 22c and 22d.

In the pseudo frame selection mode, the signal from the pseudo frame signal generation circuit 49 is selected instead of the FP 41.

In the frame mark mode, the selector 31
At the FP pulse at the frame mark 36
Is selected.

In the frame data count mode, BD
The frame data counter 35 is selected instead of 22c and 22d.

Next, the address value write operation at the time of data input will be described with reference to FIG.

In burst transfer, a head address is designated, which indicates the location of the memory 11. In this mode, thereafter, the value of the DMA address counter 35 is output. The DMA address counter 35 sequentially counts as the data is transferred, and when sending eight pieces of data as shown in this figure, it sequentially outputs addresses n to n + 7. After this transfer, the DMA address counter 35 internally increments and the address value becomes n.
It becomes +8. In the next burst transfer, the address value is n +
Starting from 8, the same processing is performed thereafter.

According to this mode, even if no data is input, since the address value corresponding to the memory location is written in the memory 11 as the DMA-transferred data, the data of the external ports 25c and 25d is written. The DMA operation can be tested independently of the transfer. At this time,
The address value makes it easy to check whether the written value is correct or incorrect.

Next, the data transfer operation from the frame pulse will be described with reference to FIG. Frame pulse F
P41 occurs every frame cycle. In the case of a normal video signal, there are 30 frames per second, so the period of one frame is 33 ms. That is, the frame pulse FP41 is generated every 33 ms.

Data transfer in the case of data input from the input / output ports 25c and 25d will be described below. Buffer 2
3c and d are sizes that can store 2 frames of data. At this time, the buffer performs double buffer management in the same manner as the double buffer management on the memory 11. That is, while one frame is fetched from the ports 25c and d and stored in the buffers 23c and d, the previous frame is fetched from the buffers 23c and d and the DMA controller 21 performs burst transfer and stores it in the memory 11. I will do it. As shown in FIG. 7, the DMA controller operates according to a frame signal (FP) indicating the end of the input of the m-th frame and the start of the input of the m + 1-th frame on the port. The DMA transfer for the data of the frame is executed. During the operation of this DMA transfer, in parallel, m +
The first input is being executed.

Next, referring to FIG. 8, the operation of inputting the frame mark at the time of data input and the order of data in the frame will be described.

First, the insertion of the frame mark will be described. As shown in FIG. 7, frame data is sequentially stored in the memory from the frame signal. As shown in FIG. 8A, the frame mark 36 is selected by the selector 31 in accordance with the FP signal. Since the frame mark 36 is stored at the beginning of the frame in the memory 11, the beginning of the frame can be identified when checking the input data stored in the memory 11. Even if an error occurs on the input ports 25c and 25d, the data can be stored and the DMA part of the input operation can be tested.

Next, the case of outputting the order of the data in the frame will be described with reference to FIG. The value of the frame data counter 35 is output instead of the stream data input from the port. The frame data counter 35 is reset by the frame pulse and sequentially counted in accordance with the data transfer. When checking the input of stream data, it is possible to check the data fetching operation by the DMA regardless of the state of the data on the port side. At this time, since the data stored in the memory 11 are numbered in order, it is easy to check. Further, by selecting a signal from the pseudo frame signal generation circuit for the FP, it is possible to perform a pseudo frame input operation even when there is no port signal, so the system test becomes easy.

As described above, according to the stream data transfer device of the present invention, in the mode in which the DMA address counter is output to the system bus, the address value is written in the memory even if the data is not input. Therefore, the DMA operation can be easily tested only by checking the address value regardless of the data transfer of the external port.

Further, according to the mode of inserting the frame mark, the head of the frame can be easily identified when checking the input data stored in the memory.

Further, the pseudo frame pulse and the frame data counter can check the data fetch operation by the DMA regardless of the state of the data on the port side, and the DM can be checked regardless of the error occurrence at the input port.
A test is possible.

Although the embodiments of the stream data transfer apparatus according to the present invention have been described above, it goes without saying that the present invention is not limited to these embodiments. That is, with respect to the bus BD of the buffer inside the stream interface in the above embodiment, the output side of this bus is made into a tri-state buffer which can be controlled to a high impedance state, and is connected to the bus connected to the input selector to form a bidirectional bus. You can also do it. In this case, by making the buffer bidirectional, data can be input / output by switching bidirectionally with one port.

The memory address counter in the above embodiment may be generated by adding the base address and the data count value. The data counter sequentially increments its value in accordance with the data transfer, and an address can be generated by adding this value to the base address.

[0058]

As is apparent from the above description, according to the stream data transfer device of the present invention, it is possible to easily perform a test on the DMA operation of the stream data transfer device without actually performing external data transfer. I can do it.
This is very effective for identifying the cause of the error occurrence outside the boat, the error occurrence in the buffer portion, and the error occurrence in the DMA controller section.

Further, when the memory is accessed by the DMA operation, the actual data transfer to the input / output port is unnecessary, so that the software for the DMA operation can be developed independently of the external device. This is particularly effective for device driver development.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a video server system according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a specific configuration of a stream interface of the video server system.

FIG. 3 is a block diagram showing a specific configuration of a DMA controller of the stream interface.

FIG. 4 is a diagram showing a data transfer buffer area in a memory.

FIG. 5 is a timing diagram of burst data transfer to a memory.

FIG. 6 is a data sequence diagram in an address write mode.

FIG. 7 is a timing diagram showing data transfer from a frame pulse.

FIG. 8 is a diagram showing the content of data transfer from a frame pulse.

FIG. 9 is a block diagram showing the configuration of a conventional video server system.

FIG. 10 is a block diagram of a DMA controller in a conventional stream interface.

FIG. 11 is a block diagram showing a connection example of a stream interface in a conventional video server system.

[Explanation of symbols]

 10 CPU 11 Memory 12 System Bus 13 SCSI Interface 14 Hard Disk Device 15 Stream Interface 16 Display 17 VCR (Video Cassette Recorder) 21 DMA Controller 23 Buffer 24 I / O Controller 33 DMA Address Counter 34 DMA Data Counter 35 Frame Data Counter 36 Frame Mark 37 Bus Controller 39 Pseudo Frame Generation Circuit

Claims (4)

[Claims] 1. An n set of input / output ports for inputting / outputting continuous media data in which frame delimiters are indicated by a frame signal, a data input / output device for inputting / outputting to / from the n set of input / output ports, Storage means for storing continuous media data by bus connection with a data input / output device, wherein the data input / output device includes n sets of buffer means corresponding to each of the n sets of input / output ports; Data transfer control means for transferring data between one of the n sets of buffer means and the storage means, and counting means for generating a pseudo frame signal at fixed time intervals are provided. The output device has a first mode of inputting and outputting according to a frame signal input to the input / output port, and the counting device in place of the frame signal input to the input / output port. Stream data transfer apparatus characterized by having a second mode for inputting and outputting data in accordance with pseudo frame signal to be output. 2. The stream data transfer device according to claim 1, wherein the data transfer control means continuously transfers data to be stored following information on a position to be stored in the storage means. When the continuous media data is input from the input / output port, the data transfer control unit replaces the data input from the input / output port during burst transfer instructed by the burst transfer control unit. And outputting the storage position information of the storage means to the storage means. 3. N sets of input / output ports for inputting / outputting continuous media data in which frame delimiters are indicated by frame signals, data input / output devices for inputting / outputting to / from the n sets of input / output ports, Storage means for storing continuous media data by bus connection with a data input / output device, wherein the data input / output device includes n sets of buffer means corresponding to each of the n sets of input / output ports; The data input / output device includes data transfer control means for transferring data between one of the n sets of buffer means and the storage means, and the data input / output device receives data input to the input / output port. A first mode for outputting and a second mode for inputting data indicating a frame instead of the data input to the input / output port when the frame signal is input from the input / output port Stream data transfer apparatus characterized by having a mode. 4. The stream data transfer device according to claim 3, wherein the data transfer control unit includes a counting unit that counts the order of data in one frame, and the data input / output device includes: In the second mode,
A stream data transfer device, wherein the value of the counting means is output to the bus for each piece of data and stored in the storage means.