JPH09289326A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To passivate defects in the crystal grain boundary of a crystal silicon film, formed by crystallizing an amorphous silicon film, without use of hydrogen plasma processing. SOLUTION: A base film 102 and a crystal silicon film 105 obtained by crystallizing an amorphous silicon film 103 are formed on a glass substrate 101. The workpiece is heated in an oxygen atmosphere with added NF3 gas to grow a thermal oxidation film 106 on the surface of the crystal silicon film 105. As the thermal oxidation film 106 grows, unbonded Si is produced, and this surplus Si passivates defects in the crystal grain boundary of the crystal silicon film 105. The thermal oxidation film 106 is removed, and the crystal silicon film 105 is patterned into an insular shape to form the active layer 10 of TFT(Thin Film Transistor). A gate insulating film 108, a gate electrode 109 and so on are sequentially formed to complete TFT.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing an insulating gate type semiconductor device such as a thin film transistor.

[0002]

2. Description of the Related Art An active matrix type liquid crystal display device is small and lightweight and can display fine moving images at high speed. Therefore, it is expected to be a mainstay of future displays. The type of the substrate that constitutes a liquid crystal display device is limited because it has a light-transmitting property, and examples thereof include a glass substrate, a quartz substrate, and a plastic substrate. However, plastic substrates lack heat resistance, and quartz substrates can withstand temperatures as high as 100 ° C,
It is extremely expensive, especially when it has a large area.
It is more than doubled and lacks cost performance. Therefore, generally, the glass substrate is widely used because of its heat resistance and economical efficiency.

At present, the performance required of liquid crystal display devices is increasing more and more, and the performance and characteristics required of thin film transistors (hereinafter referred to as TFTs) used as switching elements are also increasing. Therefore, research on forming a crystalline silicon film having crystallinity on a glass substrate has been actively conducted. Currently, in order to form a crystalline silicon film on a glass substrate, a method of forming an amorphous silicon film and heating it to crystallize it is adopted.

Since the heat resistant temperature of the glass substrate is about 600 ° C., it is not possible to adopt a process exceeding the heat resistant temperature of the glass substrate in the step of forming the crystalline silicon film. To form a silicon film, a method of forming an amorphous silicon film by a plasma CVD method or a low pressure CVD method and heating it to crystallize is used.

Further, by irradiating with laser light,
A technique for crystallizing a silicon film is known, and it is possible to form a crystalline silicon film having excellent crystallinity even on a glass substrate, and laser light does not cause thermal damage to the glass substrate. Has the advantage.

[0006]

However, the crystalline silicon film obtained by crystallizing the amorphous silicon film has many defects derived from dangling bonds and the like. Defect is TF
Since it is a factor that deteriorates the characteristics of T, when a TFT is manufactured by using such a crystalline silicon film, defects in the interface between the active layer and the gate insulating film and the crystal grains of silicon in the active layer are used. It is necessary to passivate defects inside and at grain boundaries. In particular, defects at crystal grain boundaries are the largest factor for scattering charges, but it is very difficult to passivate defects at crystal grain boundaries.

When a TFT is formed on a quartz substrate,
Since heat treatment at a high temperature of about 1000 ° C. is possible, it is possible to compensate for defects in crystal grain boundaries of the crystalline silicon film with Si. On the other hand, when manufacturing a TFT on a glass substrate,
It is difficult to perform heat treatment at a high temperature, and generally, in the final stage of the process, hydrogen plasma treatment is performed in an atmosphere of about 300 to 400 ° C. to passivate the defects in the crystal grain boundaries of the crystalline silicon film with hydrogen. The n-channel TFT exhibits a practical field-effect mobility by performing hydrogen plasma treatment.

On the other hand, in the p-channel TFT, the effect of hydrogen plasma treatment is not so remarkable. It is interpreted that the level caused by crystal defects is formed in a relatively shallow region below the conduction electron band.

By the hydrogen plasma treatment, it is possible to compensate the defects of the grain boundaries of the crystalline silicon film, but the hydrogen compensating the defects is easily released, so that the hydrogen plasma treated TFT, especially n. The reliability of the type channel TFT over time is not stable. For example, an n-channel TFT at 90 ° C
If electricity is applied for 48 hours in the atmosphere, the mobility will be halved.

Further, although the crystalline silicon film obtained by irradiating the laser beam has good film quality, if the film thickness is 1000 Å or less, ridges (irregularities) are formed on the surface of the crystalline silicon film. When the silicon film is irradiated with laser light, the silicon film is instantaneously melted and locally expands, so that a ridge (unevenness) is formed on the surface of the crystalline silicon film in order to relieve the internal stress caused by the expansion. It The height difference of this ridge is about 1/2 to 1 times the film thickness. For example, the film thickness is 700
When the amorphous silicon film of about Å is heated to be siliconized and then laser annealing is performed, 100 to 30
A ridge having a height of about 0Å is formed.

In the insulating gate type semiconductor device, since a potential barrier and a trap level due to dangling bonds, lattice distortion, etc. are formed on the ridge on the surface of the crystalline silicon film, the active layer and the gate insulating film are formed. Will increase the interface state between and. Further, since the top of the ridge is steep, the electric field is likely to be concentrated, which may be a source of leakage current, and eventually dielectric breakdown may occur. The ridge on the surface of the crystalline silicon film is formed by sputtering or CVD.
This impairs the coverage of the gate insulating film deposited by the method, and lowers reliability such as insulation failure.

An object of the present invention is to solve the above problems and to passivate defects in crystal grain boundaries of a crystallized silicon film of an amorphous silicon film without using hydrogen plasma treatment. It is to provide a method for manufacturing a device.

Still another object of the present invention is to provide a method for manufacturing a semiconductor device having high reliability and high mobility. In particular, it has a gate insulating film made of a deposited film, An object of the present invention is to provide a method for manufacturing a semiconductor device which can improve the reliability and characteristics of the semiconductor device.

[0014]

In order to solve the above problems, the structure of a method for manufacturing a semiconductor device according to the present invention is
A step of forming an amorphous silicon film, a step of crystallizing the amorphous silicon film to form a crystalline silicon film, and a step of heating in an oxidizing atmosphere to which a fluorine compound gas is added to form the crystalline silicon film. There is a step of forming a thermal oxide film on the surface of the crystalline silicon film, a step of removing the thermal oxide film on the surface of the crystalline silicon film, and a step of depositing an insulating film on the surface of the crystalline silicon film.

Further, the structure of a method of manufacturing a semiconductor device according to another invention is the method of manufacturing a thin film transistor on a substrate having an insulating surface, the method comprising the step of forming an amorphous silicon film, and the amorphous silicon film. To form a crystalline silicon film, heating in an oxidizing atmosphere to which a fluorine compound gas is added to form a thermal oxide film on the surface of the crystalline silicon film; Of the thermal oxide film on the surface of the conductive silicon film, shaping the crystalline silicon film to form an active layer of a thin film transistor, and depositing an insulating film on the surface of the active layer to form at least a channel. Forming a gate insulating film on the surface of the region; forming a gate electrode on the surface of the gate insulating film; and implanting impurity ions imparting a conductivity type to the active layer using the gate electrode as a mask. And a step of forming source and drain in a self-aligned manner.

[0016]

1 and 2 show an embodiment of the present invention.
It will be described according to. 1 and 2 show thin film transistors (T
FIG. 1A is an explanatory diagram of a manufacturing process of FT), and in FIG. 1A, a base film 102 and an amorphous silicon film 10 are formed over a glass substrate 101.
3 are sequentially stacked, and a nickel (Ni) layer 104 is formed on the surface of the amorphous silicon film 103.

By performing heat treatment in this state, the amorphous silicon film 103 is crystallized to form a crystalline silicon film 105 as shown in FIG. 1 (B). Nickel layer 10
The step of forming No. 4 is not an essential step, but nickel functions as a catalyst for lowering the heat energy required for crystallization, so it is possible to lower the heating temperature of the crystallization treatment and shorten the treatment time. . As such a catalytic element,
In addition to nickel (Ni), Fe, Co, Ru, Rh, P
Although d, Os, Ir, Cu and Au can be used, nickel has the most remarkable catalytic effect.

It is also possible to form the crystalline silicon film by using a known technique without using nickel element. Further, as the crystallization step, laser light may be irradiated instead of the heat treatment. Furthermore, after forming the crystalline silicon film, optical annealing with laser light, infrared light, or the like, or thermal annealing may be performed.

FIG. 1C shows a thermal oxidation process. As the thermal oxide film 106 grows on the surface of the crystalline silicon film 105, that is, as Si—O bonds are formed, unbonded Si is generated. This surplus Si diffuses from the interface between the thermal oxide film 106 and the crystalline silicon film 105 into the crystalline silicon film 105, and is bonded to the dangling bond of Si existing at the crystal grain boundary to form crystalline silicon. Membrane 1
The defect of the grain boundary of No. 05 is passivated. As a result, the mobility of the TFT composed of the crystalline silicon film 105 can be improved. Further, in the subsequent manufacturing process involving heating, S which has passivated defects
Since i does not easily separate from the crystalline silicon film 105 like H, hydrogen plasma treatment can be omitted.

For example, in an n-channel TFT manufactured by the method for manufacturing a semiconductor device according to the present invention, the mobility after hydrogen plasma treatment is increased by 10 to 20% as compared with the mobility before hydrogen plasma treatment. This suggests that the defects of the crystalline silicon film 105 have been sufficiently passivated in the thermal oxidation process, and that the Si passivating the defects does not separate during the manufacturing process. .

The purpose of the thermal oxidation step in the present invention is to improve the passivation of defects at grain boundaries of the crystalline silicon film.
i for supplying i, and the crystalline silicon film 105 is a TFT
Considering that the active layer of the
Can be grown to a film of about 200 to 500 Å without considering the film quality such as pressure resistance. Further, in the present invention, since the TFT is intended to be manufactured on the glass substrate, the thermal oxidation step needs to be carried out under the condition that distortion, deformation and the like of the substrate caused by heating are acceptable. For example, the upper limit of the heating temperature may be based on the strain point of the glass substrate.

In the present invention, the thermal oxidation step is carried out in an oxidizing atmosphere containing a fluorine compound. Specifically, thermal oxidation is performed in an atmosphere in which NF ₃ gas or the like is added to oxygen gas. By adjusting the concentration of NF ₃ gas appropriately, it is possible to grow a thermal oxide film to a film thickness of several hundred Å by heating the glass substrate at a temperature below the strain point for several hours to several hours. is there.

The growth of a thermal oxide film is promoted by adding a gas that supplies Cl radicals such as HCl to an oxidizing atmosphere in addition to a gas that conventionally supplies fluorine radicals such as NF ₃ gas. However, it is unsuitable to form a thermal oxide film with a film thickness of several hundred Å at a temperature below the strain point of a glass substrate and at a temperature of about 600 to 500 ° C. because it takes time. NF ₃ gas is 45 in oxygen gas
In an oxidizing atmosphere with 0 ppm added, it is 4 at 600 ° C.
By heating for a time, it is possible to form a thermal oxide film of about 200 Å.

Further, in the thermal oxidation step, since the fluorine radicals are concentratedly supplied to the convex portion on the surface of the crystalline silicon film 105, the thermal oxidation of the convex portion is most advanced and the thermal oxidation of the concave portion is suppressed. To be done. Further, since the thermal oxide film 106 contains fluorine at a high concentration, stress is relieved, so that the crystalline silicon film 1
On the surface of 05, the thermal oxide film 106 with the convex portion rounded
Are formed with a uniform thickness.

In the thermal oxidation step, since it is necessary to determine the heating temperature and the heating time so that the strain and the deformation of the substrate are within the allowable range, when the concentration of the fluorine compound in the thermal oxidation atmosphere increases. There is also. As a result, although a large amount of fluorine is contained in the thermal oxide film 108 and Si—F bonds may be formed, the thermal oxide film 106 is Si that passivates defects at the grain boundaries of the crystalline silicon film. Since it is a film grown to supply the film, and is formed as a film to be removed later, its characteristics are not required to have the high function and high reliability of the gate insulating film, and the thermal oxide film 106 has It does not matter whether there is instability such as existing Si—F bond or pressure resistance.

FIG. 1D shows an active layer 107 formed by patterning the crystalline silicon film 105 after removing the thermal oxide film 106, and a gate insulating film 108.

In the present invention, the gate insulating film 108 is a film formed by a deposition method such as a plasma CVD method or a sputtering method. It is possible to use a thermal oxidation method to form the gate insulating film, but this is because the thermal oxide film obtained by thermal oxidation at a low temperature that allows deformation of the glass substrate is not excellent in film quality. . Therefore, in the present invention, in order to stably obtain a gate insulating film having a predetermined characteristic, the gate insulating film is formed by a deposition method such as a plasma CVD method or a sputtering method.

In the present invention, since the surface of the active layer 107 (crystalline silicon film 105) is flattened by the thermal oxidation process, even if the gate insulating film is formed by the deposition method, the gate insulating film is formed. The film can be formed with good coverage. Therefore, it becomes possible to lower the interface state between the gate insulating film and the active layer.

As described in the conventional example, the crystalline silicon film obtained by irradiating laser light has excellent crystallinity, but a ridge having a steep convex portion is formed on the surface thereof.
When an amorphous silicon film having a film thickness of about 700Å is heated to be siliconized and then laser annealing is performed, a ridge having a height of about 100 to 300Å is formed on the surface thereof. By thermal oxidation for 12 hours in an atmosphere in which about 450 ppm of NF ₃ gas is added to oxygen gas to form a thermal oxide film with a film thickness of about 500 Å, the height difference on the surface of the crystalline silicon film is set to about 10 Å It is also possible. Therefore, the insulating film can be deposited with good coverage on the surface of the crystalline silicon film crystallized by the laser beam by the CVD method.

FIG. 2A shows a step of doping impurity ions. The gate electrode 109 functions as a mask, and the source / drain 111, 112,
The channel 113 is formed in a self-aligned manner. Further, FIG.
As shown in (B), the interlayer insulating film 114, the electrode 115,
116 is formed, and the TFT is completed.

[0031]

【Example】

Example 1 FIGS. 1 and 2 are explanatory views of a manufacturing process of a TFT of this example, and are cross-sectional views of each step. In this embodiment, a TFT is manufactured using a silicon film crystallized by utilizing the catalytic action of a metal element that promotes crystallization of silicon. In this embodiment, nickel is used as the metal element.

As shown in FIG. 1A, the glass substrate 10
On 1 (Corning 1737, strain point 667 ° C.), a silicon oxide film is formed as a base film 102 to a thickness of 3000 Å by plasma CVD or low pressure thermal CVD. Next, by a plasma CVD method or a low pressure thermal CVD method, the intrinsic (I
Type amorphous silicon film 103 is formed to a thickness of 700Å to 1000Å. Here, the thickness of the amorphous silicon film 103 is set to 7
00 °.

After irradiating the surface of the amorphous silicon film 103 with UV light in an oxidizing atmosphere to form an oxide film (not shown) having a thickness of several 20Å on the surface, nickel is formed on the surface of the oxide film. A solution containing the element is applied. The oxide film improves the wettability of the surface of the amorphous silicon film 103 and suppresses repulsion of the solution. In this embodiment, a nickel acetate solution having a nickel content of about 1 to 100 ppm is used as the nickel element-containing solution. A nickel acetate solution is applied with a spinner or the like and dried to form the nickel layer 104. Although the nickel layer 104 does not necessarily form a perfect film, the nickel element is held in contact with the surface of the amorphous silicon film 203 via an oxide film (not shown) in this state.

However, if the nickel concentration in the silicon film is 1 × 10 ¹⁶ atoms · cm ⁻³ or less, it is difficult to obtain the effect of promoting crystallization. On the other hand, the nickel concentration is 5
If it is × 10 ¹⁹ atoms / cm ³ or more, the characteristics of the obtained silicon film as a semiconductor will be impaired and the characteristics as a metal will appear, so that the average nickel concentration in the finally obtained silicon film will be 1 × 10 ^{16 to} 5 × 10 ¹⁹ atoms / cm
The process conditions such as the concentration of nickel in the nickel acetic acid solution, the number of times of application, and the amount of application are set in advance so as to be ³ . The concentration of nickel may be measured by SIMS (secondary ion mass spectrometry method).

With the nickel element held on the surface of the amorphous silicon film 103, as shown in FIG. 1 (B), heat treatment is performed in a nitrogen atmosphere to form the amorphous silicon film 103.
Is crystallized to form a crystalline silicon film 105. In order to crystallize silicon, it is necessary to heat at a temperature of 450 ° C. or higher, but at a temperature of about 450 ° C. to 500 ° C., it takes several tens of hours or more to crystallize the amorphous silicon film. It is desirable to heat at a temperature of ℃ or more. Note that the heating temperature is not limited to the crystallization step shown in FIG. 1B, and it is necessary to set the heating temperature within a range in which deformation or shrinkage of the glass substrate caused by heating can be allowed. The upper limit of the heating temperature may be, for example, the strain point of the substrate. In this embodiment, since the glass substrate 101 having a strain point of 667 ° C. is used, the heating temperature is 620 ° C. and heating is performed for 4 hours.

By heating, nickel is converted into the amorphous silicon film 10.
From the surface of No. 3 toward the interface with the base film 102, the crystal growth of silicon progresses as it diffuses along a direction substantially orthogonal to the glass substrate 101, and a crystalline silicon film 105 is formed. This crystal growth proceeds randomly in a direction perpendicular to the glass substrate 101. Such a crystallization process will be referred to as vertical growth here. If necessary, the crystallinity of the crystalline silicon film 105 may be further improved by performing optical annealing with laser light or infrared light or thermal annealing after the crystallization step. Also, optical annealing and thermal annealing may be used together.

However, when the laser annealing is performed, the crystalline silicon film 105 is effectively supplied with heat energy by the laser light to the crystalline silicon film 105.
The film thickness of the amorphous silicon film 103, which is the starting film of
Hereinafter, it is preferable to set it to about 700Å to 800Å.

Next, by heating in an oxidizing atmosphere containing fluorine atoms, a thermal oxide film 106 is formed on the surface of the crystalline silicon film 105 to a film thickness of 200 to 500 Å. In this embodiment, the thermal oxide film 106 is formed to a thickness of about 200 Å by heating at a temperature of 600 ° C. for 4 hours in an atmosphere in which 400 ppm of NF ₃ is added to oxygen gas. As a result,
The film thickness of the crystalline silicon film 105 is about 700 Å, but is about 600 Å. Since the crystalline silicon film 105 finally forms the active layer of the TFT, the amorphous silicon film 103 is considered in consideration of the film thickness of the oxide film 106 so that an active layer having a necessary thickness can be obtained. It is necessary to determine the film thickness of.

The thermal oxide film 10 is formed on the surface of the crystalline silicon film 105.
As 6 is formed, unbonded Si is generated. This excess Si is caused by the thermal oxide film 106 and the crystalline silicon film 1.
05 from the interface with the crystalline silicon film 105 to diffuse into the inside of the crystalline silicon film 105 and combine with the dangling bond of Si existing in the crystal grain boundary to reduce the defect density of the crystal grain boundary of the crystalline silicon film 105. Also, in the subsequent manufacturing process involving heating,
Si, which is passivated with defects, does not easily separate from the crystalline silicon film 105 like H does.
The crystalline silicon film 105 is suitable as a material for a semiconductor device such as a TFT.

On the surface of the crystalline silicon film 105, the convex portions are rounded and flattened due to the difference in oxidation rate between the convex portions and the concave portions. When the crystalline silicon film 105 is irradiated with laser light, a ridge is formed on the surface of the crystalline silicon film 105. Therefore, the crystalline silicon after the thermal oxidation process is made so that the ridge can be planarized and removed as much as possible. The thermal oxidation process conditions such as the thickness of the thermal oxide film 106 and the NF ₃ gas concentration may be set in consideration of the film thickness of the film 105.

As shown in FIG. 1D, the thermal oxide film 106 is removed by etching. At this time, an etching solution or etching gas having a high etching rate of silicon oxide and silicon is used. In this embodiment, the thermal oxide film 106 is removed by wet etching using a hydrofluoric acid-based etchant such as buffer hydrofluoric acid.

Then, the crystalline silicon film 105 is patterned into an island shape to form an active layer 107 of the TFT. Then, as the gate insulating film 108, a silicon oxide film is formed to a thickness of 1000 Å by the plasma CVD method. Since the surface of the active layer 107 is flattened in the thermal oxidation process, the gate insulating film 108 can be deposited with good coverage.

Next, on the surface of the gate insulating film 108, an aluminum film containing a small amount of scandium (not shown) is formed to a thickness of 6000 Å by the electron beam evaporation method, and then, as shown in FIG.
Patterning is performed as shown in FIG.
9 is formed. Then, an oxide layer 110 is formed by anodizing in the electrolytic solution using the gate electrode 109 as an anode. In this case, the gate electrode 109 is placed in an ethylene glycol solution containing 3% tartaric acid.
Is used as an anode and platinum is used as a cathode, and a voltage is applied to form an anode oxide layer 110 having a dense structure to 200
It is formed to a thickness of 0 °. The film thickness of the anodic oxide 110 can be controlled by the voltage application time.

Next, as shown in FIG.
In order to form the drain regions 111 and 112, the active layer 1 is formed by an ion implantation method or a plasma ion implantation method.
Impurity ions imparting one conductivity type are implanted into 07. n
When forming a channel type TFT, phosphine diluted to 1 to 10% with H ₂ gas is used to inject phosphorus (P) on to the active layer 106. On the other hand, when a p-channel TFT is manufactured, boron (B) ions are implanted using diborane diluted to 1 to 10%.

When the impurity ions are implanted into the active layer 107, the gate electrode 109 and the surrounding anodic oxide 110 function as a mask, and the regions into which the impurity ions are implanted are defined as the source / drains 111 and 112. A region where impurity ions are not implanted is defined as the channel 113. The impurity ion concentration of the source / drain 111, 112 is 3 × 10 ¹⁹ to 1 × 10 ²¹ atoms / c.
Doping conditions such as dose amount and accelerating voltage are controlled so as to be m ³ . After the doping, laser light is irradiated to activate the impurity ions implanted in the source / drain 111, 112.

Next, a silicon oxide film is formed as an interlayer insulating film 114 to a thickness of 7,000 Å by the plasma CVD method. Then, contact holes are formed, and electrodes 115 and 116 connected to the source / drains 111 and 112 are formed of a material containing aluminum as a main component. Finally 300 ℃
Then, hydrogen plasma treatment is performed to complete the thin film transistor shown in FIG. The main purpose of this hydrogen plasma treatment is not passivation of defects in the active layer 107, but passivation of interfaces between the active layer 107 and the electrodes 115 and 116 made of aluminum.

P manufactured according to the manufacturing process of this embodiment
The field-effect mobility of the channel-type TFT did not significantly change before and after the hydrogen plasma treatment. This is not because the thermal oxidation step shown in FIG. 1C does not have the effect of passivation, but as described above, the field effect mobility of the p-channel TFT is not significantly improved only by the hydrogen plasma treatment. As is expected from the above, it is considered that in the p-channel TFT, passivation of defects at the crystal grain boundaries of the active layer 107 is not the best means for improving the field effect mobility.

On the other hand, the n-channel TFT manufactured according to the manufacturing process of this embodiment has a field effect mobility of 200 cm ² · V ⁻¹ · s before the hydrogen plasma treatment.
It was ^-1, but after performing the hydrogen plasma treatment, the field effect mobility was only under increased 10 to 20%. Conventionally, an n-channel TFT cannot be put into practical use unless it is subjected to hydrogen plasma treatment, but as in the present embodiment, it can be put into practical use only by adding NF ₃ and performing thermal oxidation treatment.
It suggests that a channel type TFT can be manufactured.

That is, in the hydrogen plasma treatment, there are not so many defects at the crystal grain boundaries of the active layer 107 that are passivated by hydrogen, and most of the defects at the crystal grain boundaries are as shown in FIG.
In the thermal oxidation step shown in (C), it is shown that it is passivated. Therefore, most of the defects that are passivated by the hydrogen plasma treatment of the present embodiment are defects that occur after the thermal oxidation process, and the electrode 11 is mainly used.
This is a defect that occurred when forming 5, 116.

Further, in this embodiment, defects in the crystal grain boundaries of the active layer 107 are passivated with Si. Si
Since H does not easily separate from the active layer due to thermal influence like H, it is possible to form a highly reliable TFT having excellent heat resistance.

Example 2 FIGS. 3 and 4 show T of this example.
It is explanatory drawing of the manufacturing process of FT, and is sectional drawing for every process. In this embodiment, a TFT is manufactured using a silicon film crystallized by utilizing the catalytic action of a metal element that promotes crystallization of silicon. In this embodiment, nickel is used as the metal element.

As shown in FIG. 3A, the glass substrate 20
On 1 (Corning 1737, strain point 667 ° C.), a silicon oxide film is formed as a base film 202 to a thickness of 3000 Å by plasma CVD or low pressure thermal CVD. Next, a substantially intrinsic amorphous silicon film 203 is formed to a thickness of 700 Å to 1000 Å by plasma CVD or low pressure thermal CVD. Here, the thickness of the amorphous silicon film 103 is 1000 Å
And

UV light is applied to the surface of the amorphous silicon film 203 in an oxidizing atmosphere to form an oxide film (not shown) with a thickness of several 20 Å on the surface. A solution containing nickel element is applied to the surface of the oxide film. The oxide film is for improving the wettability of the surface of the amorphous silicon film 203 and suppressing the repulsion of the solution.

A mask film 204 having an opening portion 204a made of a silicon oxide film having a thickness of 1500 Å is formed on the surface of an oxide film (not shown). The opening portion 204a has a slit-like shape having a long side in a direction perpendicular to the paper surface. It is appropriate that the width of the opening portion 204a is 20 μm or more, while the dimension in the longitudinal direction is appropriately determined according to the substrate dimension and the like.

Next, a nickel acetate solution containing about 1 to 100 ppm of nickel element is applied to the nickel acetate solution by a spinner and dried to form a nickel layer 2.
05 is formed. Although the nickel layer 205 does not necessarily form a perfect film, in this state, the nickel element is contained in the surface of the amorphous silicon film 203 through the oxide film (not shown) in the opening portion 204a of the mask film 204. Held in contact with.

Next, the amorphous silicon film 203 is crystallized by heating at 620 ° C. for 4 hours to form a crystalline silicon film 206. By heating, in the amorphous silicon film 203, crystals grow vertically from the surface of the region 206a exposed in the opening 204a of the mask film 204 toward the base film 202, so that the region 206a is a vertically grown region. Becomes Eventually, in the region 206b, the vertical growth region 206a
Starting from the crystalline silicon film 20 as indicated by an arrow.
6 Crystal growth proceeds parallel to the surface. The crystallization process in which crystals grow in one direction is called lateral growth. Therefore,
A region 206b of the crystalline silicon film 206 is a lateral growth region.

Next, as shown in FIG. 3C, after the mask film 204 made of a silicon oxide film is removed, the surface of the crystalline silicon film 206 is heated by heating in an oxidizing atmosphere containing fluorine atoms. Thermal oxide film 207 200-500 Å
To a film thickness of If necessary, the crystallinity of the crystalline silicon film 105 may be further improved by performing optical annealing with laser light or infrared light or thermal annealing before the thermal oxidation step. Also, optical annealing and thermal annealing may be used together.

In order to carry out the thermal oxidation step, 600 NF ₃ gas was added in an oxygen atmosphere in an amount of 450 ppm.
The thermal oxide film 207 is heated to 500 ° C. for 12 hours.
It is formed to a thickness of about Å. As a result, the crystalline silicon film 20
The film thickness of No. 6 was about 1000 Å, but becomes about 750 Å.

The thermal oxide film 20 is formed on the surface of the crystalline silicon film 206.
As 7 is formed, unbonded Si is generated. The Si atoms bond with dangling bonds of Si at the crystal grain boundaries of the crystalline silicon film 206, and the defects in the crystalline silicon film 206 are passivated. 1000
For the crystalline silicon film 206 having a thickness of Å, the silicon oxide film 1
The crystalline silicon film 20 is formed by forming 06 about 500Å.
The defect density of the crystal grain boundary of No. 6 can be sufficiently reduced.

Next, as shown in FIG. 3D, the thermal oxide film 207 is removed by etching. At this time, an etching solution or etching gas having a high etching rate of silicon oxide and silicon is used. In this embodiment, the thermal oxide film 106 is removed by wet etching using a hydrofluoric acid-based etchant such as buffer hydrofluoric acid.

Next, as shown in FIG. 3E, the crystalline silicon film 206 is etched into an island shape to form the active layer 2 of the TFT.
08 is formed. At this time, the active layer 208 may be composed of only the lateral growth region 206b. Active layer 2
Silicon oxide film 209 forming a gate insulating film on the surface of 08
Is formed by plasma CVD or low pressure CVD. Further, the gate electrode 210 is formed on the surface of the silicon oxide film 209.
The aluminum film forming the
Deposit to a thickness of Å. If 0.2% by weight of scandium is contained in advance in aluminum, generation of hillocks and whiskers can be suppressed in the subsequent heating step and the like.

Next, the surface of the aluminum film is anodized to form a dense anodic oxide (not shown) to be extremely thin. Next, a resist mask 211 is formed on the surface of the aluminum film. At this time, since a dense anodic oxide not shown is formed on the surface of the aluminum film, the mask 21
1 can be formed in close contact with each other. Next, using the resist mask 211, the aluminum film is etched to form a gate electrode 210 as shown in FIG.

As shown in FIG. 4A, the gate electrode 210 is anodized while leaving the resist mask 211, and a porous anodic oxide 212 is formed to a thickness of 4000 Å. At this time, since the resist mask 208 is in close contact with the surface of the gate electrode 210, the porous anodic oxide 212 is formed only on the side surface of the gate electrode 210.

Next, as shown in FIG. 4B, after removing the resist mask 211, the gate electrode 210 is anodized again in an electrolytic solution to form a dense anodic oxide 213.
Is formed to a thickness of 1000 °.

The anodic oxides may be selectively made by changing the electrolytic solution used. When the porous anodic oxide 212 is formed, citric acid, oxalic acid, chromic acid or sulfuric acid is used in 3 parts.
An acidic solution containing ~ 20% may be used. On the other hand, in the case of forming the dense anodic oxide 213, an electrolytic solution in which the pH of the ethylene glycol solution containing tartaric acid, boric acid or nitric acid is adjusted to about 7 may be used.

As shown in FIG. 4C, the gate electrode 21
0 and its surrounding porous anodic oxide 212 and dense anodic oxide 213 are used as a mask to etch the silicon oxide film 209 to form a gate insulating film 214.

As shown in FIG. 4D, after removing the porous anodic oxide 212, the gate electrode 210, the dense anodic oxide 213, and the gate insulating film 214 are used as a mask by an ion doping method. Impurity imparting conductivity type is implanted into the active layer 208. In this embodiment, phosphine is used as a doping gas to dope phosphorus (P) ions in order to form an n-channel TFT. During the doping, the conditions such as the dose amount and the acceleration voltage are controlled so that the gate insulating film 212 functions as a semitransparent mask.

As a result of doping, phosphorus ions are implanted at a high concentration in a region not covered with the gate insulating film 212,
Source / drain 215, 216 are formed. Also,
In the region covered only by the gate insulating film 214, phosphorus ions are implanted at a low concentration, and the low concentration impurity region 217,
218 is formed. Since impurities are not injected into the region directly below the gate electrode 210, the channel 219 is formed. After the doping step, thermal annealing, laser annealing or the like is performed to activate the doped phosphorus ions.

Since the low-concentration impurity regions 217 and 218 function as high-resistance regions, they contribute to the reduction of off current.
Particularly, the low concentration impurity region 218 on the drain 216 side is L
It is called DD. Further, by sufficiently thickening the dense anodic oxide 212, an offset structure in which the impurity region is displaced from the end face of the gate electrode 210 can be formed, and thus the off current can be further reduced.

As shown in FIG. 4E, plasma CVD
A silicon oxide film as an interlayer insulator 220 by
A film is formed to a thickness of 0 °. Note that as the interlayer insulator 220, a single-layer film of a silicon nitride film or a stacked film of a silicon oxide film and a silicon nitride film may be formed instead of the single-layer film of a silicon oxide film. Next, the interlayer insulator 220 made of a silicon oxide film is etched by a known etching method to form contact holes in the source / drain 215 and 216, respectively. Next, an aluminum film is formed to a thickness of 4000 Å by a sputtering method and is patterned to form electrodes 221 and 222 in the contact holes of the source / drain 215 and 216.

Finally, heat treatment is performed at a temperature of 300 ° C. in a hydrogen atmosphere. Through the above steps, a TFT having an LDD structure is manufactured. Note that this hydrogen plasma treatment does not passivate defects in the active layer 208, but
Electrodes 213 and 21 made of active layer 107 and aluminum
The main purpose is passivation of the interface with 4.

N produced according to the production process of this embodiment
The channel-type TFT has a field-effect mobility of 1 before the hydrogen plasma treatment after the hydrogen plasma treatment.
The increase was only 0 to 20%. This is traditionally
The n-channel TFT is not practical without hydrogen plasma treatment, but only thermal oxidation treatment with NF ₃ is added.
This suggests that defects in the crystal grain boundaries of the active layer 208 are effectively passivated.

[Embodiment 3] In this embodiment, an example of manufacturing a CMOS TFT in which an n-channel TFT and a p-channel TFT are complementarily combined is shown. FIG. 5 is an explanatory diagram of the manufacturing process of the TFT of this embodiment. As shown in FIG. 5A, a glass substrate (coning 1737) 301 is used.
An underlying film 3 made of a silicon oxide film having a thickness of 2000 Å
An intrinsic (I-type) amorphous silicon film is formed to a thickness of 700 Å by the plasma CVD method or the low pressure thermal CVD method in which 02 is formed. Then, the amorphous silicon film is crystallized by the method shown in Examples 1 and 2 or an appropriate crystallization method such as heat treatment or laser irradiation to form a crystalline silicon film 303.

As shown in FIG. 5B, thermal oxidation is performed at a temperature of 600 ° C. for 2 hours in an oxygen atmosphere having a concentration of NF ₃ of 400 ppm to form a thermal oxide film 304 with a thickness of about 200 Å. Then, the defects at the crystal grain boundaries of the crystalline silicon film 303 are passivated with Si. As a result, the crystalline silicon film 303 is suitable for a semiconductor material such as TFT.

Next, after removing the thermal oxide film 106 using a hydrofluoric acid-based etchant such as buffer hydrofluoric acid, the crystalline silicon film 303 is patterned into an island shape to form the active layers 305 and 306, respectively. Form. Further, a silicon oxide film 307 forming a gate insulating film is deposited to a thickness of 1500 Å by plasma CVD. The active layer 30
5 constitutes an n-channel TFT, and the active layer 306 constitutes a p-channel TFT.

Next, the gate electrode 30 is formed by the sputtering method.
An aluminum film constituting 8,309 is deposited to a thickness of 4000 Å. The aluminum film is made to contain 0.2 wt% of scandium in advance to suppress the generation of hillocks and whiskers. Next, the aluminum film is anodized in an electrolytic solution to form a dense anodic oxide film 3 of about 100 Å on the surface.
00 is formed. A photoresist mask 310 is formed on the surface of the anodic oxide film, and the aluminum film is patterned.
To form gate electrodes 308 and 309, respectively.

Further, the gate electrodes 308 and 309 are anodized again while the photoresist mask 310 is still on to form anodic oxides 311 and 312. The electrolytic solution contains 3 to 2 citric acid, oxalic acid, chromic acid or sulfuric acid.
An acidic solution containing 0% may be used. In this example, a 3% oxalic acid aqueous solution is used. Gate electrodes 905, 9
In the state where the photoresist mask 310 and the anodic oxide film 300 exist on the surface of 06, the gate electrodes 308, 3
The porous anodic oxides 311 and 312 are formed only on the side surface of 09. The growth distance of the porous anodic oxides 311 and 312 can be controlled by the treatment time of anodic oxidation, and this growth distance determines the length of the low concentration impurity region (LDD region). In this example, the porous anodic oxide 3 was used.
Grow 11, 312 to a length of 7,000 Å.

Next, after removing the photoresist mask 310, the gate electrodes 308 and 309 are again anodized to form dense and strong anodic oxide films 313 and 314 as shown in FIG. 5 (E). To do. In this example, a 3% tartaric acid ethylene glycol solution was used as an electrolytic solution after being neutralized to pH 6.9 with aqueous ammonia.

Next, phosphorus ions are implanted into the island-shaped active layers 305 and 306 by an ion doping method using the gate electrodes 308 and 309 and the porous anodic oxides 311 and 312 as masks. Hydrogen as the doping gas
Use phosphine diluted to 10%. Doping is performed with an acceleration voltage of 60 to 90 kV and a dose amount of 1 × 1.
It is set to 0 ¹⁴ to 8 × 10 ¹⁵ atoms / cm ² . In this embodiment, the acceleration voltage is 80 kV and the dose amount is 1 × 1.
It is set to 0 ¹⁵ atoms / cm ² .

At this time, phosphorus ions are used as the gate electrode 30.
8, 309 and porous anodic oxides 311, 312 are not permeated, but they are permeated through the gate insulating film 307 and implanted into the island-shaped silicon 305, 306. As a result, FIG. 5 (E)
As shown in FIG. 5, n type impurity regions 315 to 318 are formed respectively.

As shown in FIG. 5 (F), after removing the dense anodic oxide film 300 with buffer-hydrofluoric acid, a porous anodic oxide 31 is formed with a mixed acid of phosphoric acid, acetic acid and nitric acid.
Remove 1, 312. Porous anodic oxide 311, 3
Since 12 can be easily removed, the dense and strong anodic oxides 313 and 314 are not etched.

Then, phosphorus ions are doped again. The acceleration voltage is 60 to 90 kV, and the dose is 1 × 10 ¹² to
It is set to 1 × 10 ¹⁴ atoms / cm ² . In this embodiment, the acceleration voltage is 80 kV and the dose is 1 × 10 ¹⁴ atoms / cm ^2.
And At this time, phosphorus ions are transferred to the gate electrodes 308, 3
09 is not transmitted, but is transmitted through the gate insulating film 307,
It is injected into the active layers 305 and 306. Therefore, the region where the phosphorus ions are implanted twice is the n-type high-concentration impurity region 319.
.About.322, and the region where phosphorus ions are once implanted is n
To become the low concentration impurity regions 323 to 326 of the mold.

As shown in FIG. 5G, after covering a region to be an n-channel TFT with polyimide or a heat resistant resist 327, boron is added in order to reverse the conductivity type of the active layer 306 from n type to p type. Ions are ion-doped.
Diborane diluted to about 1 to 10% with hydrogen is used as a doping gas, the acceleration voltage is set to 80 kV, and the dose amount of boron is set to 2 × 10 ¹⁵ atoms / cm ² . The region covered with the polyimide or the heat resistant resist 327 remains as n-type because boron is not implanted. Therefore, in the active layer 305, the high-concentration impurity regions 319 and 320 respectively correspond to the source and drain of the n-channel TFT, and the region 328 immediately below the gate electrode 308 is not implanted with phosphorus ions and boron ions, so that the intrinsic regions are not formed. Until now,
It corresponds to the channel of the TFT.

In the boron ion doping, since the amount of boron implanted is large, the low concentration impurity regions (LDD regions) are not formed, but only the p-type high concentration impurity regions 329 and 330 are formed. The high-concentration impurity regions 329 and 330 correspond to the source and drain of the p-channel TFT, respectively.
Further, the region 331 immediately below the gate electrode 309 is left as an intrinsic channel because it is not implanted with phosphorus ions and boron ions and becomes a channel.

Then, the resist 327 is removed, and the structure shown in FIG.
As shown in (H), a silicon oxide film having a thickness of 1 μm is formed as an interlayer insulating film 332 by a plasma CVD method, and a contact hole is formed thereon. On this contact hole, source / drain electrodes and wirings 333 to 335 are formed of a metal material, for example, a multilayer film of titanium and aluminum. Finally, in a hydrogen atmosphere at 350 ° C,
Heat treatment is performed for 2 hours. Through the above steps, CMOS
The thin film transistor is completed.

In this embodiment, since a CMOS structure in which an n-type TFT and a p-type transistor are complementarily combined is formed, it is possible to reduce the power consumption when driving the TFT. Also,
Channel 328 and drain 320 of n-channel TFT
Since the low-concentration impurity region 321 is provided between the two, it is possible to prevent a high electric field from being generated between the channel 328 and the drain 320.

The conditions of the thermal oxidation process to which NF ₃ is added are not limited to those described in Examples 1 to 3 above, and the distortion and deformation of the substrate on which the TFT formed in the thermal oxidation process is formed. In order to keep the temperature within the allowable range, the concentration of NF _{3 in} the oxygen atmosphere is determined so that the thermal oxide film grows to a film thickness of several hundred liters by heating at a temperature below the strain point of the glass substrate for several hours. do it.

Further, in Examples 1 to 3, since Corning 1737 glass having a strain point of 667 ° C. was used as the glass substrate, the heating temperature in the thermal oxidation step was 600 ° C., for example, Corning 7059. When glass is used, the strain point is 593 ° C, so
The heating temperature in the thermal oxidation step may be about 500 to 550 ° C.

[0089]

In the method of manufacturing a semiconductor device according to the present invention, since the thermal oxide film is grown in an oxidizing atmosphere to which a fluorine compound is added, the temperature is lower than the strain point of the glass substrate for several hours. By heating for 10 hours or more, it is possible to grow a thermal oxide film to a film thickness of several hundred Å. Further, by growing the thermal oxide film, excess S
Since i is generated and defects in crystal grain boundaries of the crystalline silicon film can be passivated with Si, it is possible to eliminate the need for hydrogen plasma treatment.

Further, since the surface of the crystalline silicon film can be flattened by the thermal oxidation step, even if the step of irradiating the laser beam to obtain the crystalline silicon film is adopted, it is formed of the deposited film. Since the gate insulating film can be formed with good coverage, the interface state between the gate insulating film and the active layer can be lowered. Since the crystalline silicon film is irradiated with laser light and has excellent crystallinity, the mobility of the semiconductor device can be further improved.

Therefore, like a glass substrate, 1000 ° C.
It becomes possible to manufacture an insulating gate type semiconductor device such as a TFT having high mobility and high reliability on a substrate that is difficult to process at a high temperature.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of a manufacturing process of a TFT of Example 1.

FIG. 2 is an explanatory diagram of a manufacturing process of the TFT of Example 1.

FIG. 3 is an explanatory diagram of a manufacturing process of the TFT of Example 2.

FIG. 4 is an explanatory diagram of a manufacturing process of the TFT of Example 2.

FIG. 5 is an explanatory diagram of a manufacturing process of the TFT of Example 3.

[Explanation of symbols]

 101, 201, 301 ... Glass substrate 102, 202, 302 ..... Base film 103, 203 ..... Amorphous silicon film 104, 205 ........ Nickel layer 105, 206, 303 ... Crystalline silicon film 106, 207, 304 ... Thermal oxide film 107, 208, 305, 306 ... Active layer 108, 214, 307 ... Gate insulating film 109, 210, 308, 309 ... Gate electrode

Claims (7)

[Claims] 1. A step of forming an amorphous silicon film, a step of crystallizing the amorphous silicon film to form a crystalline silicon film, and heating in an oxidizing atmosphere to which a fluorine compound gas is added. And then growing a thermal oxide film on the surface of the crystalline silicon film, removing the thermal oxide film on the surface of the crystalline silicon film, and depositing an insulating film on the surface of the crystalline silicon film. And a method for manufacturing a semiconductor device. 2. A step of forming an amorphous silicon film, irradiating a laser beam to crystallize the amorphous silicon film,
Forming a crystalline silicon film; heating in an oxidizing atmosphere to which a fluorine compound gas is added to grow a thermal oxide film on the surface of the crystalline silicon film; A method of manufacturing a semiconductor device, comprising: a step of removing a thermal oxide film; and a step of depositing an insulating film on the surface of the crystalline silicon film. 3. A method of manufacturing a thin film transistor on a substrate having an insulating surface, the step of forming an amorphous silicon film, and the step of crystallizing the amorphous silicon film to form a crystalline silicon film. A step of growing a thermal oxide film on the surface of the crystalline silicon film by heating in a oxidizing atmosphere to which a fluorine compound gas is added, and a step of removing the thermal oxide film on the surface of the crystalline silicon film, Shaping the crystalline silicon film to form an active layer of a thin film transistor; depositing an insulating film on a surface of the active layer to form a gate insulating film on at least a surface of a channel region; A step of forming a gate electrode on the surface of an insulating film, and a step of implanting impurity ions imparting a conductivity type to the active layer using the gate electrode as a mask to form a source and a drain in a self-aligned manner The method for manufacturing a semiconductor device characterized by having a. 4. A method of manufacturing a thin film transistor on a substrate having an insulating surface, the step of forming an amorphous silicon film, and the step of crystallizing the amorphous silicon film to form a crystalline silicon film. Irradiating the crystalline silicon film with laser light, heating the crystalline silicon film in an oxidizing atmosphere to which a fluorine compound gas is added, and growing a thermal oxide film on the surface of the crystalline silicon film; Of the thermal oxide film on the surface of the conductive silicon film, shaping the crystalline silicon film to form an active layer of a thin film transistor, depositing an insulating film on the surface of the active layer, and forming at least the channel region. A step of forming a gate insulating film on the surface of the gate insulating layer, a step of forming a gate electrode on the surface of the gate insulating film, and implanting impurity ions imparting a conductivity type to the active layer using the gate electrode as a mask. And a step of forming a source and a drain in a self-aligned manner. 5. The method of manufacturing a semiconductor device according to claim 1, wherein the thermal oxide film has a film thickness of 200 to 500 Å. 6. The method according to claim 1, wherein after the step of forming the amorphous silicon film, the concentration of the metal element in the amorphous silicon film is 1 × 10 ^{16 to} 5 × 10 ¹⁹ atoms / cm ³ . A method for manufacturing a semiconductor device, comprising the step of: 7. The metal element according to claim 6, wherein the metal element is F
e, Co, Ni, Ru, Rh, Pd, Os, Ir, C
A method for manufacturing a semiconductor device, comprising at least one element selected from u and Au.