JPH09289183A - Flattening method of semiconductor substrate and its equipment - Google Patents
Flattening method of semiconductor substrate and its equipmentInfo
- Publication number
- JPH09289183A JPH09289183A JP8126543A JP12654396A JPH09289183A JP H09289183 A JPH09289183 A JP H09289183A JP 8126543 A JP8126543 A JP 8126543A JP 12654396 A JP12654396 A JP 12654396A JP H09289183 A JPH09289183 A JP H09289183A
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- substrate
- liquid
- polishing pad
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P80/00—Climate change mitigation technologies for sector-wide applications
- Y02P80/30—Reducing waste in manufacturing processes; Calculations of released waste quantities
Landscapes
- Electrical Discharge Machining, Electrochemical Machining, And Combined Machining (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、例えばシリコンウ
エハ等の半導体基板の表面を平坦化加工する方法及び装
置に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and apparatus for flattening the surface of a semiconductor substrate such as a silicon wafer.
【0002】[0002]
【従来の技術】半導体デバイスの製造プロセス中では、
例えば、ウエハ上に形成した各種の膜の表面を平坦化す
ることが多く行われる。この平坦化が均一に行われない
と膜表面に凹凸が生じ、このためリソグラフィ工程の露
光時に焦点が合わず、微細化が困難となる。そこで、例
えば特開昭62−208868号公報に記載されたよう
に、研磨布(パッド)に研磨液(スラリー)を供給しつ
つ、その研磨布によってウエハの膜表面を研磨する、い
わゆる化学的機械的研磨法(CMP)による平坦化が試
みられている。2. Description of the Related Art During the manufacturing process of semiconductor devices,
For example, the surface of various films formed on a wafer is often flattened. If this flattening is not performed uniformly, unevenness is generated on the film surface, so that the focus is not focused during exposure in the lithography process, and miniaturization becomes difficult. Therefore, as described in, for example, JP-A-62-208868, a so-called chemical machine for polishing a film surface of a wafer with a polishing liquid (slurry) while supplying a polishing liquid (slurry) to the polishing cloth (pad). Has been attempted to be planarized by dynamic polishing (CMP).
【0003】上記公報記載のシリコンウエハの加工方法
においては、ウエハ側が正電位でポリシングパッドが設
けられた研磨定盤である金属板が負電位となるように電
圧を印加し、ポリシング液をパッド上に滴下させながら
ウエハとパッドとを相対回転させてポリシングを行って
いる。In the method of processing a silicon wafer described in the above publication, a voltage is applied so that a metal plate, which is a polishing platen having a polishing pad provided with a positive potential on the wafer side, has a negative potential, and a polishing liquid is applied onto the pad. The wafer and the pad are rotated relative to each other while being dropped, and polishing is performed.
【0004】[0004]
【発明が解決しようとする課題】しかし、上記方法にお
いては、ポリシングパッドが張り付けられた研磨定盤を
マイナス側電極にしており、電流がウエハから均一に流
れ難いという欠点があった。また、この方法のようにウ
エハ側がプラスの場合は、シリコンが溶出して加工除去
速度が速くなるので、加工表面が粗くなるという問題点
があった。However, in the above method, the polishing surface plate to which the polishing pad is attached is used as the negative electrode, and there is a drawback that it is difficult for the current to flow uniformly from the wafer. Further, when the wafer side is positive as in this method, silicon elutes to increase the processing removal rate, which causes a problem that the processed surface becomes rough.
【0005】そこで本発明は、半導体基板の平坦化に際
して、電圧印加による電流が均一に流れ、表面粗さの良
好な加工が可能な方法及び装置を提供することを目的と
する。Therefore, it is an object of the present invention to provide a method and an apparatus capable of processing a current having a uniform surface roughness and a good surface roughness when flattening a semiconductor substrate.
【0006】[0006]
【課題を解決するための手段】上記目的を達成するため
に、本発明は、半導体基板の表面の平坦化加工方法であ
って、前記基板の表面を研磨パッド上に押し付け、前記
基板が負電位で前記研磨パッド上に供給された加工液が
正電位となるように基板と加工液との間に電圧を印加
し、前記加工液を介して前記基板の表面と前記研磨パッ
ドとを相対的に摺動させて、前記基板の表面を平坦化す
ることを特徴とする。この場合、前記加工液としてアル
カリを用いることができ、この加工液のpHを9〜12
の間で変化させるとよい。また、前記印加電圧は10m
V〜500mVであるのが好ましく、さらに、前記加工
液の温度を20℃〜37℃の間で変化させるとよい。In order to achieve the above object, the present invention is a method of flattening a surface of a semiconductor substrate, wherein the surface of the substrate is pressed onto a polishing pad, and the substrate has a negative potential. A voltage is applied between the substrate and the working liquid so that the working liquid supplied onto the polishing pad has a positive potential, and the surface of the substrate and the polishing pad are relatively moved through the working liquid. It is characterized in that the surface of the substrate is flattened by sliding. In this case, an alkali can be used as the working fluid, and the pH of the working fluid is 9-12.
It is good to change between. The applied voltage is 10 m
V to 500 mV is preferable, and the temperature of the working fluid may be changed between 20 ° C and 37 ° C.
【0007】また、本発明は、半導体基板の表面の平坦
化加工装置であって、前記基板を保持する基板保持手段
と、研磨パッドが設けられた研磨定盤と、前記基板と前
記研磨パッド上に供給された加工液との間に電圧を印加
する電圧印加手段と、を備え、前記基板保持手段により
前記基板の表面を前記研磨パッド上に押し付け、前記電
圧印加手段により前記基板を負電位にすると共に前記加
工液を正電位とし、前記基板保持手段及び前記研磨定盤
により前記加工液を介して前記基板の表面と前記研磨パ
ッドとを相対的に摺動させて、前記基板の表面を平坦化
することを特徴とする。この場合、前記電圧印加手段に
おいて前記加工液に接触する電極が白金であるとよい。The present invention is also an apparatus for flattening the surface of a semiconductor substrate, comprising substrate holding means for holding the substrate, a polishing platen provided with a polishing pad, the substrate and the polishing pad. Voltage applying means for applying a voltage between the substrate and the processing liquid supplied to the polishing pad, the substrate holding means presses the surface of the substrate onto the polishing pad, and the voltage applying means brings the substrate to a negative potential. At the same time, the working liquid is set to a positive potential, and the surface of the substrate is flattened by relatively sliding the surface of the substrate and the polishing pad through the working liquid by the substrate holding means and the polishing platen. It is characterized by In this case, the electrode in contact with the working fluid in the voltage applying means may be platinum.
【0008】[0008]
【作用】本発明においては、半導体基板がマイナス側で
研磨パッド上の加工液がプラス側となるように電圧を印
加すると、その電気作用と加工液の化学作用とが複合し
た電気化学作用により基板の表面が軟質化され、研磨パ
ッド上での摺動の摩擦力により基板の表面が研磨除去加
工される。加工液にプラス側の電圧を直接印加すること
により、加工液からの電流の均一性が保たれると共に、
基板側をマイナスで加工液側をプラスとすることによ
り、基板材料の溶出を少なくして表面粗さを良好にする
ことができる。In the present invention, when a voltage is applied so that the semiconductor substrate is on the negative side and the working liquid on the polishing pad is on the positive side, the substrate is operated by an electrochemical action that is a combination of the electric action and the chemical action of the working liquid. The surface of the substrate is softened, and the surface of the substrate is polished and removed by the frictional force of sliding on the polishing pad. By directly applying the positive voltage to the working fluid, the current from the working fluid is kept uniform and
By making the substrate side negative and the processing liquid side positive, it is possible to reduce the elution of the substrate material and improve the surface roughness.
【0009】[0009]
【発明の実施の形態】以下、本発明の実施の形態におけ
る半導体ウエハの平坦化加工方法及び装置について図1
を参照して説明する。BEST MODE FOR CARRYING OUT THE INVENTION A semiconductor wafer flattening method and apparatus according to an embodiment of the present invention will be described below with reference to FIG.
This will be described with reference to FIG.
【0010】図1は装置の概略図である。同図におい
て、研磨定盤であるテーブル1上に研磨パッド2が張り
付けられ、この研磨パッド2上にノズル3からアルカリ
の加工液4が供給される。半導体ウエハとしてのシリコ
ンウエハ5はチャック6により固定保持され、荷重Pを
加えてウエハ5の表面が研磨パッド2上に押し付けられ
る。そして、電源7の一方の電極8aがウエハ5に接触
されると共に他方の電極8bが加工液4に直接浸されて
おり、ウエハ5側がマイナスで加工液4側がプラスとな
るように電圧が印加される。なお、加工液4に浸される
電極8bは白金とし、溶出による金属汚染を少なくす
る。FIG. 1 is a schematic diagram of the apparatus. In the figure, a polishing pad 2 is attached to a table 1 which is a polishing platen, and an alkaline working liquid 4 is supplied from the nozzle 3 onto the polishing pad 2. A silicon wafer 5 as a semiconductor wafer is fixedly held by a chuck 6, and a load P is applied to press the surface of the wafer 5 onto the polishing pad 2. Then, one electrode 8a of the power source 7 is in contact with the wafer 5 and the other electrode 8b is directly immersed in the working liquid 4, and a voltage is applied so that the wafer 5 side is negative and the working liquid 4 side is positive. It The electrode 8b immersed in the working liquid 4 is made of platinum to reduce metal contamination due to elution.
【0011】加工液4を研磨パッド2上に供給しなが
ら、ウエハ5の表面を研磨パッド2上に押し付け、ウエ
ハ5をマイナス電位にすると共に加工液4をプラス電位
にして、テーブル1(及びチャック6)を回転させる。
このとき、ウエハ5側をマイナスにすることにより、ウ
エハ5からのシリコンの溶出は起こらず、直接プラス電
位とされた加工液4からウエハ5に電流が均一に流れる
ことによる発熱により、加工液4のアルカリに含まれる
OH基の反応が生じる。これにより、ウエハ5の表面の
研磨除去の作用が緩やかに起こり、ウエハ5の表面の粗
さを良くすることができる。なお、ウエハ5の被加工面
はポリシリコンでも単結晶でも可能である。While supplying the processing liquid 4 onto the polishing pad 2, the surface of the wafer 5 is pressed against the polishing pad 2 so that the wafer 5 has a negative potential and the processing liquid 4 has a positive potential, and the table 1 (and the chuck). 6) Rotate.
At this time, by making the side of the wafer 5 negative, the elution of silicon from the wafer 5 does not occur, and the working liquid 4 is heated by the uniform flow of current from the working liquid 4 that is directly set to the positive potential to the wafer 5. The reaction of the OH group contained in the alkali occurs. As a result, the action of polishing and removing the surface of the wafer 5 gradually occurs, and the surface roughness of the wafer 5 can be improved. The surface to be processed of the wafer 5 may be polysilicon or single crystal.
【0012】加工液4のアルカリのpHを変化させる
と、化学作用を制御することが可能となる。ここで、ア
ルカリのpHは9〜12の間で変化させるのがよく、こ
れより小さいと加工能率が低く、大きいと表面が粗くな
る。また、加工液4とウエハ5との間に印加する電圧は
10mV〜500mV程度とするのがよく、これより小
さいと加工能率が低く、大きいと表面が粗くなり、特に
望ましいのは100mV〜200mV程度である。さら
に、加工液4の温度は20℃〜37℃の間でコントロー
ルするのがよく、これより低いと加工能率が下がり、高
いと表面が粗くなる。By changing the pH of the alkali of the working liquid 4, it becomes possible to control the chemical action. Here, it is preferable to change the pH of the alkali between 9 and 12, and if it is smaller than this, the processing efficiency is low, and if it is larger, the surface becomes rough. The voltage applied between the processing liquid 4 and the wafer 5 is preferably about 10 mV to 500 mV. If it is smaller than this, the processing efficiency is low, and if it is larger, the surface becomes rough, and particularly desirable is about 100 mV to 200 mV. Is. Furthermore, the temperature of the working fluid 4 is preferably controlled between 20 ° C. and 37 ° C., and if it is lower than this, the working efficiency decreases, and if it is higher, the surface becomes rough.
【0013】[0013]
〔実施例1〕図1の実施形態のような装置において、ウ
エハ5側をマイナス100mV、押圧力300g/cm
2 とし、加工液4をpH10.5、温度30℃として加
工したところ、除去速度は0.2μm/minで、表面
粗さは0.1nmRMSが得られた。Example 1 In the apparatus as in the embodiment of FIG. 1, the wafer 5 side is minus 100 mV and the pressing force is 300 g / cm.
When the processing liquid 4 was processed to have a pH of 10.5 and a temperature of 30 ° C., the removal rate was 0.2 μm / min and the surface roughness was 0.1 nm RMS.
【0014】〔実施例2〕同様な装置において、ウエハ
5側をマイナス200mV、押圧力300g/cm2 と
し、加工液4をpH10.5、温度30℃として加工し
たところ、除去速度は0.1μm/minで、表面粗さ
は0.05nmRMSが得られた。[Embodiment 2] In a similar apparatus, the wafer 5 side was processed to a minus 200 mV, a pressing force of 300 g / cm 2 , the working liquid 4 at a pH of 10.5 and a temperature of 30 ° C., and the removal rate was 0.1 μm. / Min, a surface roughness of 0.05 nm RMS was obtained.
【0015】〔実施例3〕同様な装置において、ウエハ
5側をマイナス200mV、押圧力300g/cm2 と
し、加工液4をpH10.5、温度20℃として加工し
たところ、除去速度は0.05μm/minで、表面粗
さは0.02nmRMSが得られた。[Embodiment 3] In a similar apparatus, the wafer 5 side was processed to a minus 200 mV, a pressing force of 300 g / cm 2 , the processing liquid 4 at a pH of 10.5 and a temperature of 20 ° C., and the removal rate was 0.05 μm. / Min, a surface roughness of 0.02 nm RMS was obtained.
【0016】〔実施例4〕同様な装置において、ウエハ
5側をマイナス200mV、押圧力300g/cm2 と
し、加工液4をpH12、温度30℃として加工したと
ころ、除去速度は0.3μm/minで、表面粗さは
0.2nmRMSが得られた。[Embodiment 4] In a similar apparatus, the wafer 5 side was processed at a negative pressure of 200 mV and a pressing force of 300 g / cm 2 , and the processing liquid 4 was processed at a pH of 12 and a temperature of 30 ° C. The removal rate was 0.3 μm / min. Then, a surface roughness of 0.2 nm RMS was obtained.
【0017】以上、本発明の実施の形態について説明し
たが、本発明は上記実施形態に限定されることなく、本
発明の技術的思想に基づいて各種の有効な変更並びに応
用が可能である。例えば、平坦化すべき半導体基板の表
面の特性に応じて、加工液の種類や研磨パッドの材質等
が、適宜に選択され得るのは言うまでもない。Although the embodiments of the present invention have been described above, the present invention is not limited to the above embodiments, and various effective modifications and applications are possible based on the technical idea of the present invention. For example, it goes without saying that the type of processing liquid, the material of the polishing pad, etc. can be appropriately selected according to the characteristics of the surface of the semiconductor substrate to be planarized.
【0018】[0018]
【発明の効果】以上説明したように、本発明によれば、
半導体基板がマイナス側で研磨パッド上の加工液がプラ
ス側となるように電圧を印加することによって、加工液
から基板に電流を極めて均一に流すことができると共
に、基板材料の溶出を少なくして表面粗さを極めて良好
にすることができる。また、砥粒が含まれた加工液を用
いなくてよいので、汚染の少ない研磨加工が可能とな
る。これによって、均一性に優れた高精度な平坦化が可
能になって歩留りロスを低減することができる。As described above, according to the present invention,
By applying a voltage so that the semiconductor substrate is on the negative side and the working liquid on the polishing pad is on the positive side, a current can be made to flow from the working liquid to the substrate extremely uniformly, and the elution of substrate material is reduced. The surface roughness can be made extremely good. Further, since it is not necessary to use a processing liquid containing abrasive grains, polishing processing with less contamination becomes possible. As a result, highly uniform flattening with excellent uniformity can be achieved and yield loss can be reduced.
【図1】本発明の実施形態における半導体ウエハの平坦
化加工装置の概略図である。FIG. 1 is a schematic diagram of a semiconductor wafer flattening apparatus according to an embodiment of the present invention.
1 テーブル(研磨定盤) 2 研磨パッド 3 ノズル 4 加工液 5 シリコンウエハ 6 チャック 7 電源 8a、8b 電極 1 table (polishing surface plate) 2 polishing pad 3 nozzle 4 working liquid 5 silicon wafer 6 chuck 7 power supply 8a, 8b electrode
Claims (7)
って、 前記基板の表面を研磨パッド上に押し付け、前記基板が
負電位で前記研磨パッド上に供給された加工液が正電位
となるように前記基板と前記加工液との間に電圧を印加
し、前記加工液を介して前記基板の表面と前記研磨パッ
ドとを相対的に摺動させて、前記基板の表面を平坦化す
ることを特徴とする半導体基板の平坦化加工方法。1. A method of flattening a surface of a semiconductor substrate, wherein the surface of the substrate is pressed onto a polishing pad, and the processing liquid supplied to the polishing pad at a negative potential of the substrate has a positive potential. Voltage is applied between the substrate and the working liquid so that the surface of the substrate and the polishing pad are relatively slid through the working liquid to flatten the surface of the substrate. A method of planarizing a semiconductor substrate, which comprises:
とする請求項1記載の半導体基板の平坦化加工方法。2. The method of planarizing a semiconductor substrate according to claim 1, wherein the processing liquid is an alkali.
させることを特徴とする請求項1記載の半導体基板の平
坦化加工方法。3. The method of planarizing a semiconductor substrate according to claim 1, wherein the pH of the processing liquid is changed between 9 and 12.
あることを特徴とする請求項1記載の半導体基板の平坦
化加工方法。4. The method of planarizing a semiconductor substrate according to claim 1, wherein the applied voltage is 10 mV to 500 mV.
で変化させることを特徴とする請求項1記載の半導体基
板の平坦化加工方法。5. The method of planarizing a semiconductor substrate according to claim 1, wherein the temperature of the processing liquid is changed between 20 ° C. and 37 ° C.
って、 前記基板を保持する基板保持手段と、研磨パッドが設け
られた研磨定盤と、前記基板と前記研磨パッド上に供給
された加工液との間に電圧を印加する電圧印加手段と、
を備え、 前記基板保持手段により前記基板の表面を前記研磨パッ
ド上に押し付け、前記電圧印加手段により前記基板を負
電位にすると共に前記加工液を正電位とし、前記基板保
持手段及び前記研磨定盤により前記加工液を介して前記
基板の表面と前記研磨パッドとを相対的に摺動させて、
前記基板の表面を平坦化することを特徴とする半導体基
板の平坦化加工装置。6. An apparatus for flattening a surface of a semiconductor substrate, comprising substrate holding means for holding the substrate, a polishing platen provided with a polishing pad, the substrate and the polishing pad. Voltage applying means for applying a voltage between the working liquid,
The substrate holding means presses the surface of the substrate onto the polishing pad, the voltage applying means brings the substrate to a negative potential and the working liquid has a positive potential, and the substrate holding means and the polishing platen are provided. By relatively sliding the surface of the substrate and the polishing pad through the working liquid,
An apparatus for planarizing a semiconductor substrate, which planarizes the surface of the substrate.
接触する電極が白金であることを特徴とする請求項6記
載の半導体基板の平坦化加工装置。7. An apparatus for planarizing a semiconductor substrate according to claim 6, wherein the electrode in contact with the working liquid in the voltage applying means is platinum.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8126543A JPH09289183A (en) | 1996-04-23 | 1996-04-23 | Flattening method of semiconductor substrate and its equipment |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8126543A JPH09289183A (en) | 1996-04-23 | 1996-04-23 | Flattening method of semiconductor substrate and its equipment |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH09289183A true JPH09289183A (en) | 1997-11-04 |
Family
ID=14937792
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8126543A Withdrawn JPH09289183A (en) | 1996-04-23 | 1996-04-23 | Flattening method of semiconductor substrate and its equipment |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH09289183A (en) |
-
1996
- 1996-04-23 JP JP8126543A patent/JPH09289183A/en not_active Withdrawn
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6361413B1 (en) | Apparatus and methods for conditioning polishing pads in mechanical and/or chemical-mechanical planarization of microelectronic device substrate assemblies | |
US6682404B2 (en) | Method for controlling a temperature of a polishing pad used in planarizing substrates | |
US8439723B2 (en) | Chemical mechanical polisher with heater and method | |
KR20000052645A (en) | Method for chemical-mechanical planarization of a substrate on a fixed-abrasive polishing pad | |
US6576552B2 (en) | Method for polishing semiconductor device | |
JP2862073B2 (en) | Wafer polishing method | |
JPH09186116A (en) | Manufacture of semiconductor device and semiconductor manufacture device | |
US6343977B1 (en) | Multi-zone conditioner for chemical mechanical polishing system | |
KR20060119767A (en) | Wafer polishing apparatus and method for polishing wafers | |
JPH09289183A (en) | Flattening method of semiconductor substrate and its equipment | |
US6743080B2 (en) | Method for seasoning a polishing pad | |
US6221773B1 (en) | Method for working semiconductor wafer | |
JP2008229846A (en) | Device and method for polishing, and top ring | |
KR100857661B1 (en) | Removal profile tuning by adjusting conditioning sweep profile on a conductive pad | |
US20230024009A1 (en) | Face-up wafer edge polishing apparatus | |
US20230390887A1 (en) | Face-up wafer electrochemical planarization apparatus | |
JP3820432B2 (en) | Wafer polishing method | |
US20070158207A1 (en) | Methods for electrochemical processing with pre-biased cells | |
CN115383599B (en) | Electrophoresis-assisted self-feeding type ultra-precise micro-polishing method and device | |
US6676496B2 (en) | Apparatus for processing semiconductor wafers | |
JP3882992B2 (en) | Wafer polishing method and apparatus | |
JP2003260642A (en) | Mirror grinding method and its device | |
TW426558B (en) | Method of cleaning wafer after chemical mechanical polishing | |
JP2003297804A (en) | Substrate processing device and method | |
JP2001196339A (en) | Method for on-line cleaning after cmp |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 20030701 |