JPH09288584A - State detection circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To always and precisely recognize the state of a circuit to be detected by giving interruption and reading the state of the circuit to be detected with CPU when the state of the circuit to be detected, which CPU recognizes, differs from the output signal of the circuit to be detected. SOLUTION: A circuit state detection device contains an address decoder 16 inputting the output signal of the circuit to be detected 10, CPU 18, a state comparator 24 and a latch circuit 26. The state comparator 24 is exclusive OR and it compares the outputs signal of the circuit to be detected 10 with the output signal of the latch circuit 26. When both differ, an interruption instruction signal INT is supplied to CPU 18. When the state of the circuit to be detected 10, which CPU 18 recognized, differs from the actual state of the circuit to be detected 10, interruption is given without fail, and the state of the circuit to be detected 10 is read. The circuit state is read by permitting CPU 18 to read the input part 16A of the address decoder 16.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a state detecting device for detecting a state of a circuit by a CPU (central processing unit), and more specifically for interrupting the CPU to detect the state of a detected circuit. State detection device.

[0002]

2. Description of the Related Art In some control systems using a CPU, the CPU reads the states of a plurality of circuits and controls each device based on the results. In this case, control of each device is started by surely reading the state of each circuit.

For example, the control performed by the CPU is
"Read the state of the switch (circuit) X and perform the work Y when it is ON." In this case, the CPU starts with "reading the state of X.", and the result determines "whether or not to work Y". Therefore, in a control system using a CPU, it is fundamental and important to surely read, that is, detect the circuit state.

Conventionally, when the circuit state is detected by the CPU, the following two methods have been used. (1) The CPU periodically observes the state of the circuit.
(See FIG. 3) (2) When the state of the circuit changes, the CPU is interrupted to read the state of the circuit. (See FIGS. 4 and 5)

The first conventional method will be described with reference to FIG. According to this example, the circuit state detecting device includes an address decoder 16 and a C which receive the output signal of the detected circuit 10.
PU18 and. The detected circuit 10 includes a resistor 12 connected to a power supply terminal 11 and a switch device 13.

The output signal of the detected circuit 10 becomes "L" level when the switch device 13 is ON, and becomes "H" level when the switch device 13 is OFF. The address decoder 16 includes an input section 16A, and the input section 16A is connected to the output terminal of the detected circuit 10. The input unit 16A is assigned to an arbitrary address.

The CPU 18 uses an interrupt, an address bus,
It may be a general CPU having functions such as a data bus, reading and writing.

In this method, the CPU 18 causes the address decoder 1 to read every read cycle set by software.
6 input sections 16A are configured to be read.

The second conventional method will be described with reference to FIG. According to this example, the circuit state detecting device includes an address decoder 16 and a C which receive the output signal of the detected circuit 10.
It includes a PU 18, a state change detector 20, and an interrupt circuit 22. The second method is different from the first method shown in FIG. 2 in that a state change detector 20 and an interrupt circuit 22 are additionally provided, and the other configurations are the same.

The state change detector 20 is connected to the output end of the circuit to be detected 10 and outputs the output signal SW of the circuit to be detected 10.
One pulse is generated when the level of is changed. The interrupt circuit 22 may be a D-type flip-flop, which inputs the pulse signal output from the state change detector 20 from the CK terminal and outputs the interrupt command signal INT to the CPU 18 from the Q terminal. The interrupt circuit 22 receives the reset signal RP output from the output unit 16B of the address decoder 16.
Enter

Description will be made with reference to FIG. FIG. 5 is a time chart in the second conventional method shown in FIG.
5A shows the output signal SW of the detected circuit 10, FIG. 5B shows the output signal CP of the state change detector 20, FIG. 5C shows the output signal of the address decoder 16, that is, the reset signal RP, and FIG. 5D shows the Q terminal of the interrupt circuit 22. The waveform of the output signal INT is shown. As shown in FIGS. 5A and 5B, every time the level of the output signal SW of the detected circuit 10 changes, the state change detector 2
0 produces a pulse CP. As shown in the figure, these pulses are sequentially referred to by reference symbols CP1, CP2, CP3, CP4, C.
Add P5.

As shown in FIG. 5D, the output signal of the interrupt circuit 22, that is, the interrupt signal INT, becomes "H" level when the pulse signal CP output from the state change detector 20 is input, and is output from the address decoder 16. When the reset signal RP is input, it becomes "L" level.

In this example, the CPU 18 uses the interrupt circuit 2
Interrupt signal INT from 2 goes from "L" level to "H"
When the level is reached, an interrupt is generated and the detected circuit 1
Read the circuit state of 0. The circuit state is read by the CPU 18 reading the input unit 16A of the address decoder 16. After that, the address decoder 16 generates the reset signal RP in preparation for the next interrupt, as shown in FIG. 5C.

For example, an interrupt is issued at time T _{1, the} reading is completed at time T ₂ , and a reset signal RP is generated. Next, at time T _{3, an} interrupt is issued and time T ₄
The reading is completed at and the reset signal RP is generated.
Furthermore, an interrupt is applied at time T ₅ , the reading is completed at time T ₆ , and a reset signal RP is generated.

As is clear from a comparison between FIGS. 5B and 5D, when the state change detector 20 generates a pulse (CP1, CP2, CP3) when the interrupt signal INT from the interrupt circuit 22 is at "L" level. The interrupt signal INT from the interrupt circuit 22 changes from the “L” level to the “H” level and interrupts and reads, but when the interrupt signal INT from the interrupt circuit 22 is at the “H” level, the state change detector Even if 20 generates a pulse (CP4, CP5), the interrupt signal INT does not change. Therefore, no interrupt or read is done.

[0016]

In the first method, the CP
U18 reads the state of the detected circuit 10 at every predetermined cycle. This method has an advantage that the hardware configuration is relatively simple, but has a drawback that the CPU 18 always reads without regard to the state of the circuit to be detected 10, so that the dead time is long and the performance of the CPU 18 is deteriorated.

In the second method, when the state change detector 20 generates a pulse and the interrupt signal from the interrupt circuit 22 changes from the "L" level to the "H" level, an interrupt is generated and the detected circuit 10 is detected. Read the status. Therefore, even if the state change detector 20 generates a pulse when the interrupt signal from the interrupt circuit 22 is at the "H" level, no interrupt occurs and the state of the detected circuit 10 cannot be read. .

While the interrupt signal from the interrupt circuit 22 is at the "H" level, the change detector 20 outputs the pulse C.
This is the time from the generation of P to the generation of the reset signal RP by the address decoder 16. This time is not constant for the following reasons.

(1) Since interrupts and the like (work) have priorities, it takes time until the interrupt is actually performed. (2) A register save time is required to shift to the interrupt operation. (3) It takes time to refresh the DRAM.

That is, even if the interrupt signal INT changes from "L" level to "H" level, it takes time to actually read the state of the circuit, and the time until the reset signal RP is generated is not constant. The second conventional example is configured to read the state of the detected circuit 10 only when the state of the detected circuit 10 changes, and thus has the advantage that the software performance of the CPU 18 does not deteriorate. As described above, there is a drawback that the state of the detected circuit 10 cannot be read accurately.

In view of the above point, the present invention provides a state detection circuit configured to read the state of the detected circuit only when the state of the detected circuit changes. An object is to provide a state detection circuit that can be recognized.

[0022]

According to the present invention, a state detection circuit includes a CPU for reading the state of a detected circuit, an output signal of the detected circuit and a state of the detected circuit recognized by the CPU. And a state comparator that compares the state of the circuit to be detected by the CPU with an output signal of the circuit to be detected which is different from the state of the circuit to be detected recognized by the CPU. It is configured to read the state of the circuit to be detected.

According to the present invention, in the state detection circuit,
The state of the detected circuit is passed through the address decoder to the above C
Read by PU. The state comparator is an exclusive OR circuit that compares the output signal of the detected circuit with the state of the detected circuit recognized by the CPU. The state comparator compares the output signal of the detected circuit with the output signal of a latch circuit that latches a signal indicating the state of the detected circuit. The latch circuit is a D-type flip-flop circuit which inputs the state of the detected circuit recognized by the CPU from a D terminal.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An example of a circuit state detecting device according to the present invention will be described with reference to FIG. According to this example, the circuit state detecting device includes an address decoder 16 for inputting the output signal of the detected circuit 10, a CPU 18, a state comparator 24 and a latch circuit 26. The device of this example has a state comparator 24 and a latch circuit 26 which are different from those of the first example of the related art shown in FIG.
And are additionally provided, and the second conventional type shown in FIG.
Compared with the above example, the state change detector 20 and the interrupt circuit 22
Instead of the above, a state comparator 24 and a latch circuit 26 are provided, and other configurations are the same.

The latch circuit 26 may be a D-type flip-flop, and the detected circuit 10 recognized by the CPU 18 is detected.
Latch the state of. A command signal for reading the state of the detected circuit 10 recognized by the CPU 18 is input from the CK terminal. C from the D terminal via the address decoder 16
A signal DATA indicating the state of the detected circuit 10 recognized by the PU 18 is input. Latch circuit 2 from the Q terminal
A signal indicating the state of the detected circuit 10 latched by 6 is output.

The state comparator 24 is an exclusive OR, and compares the output signal of the detected circuit 10 with the output signal of the latch circuit 26. When the two are different, the CPU 18 is supplied with the interrupt command signal INT. Therefore, the CPU 18
The detected circuit 10 recognized by the
When the state is different from the state of 1, the state of the detected circuit 10 is read in without fail. To read the circuit state, the input unit 16A of the address decoder 16 is set to the CPU 18
Is done by reading.

Description will be made with reference to FIG. 2A shows an output signal SW of the detected circuit 10, and FIG. 2B shows a signal SW ′ indicating the state of the detected circuit 10 recognized by the CPU 18.
For example, the state of the detected circuit 10 changes at time T ₁ ,
When the signal SW changes from the L level to the H level, an interrupt is issued, the state of the detected circuit 10 is read, and at the time T ₂ when the reading is completed, the signal SW ′ indicating the state of the detected circuit 10 recognized by the CPU 18 is read. Also becomes H level.

Similarly, at time T_Three , T_Five , T₇ , T₉ so
Also, the signal SW changes and_Four, T ₆, T₈, T_Tenso
Shows the state of the detected circuit 10 recognized by the CPU 18.
The signal SW 'changes. Time T when signal SW changes₁,
T_Three , T_Five , T₇ , T₉ When the signal SW 'changes from
T_Two, T_Four, T₆, T₈, T_TenRefer to Fig. 5 for time to
As explained, the actual reading is performed after the interrupt is applied.
It is the time until the collection is completed. Interrupt and read
End time T_Two, T_Four, T₆, T₈, T_TenThen 2
The two signals SW and SW 'always match.

For example, from time T ₁ to time T ₂ ,
When the state of the circuit to be detected 10 changes, the two input signals SW and SW ′ of the state comparator 24 at that time match. Therefore, interruption and reading are not performed, and CP
The state of the detected circuit 10 recognized by U18 does not change.

According to this example, the state of the detected circuit 10 and C
When the state of the detected circuit 10 recognized by the PU 18 is different, an interrupt is always issued and the state of the detected circuit 10 is read, so that the CPU 18 recognizes the actual state of the detected circuit 10. The states of the detection circuit 10 always match.

For example, even if the CPU 18 holds an appropriate value as the state of the detected circuit 10 at the initial setting of T ₀ when the CPU 18 is started, it is output to the latch circuit 26 and detected by the state comparator 24. The output signal SW of the circuit 10 and the output signal SW ′ of the latch circuit 26 are compared. If the two are different, an interrupt is issued and the state of the detected circuit 10 is read, and if the two are the same, the latch circuit 26 holds the signal.

Although the embodiments of the present invention have been described in detail above, the present invention is not limited to these examples, and various modifications can be made within the scope of the invention described in the claims. It will be understood by those skilled in the art.

In the above example, a circuit including the switch device 13 is described as the detected circuit 10, but this is merely an example, and the detected circuit applied to the present invention changes into a plurality of states. Any circuit may be used as long as it outputs a signal for instructing.

[0034]

According to the present invention, the hardware configuration is simple and the circuit state can be read reliably. Further, since it is an interrupt method, it has an advantage that the performance of the CPU does not deteriorate.

[Brief description of drawings]

FIG. 1 is a diagram showing an example of a detection circuit according to the present invention.

FIG. 2 is a diagram showing a time chart of a detection circuit according to the present invention.

FIG. 3 is a diagram showing a first example of a conventional detection circuit.

FIG. 4 is a diagram showing a second example of a conventional detection circuit.

FIG. 5 is a diagram showing a time chart of a second example of the conventional detection circuit.

[Explanation of symbols]

10 detected circuit, 11 power supply terminal, 12 resistor, 1
3 switch device, 16 address decoder, 18 CP
U, 20 state change detector, 22 interrupt circuit, 24
State comparator, 26 latch circuit

Claims (5)

[Claims] 1. A CPU for reading the state of a detected circuit,
A state comparator for comparing the output signal of the circuit to be detected with the state of the circuit to be detected recognized by the CPU, wherein the state comparator compares the state of the circuit to be detected recognized by the CPU. A state detection circuit configured to read the state of the detected circuit by the CPU by interrupting when the state and the output signal of the detected circuit are different. 2. The state detection circuit according to claim 1, wherein
The state detection circuit is characterized in that the state of the detected circuit is read by the CPU via an address decoder. 3. The exclusive OR circuit according to claim 1, wherein the state comparator compares the output signal of the detected circuit with the state of the detected circuit recognized by the CPU. A state detection circuit characterized by: 4. The state detection circuit according to claim 1, wherein the state comparator is a latch circuit that latches an output signal of the detected circuit and a signal indicating the state of the detected circuit. A state detection circuit configured to compare with an output signal. 5. The state detection circuit according to claim 4,
A state detection circuit, wherein the latch circuit is a D-type flip-flop circuit for inputting a state of the detected circuit recognized by the CPU from a D terminal.