JPH09283740A - Electrostatic induction type thyristor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a static induction type thyristor suited for high frequency use by mutually connecting metal cathode electrodes formed on an n-type cathode region and other plane of a semiconductor substrate to thereby reduce the base thickness. SOLUTION: A base layer 5 is formed through an insulation film (SiO2 ) 8 on one plane of an SOI substrate 9. A cathode metal electrode 11 on the other plane is connected to the electrode 1 formed on cathode layers 3. An anode electrode 16 is formed on the same plane at specified distance from the cathode layers 3 on the base layer 5 and gate layer 4. The withstanding voltage is shared with gaps between the cathode and anode layer 3 and 16 and between the substrate 9 and anode layer 16. This allows the thickness of the base layer 5 to be less than a half that of a longitudinal element. Thus it is expectable to improve the switching characteristic by the reduction of the base layer thickness.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to an electrostatic induction thyristor (or an electric field control thyristor: Field Cont).
Rolled Thyristor).

[0002]

2. Description of the Related Art Semiconductor devices of self-arc-extinguishing type are used in applied equipment in various fields because of the ease of power conversion. However, in order to use electric energy with high efficiency, high speed operation and low loss are possible. There is a strong demand for the development of advanced devices. Static induction type thyristor (hereinafter abbreviated as SI thyristor)
Has attracted attention as a next-generation power semiconductor device capable of high-speed operation in a high-voltage, large-current region. From the aspect of application in the power field, the peak repetitive off-voltage of 4500V, which is currently achieved by a gate turn-off thyristor (GTO), The advent of devices with a repeatable controllable on-current of 3000 A class or more has been desired.

FIG. 9 shows a sectional structure of a main part of a conventional SI thyristor. 1 is a cathode metal electrode, 2 is a gate metal electrode, 3 is a cathode layer (N type cathode region), 4 is a gate layer (P Type gate region), 5 is a base layer (N
^- layer), 6 anode layer (P-type anode region), 7 is the anode metal electrode.

In this SI thyristor, a P-type anode layer 6 is formed on one main surface of an N ^- type substrate 5, and a P-type gate layer 4 and an N-type cathode layer 3 are formed on the other main surface. It is a device having a structure in which they are alternately arranged. The SI thyristor is a device capable of increasing the current capacity by operating a plurality of unit elements surrounded by a broken line in the drawing in parallel.

[0005]

The conversion efficiency of SI thyristors is higher than that of other power semiconductor devices. Therefore, if a high-voltage and large-capacity SI thyristor can be realized, progress in the energy application field can be expected. The SI thyristor is composed of thousands to hundreds of thousands of unit SI thyristors, and each of the unit SI thyristors operates in parallel to turn on and off a large current.

Therefore, in order to improve the maximum controllable current (turn-off current) of the SI thyristor, it is sufficient to increase the element area and increase the number of unit SI thyristors.
To increase the pressure, the thickness of the base region may be increased. However, an increase in the base thickness causes a significant increase in steady loss and switching loss, making it impossible to operate at high speed.

Therefore, in order to make the increase in the base thickness as small as possible, a so-called pin base structure in which an n buffer layer is added to the n base layer is often used. However, the base thickness can be reduced by the pin structure is at most about 1/3, which switching frequency can be realized by were several KH _Z Hereinafter 2000V grade or more elements. In order to achieve higher frequencies, it was necessary to drastically reduce the base thickness by some method.

The present invention has been made in view of the above points, and an object thereof is to provide an electrostatic induction type thyristor in which the thickness of the base is reduced to achieve high frequencies.

[0009]

(1) The present invention provides a semiconductor substrate, an N-type high specific resistance semiconductor base substrate formed on one surface of the semiconductor substrate with an insulating film interposed therebetween, and the N-type high resistance substrate. A plurality of slit-shaped N-type cathode regions provided on a predetermined portion of the surface of the specific resistance semiconductor base substrate, and a P-type anode provided on another portion of the same surface of the N-type high specific resistance semiconductor base substrate. A region and a P-type gate region formed so as to surround the N-type cathode region for ON / OFF control of current, and a cathode is provided on the N-type cathode region and the other surface of the semiconductor substrate. It is characterized in that each metal electrode is provided and the cathode metal electrodes are connected to each other, and (2) a relatively high concentration of N is provided between the N-type high resistivity semiconductor base substrate and the P-type anode region.
A mold buffer layer is formed, (3)
In the plurality of P-type gate regions, a region closest to the P-type anode region is formed deeper than the other P-type gate regions, (4) The plurality of P-type gate regions, It is characterized in that it is formed deeper as it gets closer to the P-type anode region, and (5) the deeply formed P-type gate region is formed after forming a trench groove, (6) ) The deeply formed P-type gate region is formed by impurity diffusion without forming a trench groove, and (7) the deeply formed P-type gate region does not form a trench groove. (8) The P-type anode region and the N high resistivity semiconductor Over scan substrate is characterized by being short-circuited by the anode metal electrode (9) and the P-type anode region, between the nearest P-type gate region to region,
A P-type layer deeper than the P-type gate region and not connected to the gate metal electrode is provided.

(10) In the invention of claim 1, since the N-type cathode region and the P-type anode region are provided on the same surface side of the N-type high resistivity semiconductor base substrate, the withstand voltage is the same as that of the P-type anode region. Not only between the N-type cathode regions,
The voltage is also shared and applied between the P-type anode region and the semiconductor substrate. As a result, the thickness of the N-type high specific resistance semiconductor base substrate can be reduced to half or less as compared with the conventional vertical element. Further, although the withstand voltage is shared as described above, since the P-type anode region and the semiconductor substrate are separated by the insulating film, accumulation of excess carriers, which causes switching loss of the element, does not occur in the semiconductor substrate. Therefore, the switching characteristics are improved by the reduction of the thickness of the N-type high resistivity semiconductor base substrate.

(11) In the invention of claim 2, by forming a relatively high concentration N type buffer layer between the N type high resistivity semiconductor base substrate and the P type anode region to form a pin base structure, The thickness of the N-type high resistivity semiconductor base substrate is further reduced, and further improvement in switching characteristics can be expected.

(12) In the inventions of claims 3 to 7, since the P-type gate region near the P-type anode region is deeply formed, the current path between the P-type anode region and the plurality of N-type cathode regions. The substantial difference in distance is reduced as compared with the conventional one. As a result, the nonuniformity of the cathode current density is almost eliminated, and a large capacity SI thyristor can be realized. Further, immediately below the deep P-type gate region, the entire current path is cut off earlier due to the electrostatic induction effect at the time of turn-off, so that the switching characteristic is also improved.

(13) In the invention of claim 8, since the anode metal electrode is short-circuited to the N-type high resistivity semiconductor base substrate, excess carriers are discharged from the N-type high resistivity semiconductor base substrate at turn-off. Is faster and the switching characteristics are improved.

(14) In the invention of claim 9, since the P-type layer deeper than the P-type gate region and not connected to the gate metal electrode is provided to form a so-called floating electrode, the unevenness of the cathode current density is alleviated. .

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention relates to an SOI (Silocon on Insula) in a high withstand voltage SI thyristor.
The base thickness is reduced to 1 /
The thickness is reduced to 2 to 1/10 so that the frequency can be increased. Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) In the present invention, as shown in FIG. 1, an SI thyristor is formed in a so-called lateral type (horizontal type) on an SOI substrate used for a low capacity integrated device such as a MOSFET or an IGBT. did. The SOI substrate is a so-called SDB (Silicon Dire) in which, for example, two Si single crystal wafers each having a silicon oxide film formed on the surface are directly bonded, heat-treated, and polished to finish.
ct Bonding) technology.

In FIG. 1, the same parts as those in FIG. 9 are designated by the same reference numerals. A semiconductor substrate 9 has a base layer 5 provided on one surface of the substrate via an insulating film (SiO ₂ ) 8 and a cathode metal electrode 11 provided on the other surface. The cathode metal electrode 11 is connected to the cathode metal electrodes 1 provided on the plurality of cathode layers 3, respectively. An anode layer 16 is formed on the same plane of the base layer 5 separated from the cathode layer 3 and the gate layer 4 by a predetermined distance. Reference numeral 17 is an anode metal electrode.

As can be seen from the figure, the withstand voltage is the cathode layer 3
And the anode layer 16 as well as between the semiconductor substrate 9 and the anode layer 16. As a result, the thickness of the base layer 5 can be reduced to less than half that of the conventional vertical element. By the way, although the withstand voltage is shared as described above, the insulating film 8 is provided between the semiconductor substrate 9 and the anode layer 16.
Therefore, the accumulation of excess carriers, which is the cause of the switching loss of the element, does not occur in the semiconductor substrate 9. Therefore, it is expected that the switching characteristics are improved by the amount that the thickness of the base layer 5 is reduced.

(Embodiment 2) In the present invention, as shown in FIG. 2, a relatively high concentration N-type buffer layer 20 is provided between the base layer 5 and the anode layer 16 of the SI thyristor having the structure shown in FIG. It was added to form a pin base structure. 2, the same parts as those in FIG. 1 are indicated by the same reference numerals. According to FIG. 2, the thickness of the base layer 5 becomes thinner than that of FIG. 1, and it can be expected that the switching characteristics will be further improved by the reduced thickness.

(Embodiment 3) A drawback of the lateral device is that the cathode layer and the anode layer are formed on the same plane.
This means that a so-called non-uniformity of the cathode current density occurs in which the ON current flows more easily in the cathode layer closer to the anode layer. This is fatal when considering application to a large capacity element. Therefore, in the present invention, as shown in FIG. 3, the deep gate layer 24 is formed by forming the gate layer closest to the anode layer 16 after forming the trench groove 21. The trench groove 21 can be formed uniformly without damaging the miniaturization, for example, by etching with a reactive ion that is applied with an electric field using a silicon oxide film or the like as a mask. In FIG. 3, the same parts as those in FIG. 1 are designated by the same reference numerals.

Due to the deep gate layer 24 formed in the trench groove 21 as described above, the substantial difference in the current path between the anode layer 16 and the plurality of cathode layers 3 is drastically relaxed as compared with the conventional one. As a result, the nonuniformity of the cathode current density is almost eliminated, and a large capacity SI thyristor can be realized. Further, immediately below the deep gate layer 24 formed in the trench groove 21, the entire current path is cut off earlier due to the static induction effect at the time of turn-off, so that the switching characteristic is also improved.

(Embodiment 4) In the present invention, as shown in FIG. 4, a plurality of gate layers closer to the anode layer 16 than the gate layer are formed after the trench grooves 21a and 21b are formed. 24a and 24b were formed.
The depth of the trench grooves 21a and 21b is set to be shallower as the gate layer is farther from the anode layer 16. As a result, the substantial difference in the current path between the anode layer 16 and the plurality of cathode layers 3 is further alleviated as compared with the device of the third embodiment. In FIG. 4, the same parts as those in FIG. 1 are designated by the same reference numerals.

[0023]

EXAMPLE A gate layer 24 closest to the anode layer 16
The a is not limited to be formed using the trench groove, but may be formed only by impurity diffusion as shown in the diffusion layer 32 (deep gate layer) in FIG. Also in this case, the same operation and effect as described above are obtained.

The embodiment of FIG. 5 has the advantage that no trench etching is required, but has the problem that the gate width becomes wider due to the lateral diffusion by the diffusion depth. Therefore, as shown in FIG. 6, the buried P-type layer 43 is buried by epitaxial growth to diffuse the diffusion layer 42.
To prevent the gate width from increasing due to lateral diffusion.

As shown in FIG. 7, the anode metal electrode 17 may be short-circuited to the base layer 5 by forming a short diffusion layer 44 on the anode metal electrode 17 side of the base layer 5. That is, the anode layer 16 and the base layer 5 are short-circuited by the anode metal electrode 17. With this configuration, the excess carriers in the N base are quickly discharged at turn-off, and the switching characteristics are improved.
FIG. 7 shows that the present embodiment is applied to the device of FIG. 3 (Embodiment 3), but the present invention is not limited to this, and is applied to the devices of FIGS. 1, 2, 4, 5, and 6. Also has similar actions and effects.

The electrode on the deep gate layer closest to the anode layer may be a so-called floating electrode which is not connected to the gate control electrode. That is, as shown in FIG. 8, the gate layer 4 closest to the anode layer 16 is formed.
An independent P-type layer (gate layer) 24, which is deeper than the gate layer 4, is provided at a position further closer than the gate layer 4 and is used as a floating gate 45. With this configuration, the effect of alleviating the nonuniformity of the cathode current density can be expected as in the above case. FIG. 8 shows the present embodiment applied to the element of FIG. 3 (Embodiment 3), but the present invention is not limited to this, and the same action and effect can be obtained when applied to the elements of FIG. 5 and FIG. 5 to 8, the same parts as those in FIG. 1 are designated by the same reference numerals.

[0027]

As described above, according to the present invention, the following excellent effects can be obtained. (1) According to the inventions of claims 1 to 9, S is formed on the SOI substrate.
Since the I thyristor is formed in the horizontal type, the withstand voltage is shared and the thickness of the base layer can be reduced, which allows the high voltage and large capacity SI thyristor to have a high frequency.

(2) According to the inventions of claims 3 to 7, since the P-type gate region close to the P-type anode region is deeply formed, the distance difference between the current paths is alleviated and the nonuniform cathode current density is eliminated. As a result, a large-capacity SI thyristor can be realized and the switching characteristics are improved.

(3) According to the invention of claim 8, since the P-type anode region and the N-type high specific resistance semiconductor base substrate are short-circuited by the anode metal electrode, excess carriers in the N-base at turn-off are provided. Ejection becomes faster and switching characteristics are improved.

(4) According to the invention of claim 9, P which is deeper than the P-type gate region and is not connected to the gate metal electrode
Since the mold layer is provided and the so-called floating electrode is used,
The non-uniformity of the cathode current density is alleviated.

[Brief description of drawings]

FIG. 1 is a sectional view of a main part showing one embodiment of the present invention.

FIG. 2 is a sectional view of a main part showing another embodiment of the present invention.

FIG. 3 is a sectional view of a main part showing another embodiment of the present invention.

FIG. 4 is a cross-sectional view of essential parts showing another embodiment of the present invention.

FIG. 5 is a sectional view of a main part showing another embodiment of the present invention.

FIG. 6 is a cross-sectional view of essential parts showing another embodiment of the present invention.

FIG. 7 is a cross-sectional view of essential parts showing another embodiment of the present invention.

FIG. 8 is a sectional view of a main part showing another embodiment of the present invention.

FIG. 9 is a sectional view of an essential part showing an example of a conventional SI thyristor.

[Description of Reference Signs] 1, 11 ... Cathode metal electrode 2 ... Gate metal electrode 3 ... Cathode layer 4 ... Gate layer 5 ... Base layer 6, 16 ... Anode layer 7, 17 ... Anode metal electrode 8 ... Insulating film 9 ... Semiconductor substrate 20 ... N-type buffer layer 21, 21a, 21b ... Trench groove 24, 24a, 24b ... Deep gate layer 32, 42 ... Diffusion layer 43 ... Buried P-type layer 44 ... Short diffusion layer 45 ... Floating gate

Claims (9)

[Claims] 1. A semiconductor substrate, an N-type high specific resistance semiconductor base substrate formed on one surface of the semiconductor substrate via an insulating film, and a predetermined portion on the surface of the N-type high specific resistance semiconductor base substrate. A plurality of slit-shaped N-type cathode regions provided, a P-type anode region provided at another portion of the same surface of the N-type high resistivity semiconductor base substrate, and the N-type cathode region.
A P-type gate region for controlling on / off of electric current, which is formed so as to surround the type cathode region, and a cathode metal electrode is provided on the N-type cathode region and the other surface of the semiconductor substrate, respectively. , An electrostatic induction type thyristor characterized in that the cathode metal electrodes are connected to each other. 2. The N-type high resistivity semiconductor base substrate and P
The static induction type thyristor according to claim 1, wherein an N-type buffer layer having a relatively high concentration is formed between the type anode regions. 3. The region of the plurality of P-type gate regions closest to the P-type anode region is formed deeper than the other P-type gate regions.
Alternatively, the electrostatic induction thyristor described in 2. 4. The electrostatic induction thyristor according to claim 1, wherein the plurality of P-type gate regions are formed deeper toward the P-type anode region. 5. The deeply formed P-type gate region comprises:
The static induction thyristor according to claim 3 or 4, which is formed after forming the trench groove. 6. The deeply formed P-type gate region comprises:
The electrostatic induction thyristor according to claim 3 or 4, wherein the trench groove is formed by impurity diffusion without being formed. 7. The deeply formed P-type gate region comprises:
The static induction thyristor according to claim 3 or 4, wherein the trench groove is formed by impurity diffusion without being formed, and is formed by being connected to a P-type buried layer buried by epitaxial growth. 8. The P-type anode region and the N high resistivity semiconductor base substrate are short-circuited by an anode metal electrode, according to claim 1, 2 or 3 or 4 or 5 or 6 or 7. The described electrostatic induction thyristor. 9. A P-type layer deeper than the P-type gate region and not connected to the gate metal electrode is provided between the P-type anode region and the P-type gate region closest to the P-type anode region. The electrostatic induction type thyristor according to claim 3 or 5 or 6 or 7.