JPH09282180A - Data processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To surely process an interruption by integrating the processing routine of a processing sequence for the interruption into a data bus driver for receiving the report of interruption generation. SOLUTION: With a vertical synchronizing signal SYNC outputted from a video tape recorder(VTR) 2 as a reference, an interruption control circuit 18 outputs an interruption IRQ to a bus BUS. While reacting to this interruption IRQ, a video memory 19 stores bit map data outputted to the bus BUS. Then, an operating system (OS) has a device driver for processing the interruption IRQ and when a synchronizing signal call back routine corresponding to the interruption IRQ is previously registered by an application program, this device driver starts this synchronizing signal call back routine in response to the report of the interruption IRQ from the OS.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device, for example, applied to an editing device for processing a video signal output from a video tape recorder or the like, and a device in which interrupt processing by a synchronization signal or the like is arranged in a kernel layer. By incorporating it in the driver, the interrupt can be reliably processed.

[0002]

2. Description of the Related Art Conventionally, some editing apparatuses of this type are connected to a computer and a title or the like is created by the computer. In such an editing device, various operations can be executed while confirming the processing result on the monitor.

Therefore, in this type of editing apparatus, image data generated by a computer is transferred and held in a video memory, and the image data in the video memory is displayed on a monitor. The application program is executed by interrupt processing based on the synchronization signal.

That is, FIG. 5 is a time chart showing the interrupt processing based on this synchronizing signal. In the computer, the timing t synchronized with the rising edge of the vertical synchronizing signal due to the hardware structure located in the lowest layer.
An interrupt occurs at 1, t2, t3, ... (Fig. 5 (C))
And (D)). In response to the occurrence of this interrupt, the application program in the application layer (see FIG.
(A)), operating system of the kernel layer (O
S) is notified in advance of the device open, and thereby the corresponding device is exclusively occupied in advance (FIG. 5 (B)).

The operating system accepts the interrupt by registering the callback routine in response to the device open notification, and when the interrupt occurs, notifies the application program of the interrupt by the registered callback routine. The application program is held in a standby state waiting for an interrupt during the period from the device open to the notification of the interrupt, and when the interrupt is notified, immediately executes a corresponding process (hereinafter referred to as a synchronous process).

As a result, in the image processing apparatus, for example, when a title is displayed and moved, the contents of the video memory are sequentially updated by the synchronization processing during the vertical synchronization period of each frame, and the processing result is displayed on the monitor. I was able to confirm.

[0007]

By the way, in this type of computer, so-called multitask processing is performed. In such a computer, a swap file on a hard disk device is accessed to organize virtual memory. Swap processing is executed.
Further, this swap processing is executed on the operating system having a higher priority than the application program.

Therefore, in this type of image processing apparatus,
When this swap processing is executed in the synchronization standby state or the synchronization processing state, the swap processing is given priority during this period,
The synchronization process cannot be executed. As a result, the synchronization process is intermittently executed for the continuous synchronization signal. For example, when the title is moved by sequentially updating the contents of the video memory by the continuous synchronization process, this title is smoothed. There was a problem of not moving to.

The present invention has been made in consideration of the above points, and it is an object of the present invention to propose a data processing device capable of reliably processing an interrupt.

[0010]

In order to solve such a problem, in the present invention, a processing routine of a processing procedure for an interrupt is incorporated in a device driver which receives a notification of the occurrence of an interrupt.

In the device driver, various processes are executed in the kernel layer having a higher priority than the application program. Therefore, as compared with the case where the processing corresponding to the interrupt is executed by the application program, the processing is executed with priority, whereby the interrupt can be reliably processed.

[0012]

Embodiments of the present invention will be described below in detail with reference to the drawings.

(1) First Embodiment FIG. 2 is a block diagram showing an image processing apparatus according to the first embodiment of the present invention. The image processing apparatus 1 displays the video signal S1 output from the video tape recorder 2 on the monitor 3 and causes the computer 5 to generate a title and the like to be added to the video signal S1. Note that, in FIG. 2, description of a video tape recorder or the like for recording the edited result is omitted.

Here, in the computer 5, the image processing board 6 is inserted into the slot on the rear surface, the video signal S1 to be treated is input to the image processing board 6 from the video tape recorder 2, and the video signal resulting from the processing is also input. Is output to the monitor 3 from the image processing board 6. Furthermore, the computer 5 has a read-only memory (ROM) 7 when the power is turned on or the reset switch is operated.
And the hard disk drive (H) according to the startup procedure and startup conditions stored in the random access memory (RAM) 8.
The operating program stored in the DD) 10 is started by the central processing unit 9. Further, the computer 5 starts up an application program necessary for image processing on this operating program, and the central processing unit 9 controls the whole operation according to this application program. It should be noted that in this embodiment, depending on the operating program, WINDOWS NT or WINDOWS 95
Build an operating system based on Microsoft's registered trademark.

The interface circuit (I / F) 11 is
When the keyboard 12 and the mouse 13 are operated, the operation result and the operation amount are output to the bus BUS at a predetermined timing. The video memory 14 receives bitmap data, which is image data, via the bus BUS, and stores this bitmap data. Digital-to-analog conversion circuit (D /
A) 15 performs digital-analog conversion processing on the bitmap data stored in the video memory 14 to generate a video signal, and outputs the video signal to the monitor 16. Thereby, in the computer 5, various objects required for operation, a mouse cursor, etc. are displayed on the monitor 16 to form a display screen for operation.

In forming the display screen of the monitor 16, the random access memory 8 holds coordinate data defining a plurality of windows in a part of its area, and responds to a control command from the central processing unit 9. Data regarding these multiple windows is selectively output. The contents of the video memory 14 are updated by the central processing unit 9 in accordance with the selected and output data. Accordingly, in the computer 5, a plurality of windows in which various objects are arranged are prepared in advance, and in a state where the plurality of windows are arranged on the display screen of the monitor 16 in an overlapping manner, one of the windows is set to be transparent, Further, the upper and lower relations are switched and displayed.

The interface circuit (I / F) 17 is
The control command issued by the central processing unit 9 is received via the bus BUS, and this control command is output to the video tape recorder 2, whereby the operation of the video tape recorder 2 is switched.

The image processing board 6 is directly connected to the bus BUS of the computer 5, and the interrupt control circuit 18 outputs an interrupt IRQ to the bus BUS based on the vertical synchronization signal SYNC output from the video tape recorder 2. To do. The video memory 19 stores the bitmap data output to the bus BUS in response to this interrupt IRQ. As a result, the video memory 19 is changed to the monitor 16
The image data corresponding to the display of 1 is stored, and the image data such as the title as the image processing result is stored in the video memory 19 in response to the user's operation.

Digital-analog conversion circuit (D / A) 2
0 sequentially digital-analog converts the image data stored in the video memory 19 to generate a video signal S2. The adder circuit 22 adds the video signal S2 output from the digital-analog conversion circuit 20 to the video signal S1 output from the video tape recorder 2 to monitor 3
Output to As a result, the image processing board 6 outputs the image data stored in the video memory 19 to the monitor 3,
The menu screen and the image processing result are displayed.

The central processing unit 9 controls the operation of the image processing apparatus 1 as a whole by executing a processing program stored in the hard disk device 10. That is, the central processing unit 9 issues a control command to the video tape recorder 2 via the interface circuit 17 to control the operation of the video tape recorder 2. Further, in response to the operation of the keyboard 12 and the mouse 13 detected via the interface circuit 11, the entire operation is switched, and a title or the like to be added to the video signal S1 is created. Further, in response to the interrupt IRQ, bitmap data such as a title is transferred to the video memory 19.

Here, the processing program is composed of an operating system (OS) of the image processing apparatus 1 and an image processing application program operating on the operating system.

Of these, the operating system has a device driver for processing an interrupt IRQ, and this device driver registers a callback routine (hereinafter referred to as a synchronization signal callback routine) corresponding to the interrupt IRQ in advance by an application program. Interrupt I from the operating system
In response to the notification of the RQ, this sync signal callback routine is activated. This callback routine is IR
This routine is called by the operating system according to the Q number and is registered in the operating system.

As shown in FIG. 1, the synchronization signal callback routine is a subroutine for executing synchronization processing. Here, in this synchronization processing, random access is performed based on a pointer preset by an application program. The image data stored in the memory 8 is transferred to the interrupt control circuit 18 (FIG. 1 (B)-
(D)). As a result, in this embodiment, a synchronization process for responding to the interrupt IRQ is incorporated in the device driver having a higher priority than the application program, and the image data is transferred to the video memory 19 by this synchronization process.
Has been made to transfer to.

Correspondingly, in the application program, unlike the conventional case, when the processing result is displayed on the monitor 3 in response to the user's operation and according to the edit list, the device open is declared at the display start time. To do. As a result, the application program registers the synchronization signal callback routine in the operating system via the device driver used for the synchronization processing, and exclusively uses this device driver (FIG. 1 (A)).
At the end of the display, declare device close,
Release the device.

In the above configuration, when the power is turned on or the reset switch is operated (FIG. 2), in the image processing apparatus 1, the start-up procedure stored in the read-only memory 7 and the random access memory 8, An operating program stored in the hard disk device 10 is started up by the central processing unit 9 according to the start-up condition, and an application program required for image processing is started up on this operating program.

Thus, in the image processing apparatus 1, the user operates the keyboard 12 and the mouse 13 in accordance with the application program to generate the video signal S1.
A title or the like to be added to is created, and the created image data is stored in the random access memory 8. Further, the image processing apparatus 1 similarly stores predetermined bitmap data in the random access memory 8 as image data forming the menu screens of the monitors 3 and 16.

In the image processing apparatus 1, the image data and the like thus stored in the random access memory 8 are transferred to the video memory 19 at a timing synchronized with the vertical synchronizing signal SYNC of the video signal S1 and then digitally transferred. The analog conversion circuit 20 converts the video signal S2 into a video signal S2, and the addition circuit 22 adds the video signal S1 to the video signal S1 to display a menu screen on the monitor 3 for operation on the image to be processed. A title and the like, which is the edited result, are displayed.

In the transfer of this image data, in the image processing apparatus 1, the interrupt control circuit 18 always interrupts the interrupt IR at the timing synchronized with the vertical synchronizing signal SYNC (FIG. 1).
When Q is continuously issued and the processing result is displayed on the monitor 3 in response to the user's operation in this state and according to the edit list, the central processing unit 9 opens the device on the application program at the display start time. declare. As a result, in the image processing apparatus 1, the application program registers the synchronization signal callback routine in the device driver and exclusively uses this device driver.

In response to this, the device driver activates this synchronous signal callback routine in response to the interrupt IRQ from the interrupt control circuit 18 detected through the operating system, and by this synchronous signal callback routine, The image data stored in the random access memory 8 (synchronization processing routine) is transferred to the video memory 19 based on a preset pointer.
As a result, the device driver executes the synchronization process for the interrupt IRQ.

In the computer 5, the synchronization process in the device driver is a process having a similar or higher priority than the swap process, and naturally a process having a higher priority than the application program. As a result, the computer 5 executes the synchronous processing corresponding to the consecutive interrupts without being affected by the swap processing. As a result, the image processing apparatus 1 can reliably execute continuous interrupt processing. Therefore, for example, when the title is moved on the monitor 3, the contents of the video memory can be sequentially updated by the synchronization processing during the vertical synchronization period of each frame, and this character can be moved smoothly. Further, in the application program, it is not necessary to wait for the interrupt notification from the driver for each synchronization signal, so that the processing load of the whole is reduced.

On the other hand, when the display is ended, the central processing unit 9 declares the device close on the application program and releases the device.

According to the above configuration, the synchronous processing for transferring the image data in response to the interrupt IRQ is incorporated into the device driver for detecting the interrupt IRQ, so that the synchronous processing can be executed more stably than before. can do. As a result, it is possible to reliably execute the synchronous processing in response to successive interrupts, and the display screen of the monitor 3 can be changed smoothly.

(2) Second Embodiment FIG. 3 is a time chart used for explaining the operation of the image processing apparatus according to the second embodiment. The image processing apparatus according to this embodiment has the same configuration as that of the first embodiment, except that the processing procedure of the central processing unit 9 defined by the operating system and the application program is partly different, and therefore, there is duplication. The description is omitted.

Also in this embodiment, the application program entrusts the device driver with the synchronization processing. At this time, the application program registers the synchronization signal callback routine in the operating system in advance via the device driver, and then instructs the device driver to start the synchronization process at the time of starting the display (FIGS. 3A and 3B). ). At the end of display, the device close is declared after declaring the end of synchronous processing.

In response to this, the device driver accepts registration of the synchronization signal callback routine in advance, but waits for an instruction to start the synchronization processing from the application program, starts the synchronization processing, and synchronizes with the instruction to end the synchronization processing. The process ends (FIGS. 3C and 3D).

According to the second embodiment, the start and end of the synchronization processing are instructed separately from the registration of the synchronization signal callback routine, so that the start and end points of the synchronization processing are surely controlled. The same effect as that of the first embodiment can be obtained.

(3) Third Embodiment FIG. 4 is a time chart for explaining the operation of the image processing apparatus according to the third embodiment. The image processing apparatus according to this embodiment has the same configuration as that of the first embodiment except that the processing procedure of the central processing unit 9 defined by the operating system and the application program is partly different, and thus the duplication is eliminated. The description is omitted.

Also in this embodiment, the application program entrusts the device driver with the synchronization processing. At this time, the application program registers the synchronization signal callback routine in advance in the operating system via the device driver, and then instructs the device driver to start the synchronization process by designating the number of times of the synchronization process at the time of starting the display (see FIG. 4 (A) and (B)). At the end of display, the device close is declared after declaring the end of synchronous processing reception.

In response to this, the device driver registers a synchronization signal callback routine in the operating system, waits for an instruction from the application program to start the synchronization process, and then starts the synchronization process. Further, the device driver counts the number of times of synchronization processing, and this number of times of processing is the number N of times of synchronization processing designated at the start of the synchronization processing.
Then, the synchronous process is ended by the subsequent interrupt IRQ (FIGS. 4C and 4D).

According to the third embodiment, the number of times N of synchronization processing is designated, the start of the synchronization processing is instructed, and the synchronization processing is ended by this registration number N, whereby the number of times of synchronization processing and the synchronization processing are performed. Be sure to control the start and end times of
The same effect as in the first embodiment can be obtained.

(4) Other Embodiments In the above embodiment, the case where one type of synchronization processing is assigned to the device driver has been described.
The present invention is not limited to this, and a plurality of synchronization processes may be assigned. In this case, the type and the number of times of synchronous processing may be specified together in a series of processing. Further, in this case, for example, by activating the subroutines sequentially from the synchronization signal callback routine registered in the application program, or by setting the schedule of the synchronization process indicating that different synchronization processes are continuously executed as an argument, the callback is executed. By activating the routine, a plurality of synchronization processing routines can be called from one callback routine, and a plurality of types of preset synchronization processing may be sequentially executed for each synchronization signal.

In the above embodiment, the case where the synchronization process is simply repeated has been described. However, the present invention is not limited to this, and a function of temporarily stopping the process may be incorporated in the device driver. By doing so, it is possible to immediately suspend the synchronous processing in response to the abnormality on the application program side, and by adding a resuming function in addition to this, the suspended processing can be resumed.

Further, in the above-mentioned embodiment, the case where the image data is transferred as the synchronous processing has been described. However, the present invention is not limited to this, and can be widely applied to the processing of the interrupt which is repeatedly generated as necessary. it can.

Further, in the above embodiment, the WI
Although the case where the operating system is constructed by NDWS NT or WINDOWS 95 has been described, the present invention is not limited to this and can be widely applied to various operating systems.

Further, in the above-described embodiment, the case where a title or the like is added to the video signal output from the video tape recorder has been described, but the present invention is not limited to this and is applied to various video equipment and the like. It can be widely applied to data processing devices that process image data and the like.

[0046]

As described above, according to the present invention, it is possible to stably execute the interrupt processing by allocating the interrupt processing by the synchronization signal or the like to the device driver arranged in the kernel layer. Can be reliably processed.

[Brief description of drawings]

FIG. 1 is a time chart showing processing of a central processing unit in an image processing apparatus according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing an overall configuration of the image processing apparatus of FIG.

FIG. 3 is a time chart showing processing of a central processing unit in the image processing apparatus according to the second embodiment of the present invention.

FIG. 4 is a time chart showing the processing of the central processing unit in the image processing apparatus according to the third embodiment of the present invention.

FIG. 5 is a time chart showing interrupt processing of a conventional central processing unit.

[Explanation of symbols]

1 ... Image processing device, 2 ... Video tape recorder,
3, 16 ... Monitor, 5 ... Computer, 7 ... Hard disk device, 13 ... Mouse, 14, 19 ... Video memory, 18 ... Interrupt control circuit

Claims (4)

[Claims] 1. A data processing apparatus which executes a predetermined processing procedure in response to each interrupt which is repeatedly generated, wherein a processing routine of the processing procedure is incorporated in a device driver which receives a notification of the occurrence of the interrupt. Characteristic data processing device. 2. The processing procedure is executed by calling a predetermined subroutine registered in advance by an application program, the application program executing the registration processing in advance, and then executing the registration of the device driver at a predetermined timing. The instruction to start the operation is provided.
A data processing device according to claim 1. 3. The data processing apparatus according to claim 1, wherein the device driver counts the number of times the interrupt is processed and executes the processing procedure a preset number of times. 4. The data according to claim 1, wherein the interrupt is generated in synchronization with a vertical synchronizing signal of a video signal, and the processing procedure is a process of transferring image data to a video memory. Processing equipment.