JPH0927931A - Signal identification device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To allow the device to surely identify whether or not a signal is a letter box form even when waveform distortion by ghost or the like takes place. SOLUTION: A received video signal is given to an average value circuit 15 via a subtractor 12. The average value circuit 15 obtains a means value of bit areas B1, B2, B3, B4. The mean value depends on a level fluctuation. The means value is integrated by an integration circuit 16, the result is subjected to amplitude limit by an amplitude limit circuit 17 and the result is added to an output of an offset circuit 18, and the sum is given to a subtractor 12. The subtractor 12 cancels the level fluctuation component of the video signal and sets a criterion of a logic value to 0IRE. A bit string coincidence detection circuit 13 decides the logic value according to a sign bit from the subtractor 12 to identify the system of the input video signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal discriminating apparatus for discriminating the type of a video signal input by an NRZ type discriminating code.

[0002]

2. Description of the Related Art In recent years, second-generation EDTV (Extended Definition TV) broadcasting aimed at high image quality and high sound quality has been studied. Second-generation EDTV broadcasting is compatible with current broadcasting and has a screen aspect ratio of 1
The horizontal aspect ratio of 6: 9 makes it possible to watch programs with a realistic feel. The effective scanning line of the second generation EDTV signal corresponds to the vertically centered 3/4 portion of the current NTSC signal having an aspect ratio of 4: 3. Therefore, for example, when a second-generation EDTV broadcast is projected by a television receiver for current broadcasting having an aspect ratio of 4: 3, a letter having a non-image portion at the top and bottom of the screen and a main image portion at the center is displayed. Box display is supposed to be performed.

By adopting this letterbox display, it is possible to display the entire screen of the second generation EDTV broadcast without distortion even in the current television receiver having an aspect ratio of 4: 3. However, the second generation ED
Since the TV uses only the central 3/4 portion of the current NTSC signal having an aspect ratio of 4: 3 as the effective scanning lines, the number of effective scanning lines of the current NTSC signal is 480, whereas the number of effective transmission lines is 480. The number of effective scanning lines of the second generation EDTV signal is 3
It will be 60. At the time of decoding, the 360 effective scanning lines are converted from 3 to 4 scans and returned to 480 lines. The second-generation EDTV signal can be converted to the current NTSC by simply scanning line conversion.
Since the vertical resolution is worse than the signal, it has been decided to multiplex the vertical reinforcement signal to improve the vertical resolution during transmission and to transmit the horizontal reinforcement signal to improve the horizontal resolution. .

In the second generation EDTV system, a sequential scanning signal of 480 lines / screen height is converted into an interlaced scanning signal and transmitted on the transmitting side. In this case, in order to make the letterbox format, that is, to make the number of effective scanning lines 360, the luminance signal of 480 lines / screen height is band-limited to 360 lines / screen height signal by the vertical low-pass filter. To do. Further, in order to convert to the interlaced scanning signal, the luminance signal is band-limited to the signal of 180 lines / screen height by the vertical low pass filter. The band limitation prevents the generation of aliasing distortion at the time of scanning line conversion. A component YL of 4.2 MHz or less in the horizontal low band of the luminance signal of 180 lines / screen high is transmitted as a main screen signal.

Further, the component YH of the band of 4.2 to 6 MHz in the horizontal high range of the luminance signal of 180 lines / screen height is multiplexed with the main screen signal as the horizontal reinforcement signal HH. In this case, the horizontal high frequency component YH is subjected to carrier suppression modulation using a carrier having a frequency of 16 / 7fsc (fsc is a color subcarrier frequency), and further frequency shifted to a frequency region conjugate with the color signal of the main screen signal. The frequency is multiplexed in the blowhole.

On the other hand, the vertical reinforcement signal is band-limited and lost during conversion to the letterbox format from 360 to 48.
Brightness signal vertical high-frequency component (VH) of 0 lines / screen height and temporal vertical high-frequency component (VT) of 180 to 360 lines / screen height lost due to band limitation during conversion from progressive scanning to interlaced scanning And have. These components VH and VT are added according to the movement of the image, and the horizontal direction (time direction)
It is compressed to 1/3. Further, after being modulated using a color subcarrier and band-limited, it is multiplexed on the non-picture part.

In the conventional television receiver, the horizontal reinforcement signal multiplexed in the main picture portion and the vertical reinforcement signal multiplexed in the non-picture portion are demodulated and added to the main screen signal to improve the image quality. I am trying.

By the way, at the beginning of broadcasting, the signal has an aspect ratio of 1 with the signal of the current NTSC system having an aspect ratio of 4: 3.
It is expected that a 6: 9 second-generation EDTV system signal will be mixed and broadcast for each program. Therefore, it is necessary for the receiving side to perform control corresponding to the current NTSC system and the second-generation EDTV system, respectively. Therefore, it is also decided on the transmitting side to multiplex and transmit an identification signal indicating that the second generation EDTV system broadcast signal is being transmitted. The identification signal indicates the aspect ratio of the broadcast signal and the presence / absence of various reinforcing signals, and the phase reference for demodulating the reinforcing signal is obtained. By detecting the identification signal, it is identified whether or not the second generation EDTV system broadcast signal is received, and the identification result is used to perform control corresponding to each broadcast system.

The identification signal is at the top of the image area (22H,
285H) in the horizontal scanning period. Figure 13 shows BT
ANEWS No. FIG. 44 is a waveform diagram showing an identification signal proposed in No. 44 (Jan. 30, '95).

As shown in FIG. 13, the identification signal has 27-bit bit regions B1 to B27. The bit width of each bit is 7 times the color subcarrier period. The bit areas B1 to B5 and B24 are identification codes transmitted in the NRZ (non-return zero) format, and the bit areas B6 to B6.
Reference numeral 23 is a color subcarrier type identification code (frequency is fsc).

An identification code for identifying the mode is assigned to the bit areas B1 to B23, and a confirmation signal for determining the existing video signal is assigned to the bit areas B25 to B27. The confirmation signal has a frequency of 2.04 MH
It is a sine wave of z (= (4/7) fsc). According to the explanation on the identification control signal specifications issued by the Broadcasting Technology Development Council, the zero-cross point of the rising edge of the confirmation signal is synchronized with the I-axis or Q-axis phase of the color subcarrier fsc.

The bit areas B1 and B2 are reference timing signals, the bit area B3 is a signal indicating whether or not letterbox display is performed, the bit area B5 is an undefined bit, and the bit area B4 is a bit area B3. ，
It is an even parity of B5. The identification code of the bit area B3 is "0" to indicate a normal system with an aspect ratio of 4: 3, and "1" to have an aspect ratio of 16:16.
9 shows the letter box method of No. 9. In addition, the bit areas B6 to B11 are assigned information such as the presence / absence of a reinforcement signal for improving the image quality of the second generation EDTV broadcast.

The position of each bit region in the horizontal direction (time direction) is 50% of the level of the leading edge of the horizontal synchronizing signal, that is,-.
It is specified based on 20 IRE. For example, for the bit area B1, as shown in FIG. 13, the timing at which the level becomes -20IRE is defined as the start position, and this start position is 33SC based on the leading edge of the horizontal synchronizing signal.
Is set to the position of. Since the bit width of each bit area is 7 SC, the end position of the bit area B1 is (33 + 7) SC. Similarly, the start position and end position of the n-th bit area Bn are {33 + 7 (n-1)} SC = (26, respectively) with respect to the leading edge of the horizontal synchronizing signal.
+ 7n) SC and {33 + 7n) SC.

In the identification code of the bit areas B1 to B5 and B24 of the NRZ (non-return zero) format, 40I is used.
RE is associated with "1" and 0IRE is associated with "0". The median value of the amplitude of the NRZ identification code is + 20IRE
It is. Identification codes of bit areas B1 to B5 (hereinafter referred to as N) when a letterbox format signal is input.
There are two expected logical values of "RZ identification code", "10110" and "10101", respectively.

By correctly detecting the NRZ identification code, it is possible to determine whether or not the transmission signal is a letterbox type signal. For example, when the NRZ identification code indicates that a letterbox format signal is input, the detection result of the NRZ identification code is used to display a second screen having a wide screen with an aspect ratio of 16: 9. In a television receiver compatible with the generation EDTV, a wide image can be displayed on the entire screen without distortion. In addition, in a current television receiver compatible with NTSC, a wide image having an aspect ratio of 16: 9 can be displayed in a letter box without distortion at a portion having an aspect ratio of 16: 9 in the vertical center of the screen.

However, if the NRZ identification code is erroneously detected or if the detection result is unstable, it may be displayed wide and the top and bottom of the image may be lost even though it is not a letterbox image. In some cases, the wide display and the normal 4: 3 display are alternately repeated, and the display quality may be significantly deteriorated. Furthermore, the load on the deflection system also increases. Therefore, it is extremely important to accurately detect the NRZ identification code, and it is necessary to enable normal detection even in reception in a weak electric field area or reception affected by a ghost. It is necessary to enable accurate detection even when a low-accuracy signal such as a reproduction signal of a (video tape recorder) is input.

FIG. 14 is a block diagram showing a conventional signal identifying apparatus for detecting such an NRZ identifying code. Further, FIG. 15 is a waveform diagram for explaining the operation.

The second generation EDTV signal has its high frequency component removed by a noise removing circuit (not shown), and then the input terminal 1
To the comparator 2. The threshold value control circuit 3 inputs to the comparator 2 a signal having a level of + 20IRE, which is the median value of the amplitude of each bit of the NRZ identification code, as a threshold value. The comparator 2 outputs the NR of the input second generation EDTV signal.
A logical value "1" is output when the level of the Z identification code is greater than or equal to the threshold value, and a logical value "0" when the level is less than the threshold value.
Is output.

Now, it is assumed that the signals in the bit areas B1 to B5 have the waveforms shown in FIG. Comparator 2 compares the input signal with a threshold level of 20 IRE,
"10" at the timing corresponding to the bit areas B1 to B5
The bit string match detection circuit 4 detects whether or not the output of the comparator 2 matches the bit string "10110" or "10101" indicating the letterbox format. In this case, the comparator. Since the output of 2 matches the bit string indicating the letterbox format, the bit string match detection circuit 4 outputs the identification result indicating that the letterbox format signal is input from the output terminal 5. When the output of the device 2 does not match the bit string indicating the letterbox format, the bit string match detection circuit 4 outputs the identification result indicating that the current NTSC system signal is input.

The identification result output from the output terminal 5 is supplied to, for example, a vertical deflection control circuit (not shown). The vertical deflection control circuit of the television receiver having a wide screen controls the vertical amplitude so as to display the upper and lower non-image parts of the second generation EDTV image outside the screen when the identification result indicating the letterbox is given. , Display the main image area on the entire screen.

In this way, the logical value of each bit area is obtained by comparing the level of the NRZ identification code with a predetermined threshold value, and the letter box format is determined depending on whether or not the obtained bit string matches the bit string indicating the letter box. Input of the second generation EDTV signal is detected.

However, due to the influence of the ghost,
If the waveform of the input second-generation EDTV signal is distorted, there is a problem that the NRZ identification code may not be reliably detected.

FIG. 16 is a waveform diagram for explaining this problem.

The waveform diagram of FIG. 16 shows the bit regions B1 to B5 of the second generation EDTV signal affected by ghost, and the true bit string is "10110".
As shown in FIG. 16, the level of each bit area fluctuates due to the influence of the ghost, and even in the bit areas B2 and B5 whose levels should ideally be 0IRE, the bit area B2 is higher than 20IRE. The bit area B5 is almost 0IRE. Therefore, when the second generation EDTV signal shown in FIG. 16 is given to the comparator 2 of FIG. 14, the comparator 2 may determine the logical value of the bit area to be “1” depending on the ghost added to each bit area. , "0" may be determined. In the waveform of FIG. 16, the comparator 2 outputs "11110" as a bit string for the bit areas B1 to B5. That is,
In this case, the bit string coincidence detection circuit 4 outputs an identification result indicating that the input signal is not a letterbox format signal.

[0025]

As described above, in the above-described conventional signal identifying apparatus, it is possible to detect whether or not the input signal is a letterbox type signal due to the waveform distortion caused by the influence of ghost or the like. There was a problem that it could be mistaken.

The present invention has been made in view of the above problems, and it is possible to reliably detect whether or not the signal is a letterbox type signal even when waveform distortion occurs due to the influence of ghost or the like. An object is to provide a signal identification device.

[0027]

According to a first aspect of the present invention, there is provided a signal discriminating apparatus which transmits a plurality of different types of video signals including a predetermined type video signal in which an identification signal including an NRZ format identification code is multiplexed. Of the identification code in the NRZ format, a bit area having a logical value of "1" and a bit area having a logical value of "0" are paired and input at timings of at least one or more bit areas. By calculating an average value calculating means for calculating the average value of the video signal, an adding means for adding an offset value based on the average value to the input video signal, and comparing the output of the adding means with a predetermined threshold value. An identification means for identifying the system of the video signal by judging the logical value of the video signal input at the timing of the identification code of the NRZ format, and the signal according to claim 6 of the present invention. The identification device receives video signals of a plurality of different systems including a predetermined system video signal in which an identification signal including an NRZ format identification code is multiplexed, and the logical value of the NRZ format identification code is "1". Average value calculation means for calculating an average value of the video signals input at the timing of at least one or more bit areas by combining the bit area and the bit area having a logical value of “0”, Comparing means for comparing the video signal with a threshold value based on the average value, and the NR based on a comparison result of the comparing means.
And a discriminating means for discriminating the system of the video signal by judging the logical value of the video signal inputted at the timing of the Z-type discrimination code, which is inputted in claim 1 of the present invention. The video signal is provided to the average value calculating means, and the average value calculating means combines one or more bit areas having a logical value of "1" and a bit area having a logical value of "0". The average value of the video signals input at the timing is calculated. This average value corresponds to the level fluctuation due to the waveform distortion of the input video signal. The adding means cancels the level fluctuation by adding an offset value based on the average value to the video signal. The identifying means determines the logical value by comparing the input video signal with a predetermined threshold value and identifies the system of the input video signal.

According to a sixth aspect of the present invention, the inputted video signal is given to the average value calculating means, and the average value calculating means has a bit area having a logical value of "1" and a bit area having a logical value of "0". And the average value of the video signals input at the timing of one or more bit areas is calculated. This average value corresponds to the level fluctuation due to the waveform distortion of the input video signal. The comparing means compares the threshold value based on the calculated average value with the input video signal. Since the threshold value changes according to the level change, the comparison result corresponds to the logical value of the identification code. The identification means identifies the type of the video signal input from the comparison result.

[0029]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a signal identifying device according to the present invention.

A video signal of the second generation EDTV system (letter box format) or the current NTSC system is input to the input terminal 11. This video signal is obtained by removing high frequency components and then sampling at a timing corresponding to each bit region of the identification signal of the second generation EDTV signal.

This input video signal is given to the subtractor 12. An offset value is given to the subtracter 12 from an adder 14 to be described later, and the offset value is subtracted from the input video signal and output to the bit string coincidence detection circuit 13 and the average value circuit 15. The average value circuit 15 has the expected logical values of "1" and "0" when a letterbox format signal is input, such as bit areas B1 and B2, bit areas B4 and B5 or bit areas B2 and B3. Set the bit area that becomes "" to 1
The signals of a plurality of bit regions of a set or more are added to obtain an average. That is, when a letterbox format signal is input, the output of the average value circuit 15 becomes substantially zero.

FIG. 2 is a circuit diagram showing a concrete structure of the average value circuit 15 in FIG.

The output of the subtractor 12 is the adder 21 of the average value circuit 15.
Given to. The timing generation circuit 23 has a bit area B
The selection pulse is output at the timing of 1, B2, B4, B5, and the clear pulse is generated prior to the selection pulse. The output of the adder 21 is input to the data terminal D of the D flip-flop 22, and the output from the output terminal Q is given to the coefficient unit 24 and also to the adder 21. The D flip-flop 22 clears the output by the clear pulse from the timing generation circuit 23, holds the output of the adder 21 at the timing of the selection pulse, and outputs the output from the output terminal Q.

The adder 21 has bit areas B1, B2, B4,
Input signals at the timing of B5 are added. The coefficient unit 24 sets the output of the D flip-flop 22 to 1
It is adapted to be multiplied by / 4 and output to the integrating circuit 16 (see FIG. 1). In this way, the average value circuit 15 obtains the average value of one or more sets of a plurality of target bit areas.

FIG. 3 is a circuit diagram showing a specific structure of the integrating circuit 16 in FIG.

The output of the average value circuit 15 is the adder of the integration circuit 16.
Given to 31. The clock generation circuit 33 has a bit area B
When the addition result of the outputs of the subtractor 12 at the timing of 1, B2, B4, B5 is output from the average value circuit 15, the clock pulse is output to the D flip-flop 32. The output of the adder 31 is applied to the data terminal D of the D flip-flop 32, and the output from the output terminal Q is output to the amplitude limiting circuit (see FIG. 1) 17 and also to the adder 31. The D flip-flop 32 holds the output of the adder 31 by the clock pulse and outputs it from the output end Q.

The adder 31 integrates the average values obtained by the average value circuit 21 by cumulatively adding them. The integration result is output via the D flip-flop 32. The integration result increases when the average value obtained by the average value circuit 21 is positive, decreases when it is negative, and does not change when it is zero. The average value obtained by the average value circuit 21 due to the level fluctuation of the input video signal due to the waveform distortion can take a value other than zero. That is, the integration result corresponds to the level fluctuation of the input video signal based on the waveform distortion.

In FIG. 1, the output of the integrating circuit 16 is given to the amplitude limiting circuit 17. The amplitude limiting circuit 17 limits the amplitude of the integration result and outputs it to the adder 14. The adder 14 adds the output of the offset circuit 18 and the output of the amplitude limiting circuit 17 and outputs it as an offset value to the subtractor 12. The output of the adder 14 corresponds to the level fluctuation of the input video signal based on the waveform distortion, and the subtractor 12
In, the output of the adder 14 is subtracted from the input video signal to cancel the level fluctuation of the input video signal.

The offset circuit 18 is set so that 0IRE can be set as a threshold value for judging the logical value of the identification code, that is, in the bit string match detection circuit 13 described later,
A predetermined offset value, that is, an output of 20 IRE level in the present embodiment, is output so that the coincidence can be detected only by the sign bit.

The subtractor 12 outputs only the sign bit of the subtraction result to the bit string coincidence detection circuit 13. The bit string match detection circuit 13 associates a positive sign bit with “1” and a negative sign bit with “0” so that the bit string of the logical value corresponding to the sign bit is “1”.
If it is 0110 "or" 10101 ", an identification result indicating that the input video signal is a letterbox format video signal is output, and if not, the input video signal is not a letterbox format video signal. That is, the identification result indicating that it is a video signal of the current NTSC system is output.

FIG. 4 is a graph showing the characteristics of the amplitude limiting circuit 17 in FIG. 1 with the horizontal axis representing the input level and the vertical axis representing the output level.

The amplitude limiting circuit 17 outputs the integration result as it is when the level of the input integration result is within the range of -N to + M, and when the level is below -N, the level is-.
The output of N is output, and the level is + when it is more than + M.
Output the output of M. If the reception is extremely poor,
It is conceivable that the level of the integration result will be extremely high.
If the integration result is given to the adder 14 without limiting the amplitude, the level fluctuation can be canceled even if the level fluctuation of the input video signal is large. However, in this case, even if the NTSC signal in which the video signal is transmitted at the timing of the bit areas B1 to B5 is input, the video signal portion may be erroneously determined as the identification signal.
For this reason, the amplitude limiting circuit 17 is designed to limit the amplitude of the integration result, and its characteristics take into consideration the performance against ghosts and the like and the possibility that the NTSC signal may be erroneously discriminated as the second generation EDTV signal. It is determined.

Next, the operation of the embodiment thus configured will be described with reference to FIGS. FIG. 5 is a waveform diagram showing the signal waveform of each part. FIG. 5 (a) shows the input video signal at the timing of the sampled bit regions B1 to B5, and FIG. 5 (b) shows the output of the subtracter 12. , FIG. 5C shows the selection pulse. FIG. 6 shows FIG.
6A is a timing chart for explaining the operation of the average value circuit 15 and the integration circuit 16 in FIG.
15 inputs, FIG. 6 (b) shows a selection pulse, and FIG.
6C shows a clear pulse, FIG. 6D shows the output of the D flip-flop 22, FIG. 6E shows the output of the average value circuit 15, and FIG. 6F shows the output from the clock generation circuit 33. 6 (g) shows the output of the integrating circuit 16. 7 is a waveform diagram for explaining the operation when a ghost occurs, FIG. 7 (a) shows a video signal, FIG. 7 (b) shows a sampled input video signal, and FIG. 7C shows the output of the subtractor 12, and FIG.
7D shows a signal taken in at the timing of the selection pulse in the D flip-flop 22, and FIG. 7E shows the output of the subtractor 12 after the offset.

A current NTSC video signal or a letterbox type second generation EDTV signal is sampled and input to the input terminal 11 after removing high frequency components. Now, it is assumed that an undistorted letterbox format signal is input to the input terminal 11. Then, the sampling waveforms of the bit areas B1 to B5 in this case are shown in FIG.
It becomes what is shown in (a).

On the other hand, the offset circuit 18 has a level of 20I.
The output of RE is output to the subtractor 12 via the adder 14. Now, assuming that the output of the amplitude limiting circuit 17 is 0, the output of the offset circuit 18 is directly given to the subtractor 12 as an offset value, and the output of the subtractor 12 is shown in FIG.
The result is as shown in FIG. In the present embodiment, the offset circuit 18 causes the input video signal to have -20 IRE.
Is added, and the threshold in the bit string match detection is 0IRE. That is, the bit string coincidence detection circuit 13 can identify the input signal system by detecting the sign bit of the output of the subtractor 12.

The sign bit of the output of the subtractor 12 is given to the bit string coincidence detection circuit 13. In the bit string match detection circuit 13, the bit string of the logical value of the sign bit is “10110”.
Alternatively, it is detected whether it is “10101”. In this case, the bit string of the logical value of the sign bit is “10110”
Therefore, the bit string match detection circuit 13 outputs an identification result indicating that the signal is a letterbox format signal.

Here, it is assumed that the letterbox type video signal input to the input terminal 11 is distorted due to the influence of the ghost. FIG. 7A shows the waveform of the timing of the bit areas B1 to B5 of the video signal in this case. A signal sampled at the timing marked with a circle in FIG. 7A is input to the input terminal 11 (see FIG.
(B)). In this case, the level is higher than 20 IRE at the timing of the bit area B2.

An offset value is added to the input video signal in the subtracter 12. Assuming that the output of the adder 14 is 20 IRE at this point, the output of the subtractor 12 is as shown in FIG.
As shown in (c), the signs of the outputs of the subtractor 12 at the timings corresponding to the bit areas B1 to B5 are "positive, positive, positive, positive, negative", respectively. Bit string match detection circuit
Since 13 uses 0IRE as the detection threshold, the bit string coincidence detection circuit 13 determines at this point that a letterbox format signal has not been input.

On the other hand, the output of the subtractor 12 is also given to the average value circuit 15. FIG. 6A shows the input to the average value circuit 15. The output of the subtractor 12 input to the average value circuit 15 is given to the D flip-flop 22 via the adder 21. Immediately before the signal of the bit region B1 is input, the timing generation circuit 23 outputs the clear pulse shown in FIG. 6 (c), and the D flip-flop 22 clears the output (FIG. 6 (d)). When the signal of the bit area B1 is input, the timing generation circuit 23 operates as shown in FIGS.
The selection pulse shown in (b) is output. As a result, the signal in the bit area B1 is taken into the D flip-flop 22 and output to the coefficient unit 24 and the adder 21 (FIG. 6 (d)).
In FIG. 6, the levels of the bit areas B1 to B5 are B1 to B5, respectively. The coefficient unit 24 outputs the average value shown in FIG. 6E by halving the input signal.

When the signal of the next bit area B2 is input, the adder 21 adds the output B1 of the D flip-flop 22 and the level B2 of the bit area B2 and the level becomes (B1 +
The output of B2) is given to the D flip-flop 22. This output is given to the coefficient unit 24 at the timing of the selection pulse, and 1
It is output as / 4 (FIG. 6 (e)).

The same operation is repeated thereafter, and the level from the coefficient unit 24 becomes (B1 + B2 + B) at the timing of the selection pulse generated immediately after the signal of the bit region B5 is input.
4 + B5) / 4 output, that is, bit areas B1, B2,
The average value of the B4 and B5 levels is output. When a distortion-free letterbox format video signal is input, this average value becomes zero. However, in this case, as shown in FIG. 7D, the average value of the bit areas B1, B2, B4, B5 is a positive value (ΔH) due to the influence of the ghost.

The average value ΔH from the average value circuit 15 is given to the integrating circuit 16. The clock generation circuit 33 of the integration circuit 16 generates a clock pulse (FIG. 6 (f)) after calculating the average value up to the bit area B5. By this clock pulse, the D flip-flop 32 takes in the output of the adder 31 and outputs it. The output of the D flip-flop 32 is given to the adder 31 and cumulatively added. Thus, the bit area B1
, B2, B4, B5 every time the average value is calculated, that is,
The average value is integrated for each field. The output of the integrating circuit 16 is output to the amplitude limiting circuit 17 at the clock pulse timing (FIG. 6 (g)).

Assuming that the integrated output up to the previous field is 0, the integrating circuit 16 outputs ΔH as an integrated value. This integrated value is given to the amplitude limiting circuit 17 to limit the amplitude. If ΔH is a value within the range of −N to + M, this ΔH is given to the adder 14 as it is, and is added to the output of the offset circuit 18 to be subtracted.
Given to 12.

As a result, the signal at the timing of the bit areas B1 to B5 of the next field is offset by-(20 + ΔH) IRE in the subtractor 12, and the signal shown in FIG. Is output. Figure 7
As shown in (e), the sign of the output of the subtracter 12 at the timing corresponding to the bit areas B1 to B5 is "positive, negative, positive, positive, negative", respectively. In this case, the bit string match detection circuit 13 outputs an identification signal indicating that a letterbox format signal is input from the sign bit.

As described above, the positive average value ΔH from the average value circuit 15 acts to reduce the output level of the subtractor 12, and the negative average value ΔH increases the output level of the subtractor 12. Act on. Normally, the average value ΔH from the average value circuit 15 is integrated by the integrating circuit 16, and the integrated value is added to the output of the offset circuit 18 and used as the offset value. That is, the offset value makes it possible to determine the logical value based only on the sign bit, and cancels the level fluctuation due to the waveform distortion.

As a result, even if the level of the input video signal fluctuates due to a ghost or the like, the fluctuation of the level with respect to the detection level can be suppressed with reference to the signal of the timing of the bit areas B1 to B5, and the bit string coincidence detection circuit.
A reliable identification is possible in 13.

As described above, in the present embodiment, the level variation due to the waveform distortion is obtained by the average value of the signals of the pair in which the average value in the normal waveform is 0 in the bit areas B1 to B5, and the average value is integrated. Then, by using the offset value of the input signal, the level fluctuation with respect to the detection level is suppressed, and it is possible to surely determine whether or not it is the letterbox format by the bit string coincidence detection. Also,
Since -20IRE is added to the input signal as the initial offset value, it is possible to make a determination only by the sign bit in the bit string match detection, and the circuit can be simplified. Further, by limiting the amplitude of the integrated value and suppressing the correction level, it is possible to prevent the NTSC signal from being erroneously determined to be a letterbox format signal.

In this embodiment, two sets of 4
Although the average of the signals in one bit area is calculated, it is obvious that the average of the signals in one set of two bit areas may be calculated.

FIG. 8 is a block diagram showing another embodiment of the present invention. In the embodiment of FIG. 1, the determination of the logical value of each bit area is ensured by changing the offset value added to the input video signal according to the level variation of the bit area. In the embodiment, the judgment of the logical value is ensured by changing the threshold value used for the judgment of the logical value according to the levels of the bit areas B1 to B5.

The NTSC signal or the second-generation EDTV signal in the letterbox format is input to the input terminal 11 after the high frequency component is removed and then sampled for each bit of the identification signal. This video signal is given to the average value circuit 41 and the delay device 42. The timing generation circuit 45 is a sample pulse,
Generates clear pulse, select pulse and clock pulse. The sample pulse is a pulse having a bit cycle of the identification signal, the clear pulse is a pulse generated at a timing immediately before the bit area B1 and a timing in the bit area B4, and the selection pulse is a bit area B1, B2, B4, B.
The pulse is generated at the timing of 5, and the clock pulse is the pulse generated at the timing of bit areas B1 and B4.

FIG. 9 is a circuit diagram showing a concrete structure of the average value circuit 41 in FIG.

The average value circuit 41 is composed of an n-bit adder 51 and a (n + 1) -bit D flip-flop 52 with clear. The input video signal is the adder 51 of the average value circuit 41.
Given to. The D flip-flop 52 is given a clear pulse and a selection pulse from the timing generation circuit 45, clears the output at the timing of the clear pulse, takes in the output of the adder 51 at the timing of the selection pulse, and feeds it to the amplitude limiting circuit 46. At the same time as outputting, all bits are output to the adder 51.

The adder 51 is adapted to cumulatively add the input video signals at the selection pulse timings and output them to the D flip-flop 52. The D flip-flop 52 is the adder 51.
If the video signal input to is n bits,
Output the upper n bits excluding the least significant bit. That is, D
The output of the flip-flop 52 is half the output of the adder 51, that is, the average value of the video signal input at the timing of the selection pulse. In the present embodiment, the clear pulse is generated not only immediately before the timing of the bit area B1 but also immediately before the selection pulse corresponding to the bit area B4, and the average value circuit 41 determines the timing of the bit areas B1 and B2. Average value of input signal and bit area B in
Calculate the average value of the input signal at the timing of 4 and B5. The average value of the input signals at the timings of the bit areas B1 and B2 obtained by the average value circuit 41 is used as a threshold for detecting the logical value of the input signals at the timings of the bit areas B1 to B3, and the average value of the bit areas B4 and B5 is calculated. The average value of the input signal at the timing is used as a threshold value for detecting the logical value of the input signal at the timing of the bit areas B4 and B5.

FIG. 10 is a graph for explaining the characteristics of the amplitude limiting circuit 46 with the horizontal axis representing the input level and the vertical axis representing the output level.

As shown in FIG. 10, the amplitude limiting circuit 46 outputs the input as it is when the input level is equal to or more than the predetermined value p and less than q, and when the input level is less than the predetermined value p, the level is p.
Is output, and if the value is equal to or greater than the predetermined value q, the output having the level q is output. The characteristics of the amplitude limiter 46 are determined in the same manner as the amplitude limiter circuit 17 of FIG. 1 in consideration of the performance against ghosts and the like and the possibility of misidentifying the NTSC signal as the second generation EDTV signal.

The output of the amplitude limiting circuit 46 is given to the D flip-flop 47. The D flip-flop 47 holds the output of the amplitude limiting circuit 46 in response to a clock pulse and outputs it to the comparison circuit 48 as a threshold for detecting a logical value. The D flip-flop 47 holds the output until the timing of the next clock pulse. The output of the delay device 42 is also given to the comparison circuit 48.

The delay device 42 is composed of cascaded D flip-flops 43 and 44. The D flip-flop 43 takes in the input video signal by the sample pulse and outputs it to the D flip-flop 44, and the D flip-flop 44 takes in the output of the D flip-flop 43 by the sample pulse and outputs it to the comparison circuit 48. This allows
The delay device 42 delays the input video signal by a 2-bit area and outputs it.

At the timing when the threshold values based on the bit areas B1 and B2 are input to the comparison circuit 48, the input video signals at the timings of the bit areas B1 to B3 are input from the delay device 42, and the threshold values based on the bit areas B4 and B5 are input. Is input from the delay unit 42 to the bit area B4
, B5 timing input video signals are input. The comparison circuit 48 compares whether or not the output of the delay device 42 is larger than the threshold value and outputs the comparison result. That is, the comparison circuit 48 outputs “1” when the output of the delay device 42 is equal to or larger than the threshold value, and outputs “0” to the bit string coincidence detection circuit 49 when the output is smaller than the threshold value. There is.

The bit string match detection circuit 49 has a bit area B1.
To B5 are "10110" or "10"
If it is 101 ", an identification result indicating that the input video signal is a letterbox format signal is output, and if not, an identification result indicating that a letterbox format signal is not input is output. It is supposed to do.

Next, the operation of the embodiment thus configured will be described with reference to the timing chart of FIG. 11 and the waveform chart of FIG. 11A shows the clear pulse, FIG. 11B shows the input to the average value circuit 41, FIG. 11C shows the selection pulse, and FIG. 11D shows the output of the delay unit 42. 11 (e) shows the output of the average value circuit 41, FIG. 11 (f) shows the sample pulse, FIG. 11 (g) shows the clock pulse, and FIG. 11 (h) shows D.
The threshold value from the flip-flop 47 is shown, and FIG. 11 (i) shows the output of the comparison circuit 48.

The NTSC signal or the second-generation EDTV signal in the letterbox format is inputted to the input terminal 11 after the high frequency component is removed and the bit area of the identification signal is sampled. The video signal input to the input terminal 11 is given to the average value circuit 41 and the delay device 42. Now the second generation ED
A TV signal is input. The average value circuit 41 calculates the average value of the bit areas B1 and B2 and the average value of the bit areas B4 and B5.

Immediately before the timing corresponding to the bit region B1 of the second generation EDTV signal, the clear pulse shown in FIG. 11A is generated, and the output of the D flip-flop 52 of the average value circuit 42 is at this timing. It is cleared (FIG. 11 (e)). The signal of the timing of the bit region B1 is given to the D flip-flop 52 via the adder 51. The selection pulse shown in FIG. 11C is generated at the timing of the bit area B1, and the D flip-flop 52 takes in and outputs the signal of the bit area B1. In this case, D
The flip-flop 52 outputs only the upper n bits, thereby halving the input signal and outputting the output B1 / 2 (FIG. 11 (e)).

The D flip-flop 52 outputs all bits B
Output 1 to the adder 51. When the signal at the timing of the next bit area B2 is input, the adder 51 outputs the signals B1 and B2.
Are added and output to the D flip-flop 52. The selection pulse shown in FIG. 11C is generated at the timing of the bit region B2, and the D flip-flop 52 outputs the output (B1 + B2) / 2 of the upper n bits. Thus, at this timing, the average value circuit 41 obtains the average value of the signals at the timings of the bit areas B1 and B2.

In this embodiment, this average value is used as a threshold value for identifying a logical value. Output (B1 + B2) / 2 is 0 when no waveform distortion occurs in the input video signal.
When the waveform distortion occurs, the output level is according to the level fluctuation of the input video signal. When a letter box format video signal is input, bit area B
The input video signal has a level higher than the threshold at the timing of 1, and the input video signal has a level lower than the threshold at the timing of the bit region B2.

The average value from the average value circuit 41 is amplitude-limited by the amplitude limiting circuit 46 to prevent misjudgment,
It is given to the D flip-flop 47. When the average value is within the range of the levels p and q in FIG. 10, the average value is directly given to the D flip-flop 47. The D flip-flop 47 holds the average value whose amplitude is limited at the timing of the clock pulse shown in FIG. 11 (g) and outputs it as a threshold value to the comparison circuit 48. This threshold is held until the next clock pulse occurs.

On the other hand, the input video signal is given to the delay unit 42, delayed by the 2-bit region period by the sample pulse of FIG. 11 (f), and given to the comparison circuit 48. The comparator circuit 48 includes bit regions B1 and B whose amplitudes are limited as thresholds.
Bit area B1 that receives the average value of 2 and is input sequentially
, B2, B3 timing signals and the threshold value are compared.

Now, as shown in FIG. 12, the bit area B
A waveform in which 1 to B5 are distorted by ghost is input. As shown in FIG. 12, the level of the bit area B2 is higher than 20 IRE. When the average value from the average value circuit 41 is within the range of p and q, the threshold value is (20 + ΔH) IRE as shown in FIG. As a result, the comparison circuit 48 determines that the timing signal of the bit area B1 is higher than the threshold value and the timing signal of the bit area B2 is lower than the threshold value, and outputs the comparison result shown in FIG. 11 (i). .

At the timing of the bit area B4, a clear pulse (FIG. 11A) is first generated to clear the output of the D flip-flop 52, and then a selection pulse (FIG. 11C) is generated. Bit area B4 output B4
Is taken in. Output B4 from D flip-flop 52
Is output to the adder 51. At the timing of the next bit area B5, the output (B4 + B5
) / 2 is output to the amplitude limiting circuit 46.

On the other hand, at this timing, the D flip-flop 47 holds the average value of the amplitude limited bit areas B1 and B2 as a threshold value, and the timing signal of the bit area B3 input to the comparison circuit 48 is This threshold is compared. As shown in FIG. 12, the level of the signal in the bit region B3 is higher than the threshold value, and the comparison circuit 48
The comparison result shown in 1 (i) is output.

After the bit area B3 is compared, the D flip-flop 47 uses the average value of the bit areas B4 and B5 whose amplitude is limited by the clock pulse as a threshold value to make a comparison circuit 48.
(FIG. 11 (h)). In FIG. 12, since the levels of the bit areas B4 and B5 are lowered, the threshold value is also lowered to (ΔH '+ 20) IRE. The comparison circuit 48 compares this threshold value with the signals of the bit areas B4 and B5,
The comparison result (FIG. 11 (i)) that the level of the bit area B4 is larger than the threshold value and the level of the bit area B5 is smaller than the threshold value is output.

In this way, "10110" is given to the bit string coincidence detection circuit 49 as the comparison result for the bit areas B1 to B5. The bit string coincidence detection circuit 49 outputs an identification result indicating that a letterbox format signal has been input from the comparison result.

As described above, also in this embodiment, the same effect as that of the embodiment of FIG. 1 can be obtained.

[0083]

As described above, according to the present invention, it is possible to reliably detect whether or not a signal is a letterbox format signal even if waveform distortion occurs due to the influence of a ghost or the like. Have.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a signal identification device according to the present invention.

FIG. 2 is a circuit diagram showing a specific configuration of an average value circuit 15 in FIG.

FIG. 3 is a circuit diagram showing a specific configuration of an integrating circuit 16 in FIG.

FIG. 4 is a graph showing characteristics of an amplitude limiting circuit 17 in FIG.

FIG. 5 is a waveform diagram for explaining the operation of the embodiment.

FIG. 6 is a timing chart for explaining the operation of the embodiment.

FIG. 7 is a waveform chart for explaining the operation of the embodiment.

FIG. 8 is a block diagram showing another embodiment of the present invention.

9 is a circuit diagram showing a specific configuration of an average value circuit 41 in FIG.

10 is a graph showing characteristics of the amplitude limiting circuit 46 in FIG.

FIG. 11 is a timing chart for explaining the operation of the embodiment of FIG.

FIG. 12 is a waveform chart for explaining the operation of the embodiment of FIG.

FIG. 13 is an explanatory diagram for explaining an identification signal.

FIG. 14 is a block diagram showing a conventional signal identification device.

FIG. 15 is a waveform diagram for explaining the operation of the conventional example.

FIG. 16 is a waveform chart for explaining the problems of the conventional example.

[Explanation of symbols]

12 ... Subtractor, 13 ... Bit string match detection circuit, 14 ... Adder,
15 ... Average value circuit, 16 ... Integration circuit, 17 ... Amplitude limiting circuit, 18
… Offset circuit

Claims (10)

[Claims] 1. A plurality of video signals of different systems including a video signal of a predetermined system in which an identification signal containing an NRZ format identification code is multiplexed are input, and the logical value of the NRZ format identification code is "1". Average value calculating means for calculating an average value of the video signals input at the timing of at least one set of a plurality of bit areas by grouping the bit area of 1 and a bit area having a logical value of "0"; An adding means for adding an offset value based on the value to the input video signal, and a logic of the video signal input at the timing of the NRZ format identification code by comparing the output of the adding means with a predetermined threshold value. And a discriminating means for discriminating a value to discriminate the video signal system. 2. The signal discriminating apparatus according to claim 1, wherein the adding means includes an integrating means for integrating the average value, and generates the offset value based on the integrated value. 3. The adding means comprises an amplitude limiting means for limiting the offset value to a predetermined amplitude in consideration of the identification performance of a logical value and the possibility of misjudgment. The signal identification device described. 4. The adding means comprises offset means for generating a predetermined initial offset value based on a threshold value used by the identifying means for determining a logical value, and the value based on the average value and the initial offset value are included. 2. The signal identifying apparatus according to claim 1, wherein the offset value is added to generate the offset value, and the identifying unit determines the logical value based on a sign of an output of the adding unit. 5. The addition means limits the integrated value obtained by integrating the average value to a predetermined amplitude in consideration of the identification performance of the logical value and the possibility of misjudgment, and the logical value of the identification code. The signal identification device according to claim 1, wherein the offset value is generated by adding it to a predetermined initial offset value based on a threshold value used for the determination. 6. A video signal of a plurality of different systems including a video signal of a predetermined system in which an identification signal containing an identification code of NRZ format is multiplexed, and a logical value of the identification code of the NRZ format is "1". Average value calculating means for calculating an average value of the video signals input at the timing of at least one set of a plurality of bit areas by combining the bit area of the Comparing means for comparing the video signal with a threshold value based on the average value, and judging the logical value of the video signal input at the timing of the NRZ format identification code based on the comparison result of the comparing means. A signal discriminating apparatus comprising: a discriminating means for discriminating a video signal system. 7. The signal discriminating apparatus according to claim 6, wherein the comparing means includes an integrating means for integrating the average value, and the threshold value is generated based on the integrated value. 8. The comparing means comprises an amplitude limiting means for limiting the threshold value to a predetermined amplitude in consideration of the identification performance of a logical value and the possibility of misjudgment.
The signal identification device described in 1. 9. The signal identifying device according to claim 6, wherein the identifying means determines the logical value based on the sign of the comparison result. 10. The signal discriminating apparatus according to claim 3, wherein the amplitude limiting means outputs an output sliced with a predetermined maximum value and a minimum value.