JPH099167A - Timing generating circuit for identification control signal - Google Patents

Abstract

PURPOSE: To generate a timing pulse for decoding an identification control signal to decode accurately an identification control signal even when the position of a horizontal synchronizing signal is fluctuated. CONSTITUTION: A 1st timing signal generating circuit 14 uses a start point of a vertical synchronizing signal as a trigger to count a horizontal synchronizing signal and provides an output of a 1st timing pulse within a period between a rising of the horizontal synchronizing signal for a 22nd and 285th horizontal video periods with an identification control signal superimposed thereon and a rising of a 1st bit of a 1st NRZ signal. A 2nd timing signal generating circuit 15 generates a reception pulse based on the 1st timing pulse as a reference and receives a video signal fed to an input terminal 11 for a prescribed period based on the reception pulse and provides an output of a timing pulse to receive the identification control signal based on part of the video signal. A decoding circuit 11 receives data of the identification control signal in the timing of the timing pulse and provides an output of decoded data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a current television broadcasting system and an EDTV-compatible with this broadcasting system.
The present invention relates to a timing generation circuit for an identification control signal for identifying which of the new television broadcasting systems called the 2 system is being received.

[0002]

2. Description of the Related Art Recently, as a next-generation terrestrial television broadcasting system, EDTV-which aims at wide aspect ratio, high image quality and high sound quality while maintaining compatibility with the current system.
A new broadcasting system called the 2 system is about to be introduced.

The EDTV-2 system controls identification information relating to various modes such as differences in processing of transmitted video signals, and information and sequences used as a reference such as phase and level in signal processing on the receiving side. The identification control signal is inserted in the periods of the 22nd and 285th horizontal video signals of the video signal in order to transmit the control information used for this purpose.

The structure of the identification control signal will be described with reference to FIG. FIG. 12 shows an identification control signal in one horizontal video period. First behind the color burst, from the pedestal and from there 40 IRE (1V = 14
0IRE) Contains bit information according to two high level states, the first and second bits are reference timing, and the third bit is letterbox (aspect ratio 9: 1
There is a first NRZ (non-return-to-zero) signal consisting of information of the 1st bit to the 5th bit, where the 4th bit is parity information. The length of 1 bit is 7 SC (cycle) of fsc (color subcarrier frequency), and the length of 1 bit of the following signals is also the same.

Next, following the first NRZ signal, the amplitude is ± 2.
A carrier of 0 IRE and a frequency of fsc, which includes bit information according to two phase states of in-phase and anti-phase with the color burst phase. The sixth bit is a field number, the seventh bit is a multiple phase, and the eighth bit is vertical time reinforcement Existence, 9th bit with or without vertical reinforcement, 10th bit with or without horizontal reinforcement, 11th
There is an fsc signal in which the bit is the presence or absence of horizontal reinforcement precombing and the 18th to 23rd bit information.

Following the fsc signal is a second NRZ signal consisting of 1-bit information of the 24th bit at the pedestal level, which includes bit information due to the pedestal and two level states 40IRE higher than it.

Since the above signals are inserted in the 22nd and 285th horizontal video periods of the video signal corresponding to the picture period in the current system, it is necessary to determine whether the signal is an existing video signal or an identification control signal. Therefore, the confirmation signal is inserted after the second NRZ signal.

As the confirmation signal, a carrier whose amplitude is ± 15 IRE and 4/7 of the color subcarrier frequency is selected under the condition that it cannot theoretically exist in the existing video signal. It is possible to do this, and 3 bits from the 25th to the 27th bits are applied to this.

Hereinafter, the first and second NRZ signals, fs
The c signal and the confirmation signal are collectively referred to as an identification control signal. At the receiver, the bit information must be decoded and determined from these signals, and the identification information and control information must be extracted without misjudgment.

In order to decode these bit information,
It is necessary to generate the timing pulse TP synchronized with the position of each bit of the identification control signal.

A conventional timing pulse generation circuit will be described with reference to FIG. First, the 22H / 285H detection signal output circuit 131 counts the horizontal sync signal by using the start point of the vertical sync signal as a trigger, and extracts the gate pulse GP in the 22nd and 285th horizontal video periods carrying the identification control signal. Then, it outputs to the timing pulse generation circuit 132. The timing pulse generation circuit 132 uses the start point of the gate pulse GP shown in FIG. 14 as a trigger to count the clock of fsc to generate the timing pulse TP at the position of each bit of the identification signal. The decoding circuit 133 takes in the data of the identification control signal at the timing of the timing pulse TP and outputs the decoded data.

Since the gate pulse GP is created with the horizontal synchronizing signal as a reference, the accurate timing pulse TP can be generated by the method described above, and each bit information can be obtained.

However, the position of the horizontal synchronizing signal, which is the reference, may be shifted in order to maintain the frame continuity, for example, at the time of relay of a broadcasting station and at the time of reproducing a still image by video or the like. The position shift of this horizontal sync signal is
Up to ± 710 nsec is allowed based on the position of the color burst. Therefore, if the gate pulse GP is used as a trigger for counting as shown in FIG.
There is a possibility that the position of the gate pulse GP also shifts due to the position shift of the horizontal synchronizing signal, and the timing pulse TP itself shifts ± 710 nsec (± 2.55 SC) with respect to each bit of the identification signal.

As shown in FIG. 16, since the bit width of the decoded signal is 7 SC (1.96 μS), the jitter allowable range of the timing pulse TP is significantly reduced from ± 3.5 SC to ± 1 SC, and in the worst case. However, there arises a problem that the decoded data cannot be taken in due to waveform delay, dullness, and the like.

[0015]

As described above, when the conventional identification control signal timing generation circuit generates the timing pulse for decoding the identification signal, if the horizontal synchronization signal is used as the timing pulse generation reference, the timing There is a problem that the position of the pulse changes, and in the worst case, the decoded data cannot be captured. The present invention is to generate an identification signal decoding timing pulse that accurately decodes an identification control signal even if the position of the horizontal synchronizing signal changes.

[0016]

In order to solve the above-mentioned problems, the timing control circuit for identification control signal of the present invention, at least during one horizontal video period of a television signal,
A horizontal sync signal, a first color subcarrier signal having color reference information, and a type / combination / processing of a video / augmentation signal which is inserted at a position different from that of the first color subcarrier signal and transmitted. With identification function information used to identify the difference between control signals and control function information used to control the functions and sequences used as a reference for phase and level in signal processing on the receiver side. No. 1 NRZ signal, the first color subcarrier signal and the first NRZ signal
It is inserted at a position different from the signal and is used as a reference such as phase / level in the signal processing on the receiver side and the identification function information specified to identify the difference in the type / combination / processing of the transmitted video / reinforced signal. A second color subcarrier signal having control function information used to control the functions and sequences used, the first color subcarrier signal, the first NRZ signal and the second color subcarrier. The second NRZ signal inserted at a position different from the carrier signal, and the first color subcarrier signal, the first NRZ signal, the second color subcarrier signal, and the second NRZ signal inserted at different positions. However, the identification function information that is specified to identify the difference in the type, combination, and processing of the transmitted video, augmented signal, and the functions and sequences that are used as the phase and level standards in signal processing on the receiver side. In the video signal processing circuit for processing the video signal composed of the confirmation carrier signal having the predetermined frequency and the amplitude, which has the control function information used for controlling the can and the like, the position is not changed. A first timing signal is generated from the horizontal synchronizing signal.
Of the timing signal generating means and the capturing pulse generated based on the first timing signal to capture a video signal in a predetermined period, and generate a capture timing signal of a signal having the control function based on the captured video signal. And a second timing signal generating means.

[0017]

With the above configuration, the video signal is captured for a predetermined period by the capture pulse generated with the horizontal synchronizing signal as a reference, and the capture timing signal of the identification control signal with reference to a part of the captured video signal. As a result, even if the position of the horizontal sync signal fluctuates,
It is possible to accurately decode the identification control signal without shifting the position of the timing pulse.

[0018]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a circuit configuration diagram for explaining one embodiment of the present invention. In FIG. 1, the input terminal 11 to which the video signal is supplied is connected to the input of the decoding circuit 11. The output of the decoding circuit 12 is connected to the output terminal 13. The input terminal 11 is the first timing signal generation circuit 14
And an input of the second timing signal generation circuit 15 as well. The output of the first timing signal generating circuit 14 is connected to the other input of the second timing signal generating circuit 15.

The first timing signal generation circuit 14 corresponds to the 22H / 285H detection signal output section 14 in FIG. 13, counts horizontal synchronizing signals using the vertical synchronizing signal start point as a trigger, and outputs the identification control signal. Second superimposed
The first timing pulse is output within the period from the rise of the horizontal synchronizing signal in the second and 285th horizontal video periods to the rise of the first bit of the first NRZ signal. The second timing signal generation circuit 15 generates a capture pulse with the first timing pulse as a reference, captures the video signal supplied to the input terminal 11 for a predetermined period by this capture pulse, and outputs one of the video signals. The timing pulse for capturing the identification control signal is output with the section as a reference. The decoding circuit 11 takes in the data of the identification control signal at the timing of the timing pulse and outputs the decoded data.

In this embodiment, the timing pulse for fetching the identification control signal is not a pulse depending on the position of the horizontal synchronizing signal, which tends to fluctuate, but a timing based on a part of the video signal which is a completely independent signal. Since the pulse is used, there is no influence of the position shift of the horizontal sync signal,
The decoded data of the identification control signal can be stably fetched. Therefore, the identification control signal can be accurately decoded even if the horizontal synchronization signal fluctuates.

Referring to FIG. 2, the second embodiment in FIG.
A specific example of the timing generation circuit will be described together with the signal waveforms in FIG. Second timing generation circuit 15
Is a capture pulse generator 15a, an AND circuit 15b,
It is composed of a counter 15c. The capture pulse generator 15a generates a capture pulse of A in a period including the first 1 bit of the first NRZ signal of the identification control signal with reference to the first timing pulse of the first timing signal generation circuit 14. .

The AND circuit 15b takes in the video signal including the identification control signal of FIG. 3 only during the period when the taking-in pulse is present, and outputs the B pulse to the counter 15c.
The counter 15c starts counting by using the rising edge of the first 1 bit of the fetched first NRZ signal as a trigger, and outputs a C timing pulse to the position of each bit of the identification control signal.

In this example, the first pulse is generated when the capture pulse is generated.
Since the timing pulse of 1 is used as a reference, the capture pulse is affected by the positional deviation of the horizontal synchronizing signal. However, since the rising edge of the first 1 bit of the first NRZ signal is used for the trigger of the counter 15c, there is no influence of the position shift of the horizontal synchronizing signal, and the decoded data of the identification control signal can be stably fetched. You can

Another embodiment of the present invention will be described with reference to the circuit configuration diagram of FIG. In this embodiment, when a video signal is taken in, it is output to the second timing generation circuit 15 after passing through a window means 41 that does not pass signals other than the signal that triggers the timing pulse generation. Alternatively, the window means 41 outputs the video signal and, at the same time, determines whether or not the video signal is a signal that triggers the timing pulse generation, and outputs the determination result to the second timing generation circuit 15.

In this embodiment, the received signal is the EDT.
Not a V-2 but a normal video signal other than the identification signal is 22
H, 285H, the second timing generation circuit 1
It is possible to prevent the video signal 5 from outputting the timing pulse by mistakenly using the video signal as a trigger for generating the timing pulse.

FIG. 5 is a circuit configuration diagram for explaining a second embodiment of the present invention. In this embodiment, the window means is an LPF 51 that allows a predetermined frequency component to pass therethrough. The LPF 51, as shown in FIG.
It is a filter having a cutoff frequency of 500 kHz for R and C.

Since the LPF 51 attenuates the high frequency component of the signal, only the DC component of the video signal can pass through. Therefore, disturbances such as high-frequency components of the video signal and noise are
H, 285H, the second timing generation circuit 1
It is possible to prevent the disturbance of the high frequency component or noise of the video signal from being output as a timing pulse by mistake as a trigger for timing signal generation.

A third embodiment of the present invention will be described with reference to the circuit configuration diagram of FIG. 6 together with the signal waveforms of FIG. In this embodiment, the window means is, for example, the first
The threshold value is provided above and below the level that the first 1 bit of the NRZ signal can take, and the level window 61 allows only signals having levels between the above and below threshold values to pass.

That is, the level window 61 to which the video signal is supplied includes comparators 62a and 62b and an AND gate.
It is composed of a circuit 63. The comparator 62a compares the supplied video signal with the threshold value Vref1 and outputs a signal indicated by A in FIG. 7, which becomes Lo when the potential of the video signal is higher than Vref1 and becomes Hi when the potential is lower than Vref1. The comparator 62b is
The video signal is compared with the threshold value Vref2, and if the electric potential of the video signal is higher than the threshold value Vref2, then it is Hi, and if it is lower, then the signal is Lo.
The signal indicated by B is output. The AND circuit 63 calculates the logical product of the comparators 62a and 62b and outputs the signal shown in C of FIG. The output of the AND circuit 63 becomes Hi only when the potential of the video signal is between the threshold values Vref1 and Vref2. That is, the threshold values Vref1 and Vref
Only signals with levels between 2 pass.

As a result, when a similar signal of the NRZ signal having a large DC level change is on 22H / 285H in the period corresponding to the rising or falling of the first bit of the first NRZ signal, It is possible to prevent the second timing generation circuit 15 from malfunctioning and outputting a timing pulse.

Further, a fourth embodiment of the present invention will be described with reference to the circuit configuration diagram of FIG. 8 and the signal waveforms of FIG. In this embodiment, the window means is the pattern window 81. This pattern window 8
1 sets a threshold value at a level above and below the possible level of the first 1 bit of the first NRZ signal, and passes only a signal between the levels above and below the threshold value. At the same time, the video signal is the "trigger signal for timing pulse generation" only when the level changes of the first and second bits of the first NRZ signal and the level change of the input video signal match. Is determined, and the determination result is the second timing generation circuit 1
5, the timing pulse is output from the second timing generation circuit 15 only when the determination result is “a trigger signal for timing pulse generation”. This utilizes the fact that the signals of the first and second bits of the first NRZ signal are fixed.

In FIG. 8, specifically, the pattern window 81 includes a level window 82a for passing a signal between threshold values Vref1 and Vref2 and threshold values Vref3 and Vre.
A level window 82b for passing a signal between f4 and a pattern check circuit 83 are provided therein. The level window 82a is the same as the level window 61 in FIG. 6, and detects the signal of the first bit of the first NRZ signal. The level window 82b has a threshold different from that of the level window 82a, and detects the signal of the second bit of the first NRZ signal.

As the video signal, the signal shown in A of FIG. 9 which has passed through the level window 82a is output to the second timing generation circuit 15. At the same time, the pattern check circuit 83
Is a signal whose level is between the threshold values Vref1 and Vref2 during the first bit period of the first NRZ signal, and which indicates that the first NRZ signal has Only when the signal has a level between the threshold values Vref3 and Vref4 in the second bit period, the video signal is determined to be "a trigger signal for timing pulse generation", and the determination result is the second timing generation circuit. Output to 15. The second timing generation circuit 15 outputs the timing pulse only when the result of the determination is “the trigger signal for generating the timing pulse”.

Here, a specific configuration example of the pattern check circuit 83 will be described with reference to FIG. The pattern check circuit 83 includes a delay circuit 83a and an AND circuit 83.
It is composed of the b and D flip-flops 83c.

The operation of the pattern check circuit 83 will be described with reference to the signal waveform of FIG. Delay circuit 83
a is the output signal of the level window 82a shown in A,
As shown in B, it is delayed by one bit of the identification control signal. A
The ND circuit 83b takes the logical product of the output of the delay circuit 83a and the output of the level window 82b shown at C and outputs the signal shown at D. This output shows that the input video signal is the first NR
Threshold values Vref1 and Vref during the first bit of the Z signal
The signal of the second bit of the first NRZ signal is generated only when the signal of the level is between 2 and the signal of the level between the threshold values Vref3 and Vref4 during the second bit period of the first NRZ signal. Since the period is Hi, the output signal of the AND circuit 83b in the period of the second bit of the first NRZ signal is D
The flip-flop 83c holds the signal, and outputs the signal indicated by E as the "timing pulse generation trigger signal" determination result. That is, when the output of the pattern check circuit 83 for the second and subsequent bits of the first NRZ signal is Hi, the video signal is a "timing pulse generation trigger signal", and L
In the case of o, it can be determined that it is not a "timing pulse generation trigger signal".

The result of this discrimination is used as a pattern check circuit 83.
Output from the second and subsequent bits of the first NRZ signal, the video signal is not the identification control signal, and the pseudo signal of the NRZ signal exists during the first bit of the first NRZ signal. In this case, the second timing generation means 2
The timing pulse is output in the first bit period of the first NRZ signal, but thereafter, the timing pulse is not output depending on the determination result of the pattern check circuit 83. As a result, 2 of the first NRZ signal of the video signal
It is possible to prevent decoding of the signal in the period after the bit.

Further, the discrimination result of the pattern check circuit 83 is output to the discrimination control signal decoding circuit 11, and if the discrimination result is "not a trigger signal for timing pulse generation", the discrimination control signal is not decoded. Good.

In this embodiment, it is determined whether the video signal is a trigger signal for timing pulse generation or not based on the temporal fluctuation of the signal level, and therefore the possibility of misjudgment is further reduced.

As described above, the embodiments of the present invention are not limited to the above-mentioned embodiments, and various modifications and applications are possible without changing the gist of the invention. For example, the possibility of misjudgment can be further reduced by using a combination of the LPF and the level check window in the window configuration.

[0040]

As described above, according to the timing generation circuit for the discrimination control signal of the present invention, even if the position of the horizontal synchronizing signal changes, the position of the timing pulse does not shift, and the discrimination control signal is generated. Can be accurately decoded.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram for explaining a first embodiment of the present invention.

2 is a circuit configuration diagram for specifically explaining a second timing generation circuit in FIG.

FIG. 3 is a signal waveform diagram for explaining the operation of FIG.

FIG. 4 is a circuit configuration diagram for explaining another embodiment of the present invention.

FIG. 5 is a circuit configuration diagram for explaining a second embodiment of the present invention.

FIG. 6 is a circuit configuration diagram for explaining a second another embodiment of the present invention.

FIG. 7 is a signal waveform diagram for explaining the operation of FIG.

FIG. 8 is a circuit configuration diagram for explaining a third other embodiment of the present invention.

FIG. 9 is a signal waveform diagram for explaining the operation of FIG. 8;

10 is a configuration diagram for specifically explaining the pattern check circuit of FIG.

11 is a signal waveform diagram for explaining the operation of FIG.

FIG. 12 is a configuration diagram of an identification control signal of the EDTV-2 television broadcasting system.

FIG. 13 is a configuration diagram of a conventional timing pulse generation circuit.

FIG. 14 is an explanatory diagram for explaining a problem of the conventional timing pulse generation method.

FIG. 15 is an explanatory diagram for explaining a problem of the conventional timing pulse generation method.

FIG. 16 is an explanatory diagram for explaining a problem of the conventional timing pulse generation method.

[Explanation of symbols]

12 ... Decoding circuit, 14 ... First timing signal generating circuit, 15 ... Second timing signal generating circuit, 15a ... Take-in pulse generating section, 15b ... AND circuit, 15c ... Counter, 41 ... Window means, 51 ... LPF, 61 ...
Level window, 81 ... 22H / 285H detection signal output circuit.

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[Procedure amendment]

[Submission date] August 15, 1995

[Procedure Amendment 1]

[Document name to be amended] Drawing

[Name of item to be corrected] Figure 7

[Correction method] Change

[Correction contents]

FIG. 7

Claims (6)

[Claims] 1. A horizontal sync signal, a first color subcarrier signal having color reference information, and a position different from the first color subcarrier signal during at least one horizontal video period of a television signal. Identification function information that is used to identify the difference in the type, combination, and processing of the video that is inserted and transmitted, the enhancement signal, and the function or sequence that is used as a reference such as phase and level in the signal processing on the receiver side. A first NRZ signal provided with control function information used to control, etc., and a video transmitted by inserting at a position different from the first color subcarrier signal and the first NRZ signal. Identification function information used to identify differences in the types, combinations, and processing of augmented signals, as well as functions and sequences used as standards for phase and level in signal processing on the receiver side. A second color subcarrier signal having control function information used for controlling, and a first color subcarrier signal, a first NRZ signal, and a second color subcarrier signal inserted at different positions. The second N
RZ signal, the first color sub-carrier signal, the first NRZ signal, the second color sub-carrier signal and the second NRZ signal are inserted at different positions, and the type of video / reinforcement signal transmitted Identification function information used to identify differences in combinations and processing and control function information used to control functions and sequences used as a reference for phase and level in signal processing on the receiver side. In a video signal processing circuit for processing a video signal composed of a confirmation carrier signal having a predetermined frequency and amplitude, a first timing signal is generated from the horizontal synchronizing signal whose position tends to change. A first timing signal generating means, and a capturing pulse generated based on the first timing signal to capture a video signal for a predetermined period, and the captured video signal Identification control signal timing generating circuit, characterized in that a second timing signal generating means for generating a latch timing signal of the signal with the control function based on. 2. The capture pulse is at least the first pulse.
2. The timing generation circuit for the identification control signal according to claim 1, comprising a period including the first 1 bit of the NRZ signal. 3. The discrimination control signal according to claim 2, further comprising window means for preventing a signal other than a trigger for generating the fetch timing signal from being fetched when the video signal is fetched. Timing generator circuit. 4. The timing control circuit for an identification control signal according to claim 3, wherein the window means is an LPF which allows passage of only a predetermined frequency component of the video signal. 5. The timing control circuit for an identification control signal according to claim 3, wherein the window means is a level window that allows only a predetermined level component of the video signal to pass therethrough. 6. A pattern in which the window means regards the video signal as a trigger signal for generating the capture timing signal when the video signal matches the first 1-bit to 2-bit change pattern of the first NRZ signal. 4. The timing generation circuit for an identification control signal according to claim 3, wherein the timing control circuit is a window.