JPH0927597A - Semiconductor device and its manufacture - Google Patents

Semiconductor device and its manufacture

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Publication number
JPH0927597A
JPH0927597A JP7176427A JP17642795A JPH0927597A JP H0927597 A JPH0927597 A JP H0927597A JP 7176427 A JP7176427 A JP 7176427A JP 17642795 A JP17642795 A JP 17642795A JP H0927597 A JPH0927597 A JP H0927597A
Authority
JP
Japan
Prior art keywords
conductive film
capacitor
heat treatment
semiconductor device
laminated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7176427A
Other languages
Japanese (ja)
Inventor
Masahiro Uejima
正弘 上島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP7176427A priority Critical patent/JPH0927597A/en
Publication of JPH0927597A publication Critical patent/JPH0927597A/en
Pending legal-status Critical Current

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  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which has a simple manufacturing process and can ensure the capacitance of a capacitor and to provide its manufacturing method. SOLUTION: An electrode, on one side, which constitutes a capacitor is a laminated body wherein expansive conductive films 32 whose grains are grown by a heat treatment and thermally stable conductive films 31 which are stable against a heat treatment are laminated alternately. Peripheral edge parts of the expansive conductive films protrude from peripheral edge parts of the thermally stable conductive films which are laminated at their upper and lower parts. In order to realize such a structure, the laminated body is manufactured in a laminated-film formation process wherein the expansive conductive films whose grains are grown by the heat treatment and the thermally stable conductive films which are stable against the heat treatment are formed alternately, in a patterning process in which the laminated body laminated in the film formation process is patterned and in a heat treatment process wherein the patterned laminated body is heat-treated and the expansive conductive films are grain- grown.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、DRAM等のキャ
パシタを有する半導体装置のキャパシタ容量が増加した
半導体装置及びその製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a capacitor such as a DRAM having an increased capacitor capacity and a manufacturing method thereof.

【0002】[0002]

【従来の技術】半導体装置の高集積化に伴い、最小のデ
ザインルールは微細化され、DRAMやSRAM等のメ
モリデバイスのセル面積も縮小化されてきている。この
ため、こららのメモリデバイスの構成素子であるキャパ
シタの容量確保が困難となってきた。
2. Description of the Related Art With the high integration of semiconductor devices, the minimum design rule has been miniaturized, and the cell area of memory devices such as DRAM and SRAM has been reduced. For this reason, it has become difficult to secure the capacity of the capacitor, which is a constituent element of these memory devices.

【0003】このようなキャパシタの容量を増加させる
キャパシタ構造として、図3に示すものがある。図3の
キャパシタの製造工程は、図3(A)に示すように、シ
リコンなどの基板2に、これと接続された短軸柱状の下
部電極3を形成し、次に、図3(B)に示すように、こ
の下部電極3を被覆して絶縁膜4を形成し、更に、図3
(C)に示すように、上部電極としての導電膜5を絶縁
膜4に被覆して成膜することにより製造される。
As a capacitor structure for increasing the capacity of such a capacitor, there is one shown in FIG. In the manufacturing process of the capacitor of FIG. 3, as shown in FIG. 3A, a short-axis columnar lower electrode 3 connected thereto is formed on a substrate 2 made of silicon or the like, and then, as shown in FIG. As shown in FIG. 3, an insulating film 4 is formed by covering the lower electrode 3, and further, as shown in FIG.
As shown in (C), it is manufactured by covering the insulating film 4 with the conductive film 5 as the upper electrode to form a film.

【0004】このようなキャパシタ素子は、キャパシタ
を立体化した分、容量を増加できるが、最近のセル面積
の縮小化にはその容量は不十分である。この他、キャパ
シタの容量確保のために種々の提案がなされているが、
メモリセル面積を縮小化し、かつキャパシタの表面積を
大きくとるために、キャパシタ素子の電極構造及び形成
プロセスは非常に複雑化し、工程数も大幅に増加してき
ている。
[0004] Such a capacitor element can increase the capacity by making the capacitor three-dimensional, but the capacity is insufficient for the recent reduction of the cell area. In addition, various proposals have been made to secure the capacity of the capacitor,
In order to reduce the memory cell area and increase the surface area of the capacitor, the electrode structure and forming process of the capacitor element have become very complicated, and the number of steps has also increased significantly.

【0005】本発明は、上記事情に鑑みなされたもの
で、製造工程が簡単でキャパシタの容量を確保できる半
導体装置及びその製造方法を提供することを目的とす
る。
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor device in which a manufacturing process is simple and a capacitance of a capacitor can be secured, and a manufacturing method thereof.

【0006】[0006]

【課題を解決するための手段】本発明は、上記目的を達
成するため、次の半導体装置及びその製造方法を提供す
る。 (1)キャパシタが多数形成された半導体装置におい
て、該キャパシタを構成する一方の電極が、熱処理によ
ってグレイン成長した膨張導電膜と熱処理に対して安定
な熱安定性導電膜とが交互に積層された積層体であると
共に、該膨張導電膜の周縁部がその上下に積層されてい
る熱安定性導電膜の周縁部から突出していることを特徴
とする半導体装置。 (2)前記膨張導電膜がシリサイドで構成されている上
記(1)記載の半導体装置。 (3)前記熱安定性導電膜がポリシリコンで構成されて
いる上記(1)又は(2)記載の半導体装置。 (4)半導体装置のキャパシタを構成する一方の電極を
形成する半導体装置の製造方法において、熱処理によっ
てグレイン成長する膨張性導電膜と熱処理に対して安定
な熱安定性導電膜とを交互に成膜する積層膜形成工程
と、積層膜形成工程によって積層された積層体をパター
ニングするパターニング工程と、パターニングされた積
層体を熱処理して膨張性導電膜をグレイン成長させる熱
処理工程とを有することを特徴とする半導体装置の製造
方法。 (5)前記膨張性導電膜がシリサイドであり、前記熱安
定性導電膜がポリシリコンである上記(4)記載の半導
体装置の製造方法。
In order to achieve the above object, the present invention provides the following semiconductor device and its manufacturing method. (1) In a semiconductor device in which a large number of capacitors are formed, one electrode constituting the capacitor is formed by alternately laminating an expanded conductive film that is grain-grown by heat treatment and a heat-stable conductive film that is stable against heat treatment. A semiconductor device, which is a laminated body, wherein the peripheral edge portion of the expanded conductive film projects from the peripheral edge portions of the heat-stable conductive films that are stacked above and below the expanded conductive film. (2) The semiconductor device according to (1), wherein the expanded conductive film is made of silicide. (3) The semiconductor device according to (1) or (2), wherein the heat-stable conductive film is made of polysilicon. (4) In a method of manufacturing a semiconductor device, in which one electrode forming a capacitor of a semiconductor device is formed, an expansive conductive film that undergoes grain growth by heat treatment and a heat stable conductive film that is stable against heat treatment are alternately formed. And a heat treatment step of subjecting the patterned laminate to a heat treatment to grain-expand the expansive conductive film by patterning the laminated body laminated by the laminated film formation step. Of manufacturing a semiconductor device. (5) The method for manufacturing a semiconductor device according to (4), wherein the expandable conductive film is silicide and the heat stable conductive film is polysilicon.

【0007】本発明の半導体装置は、キャパシタの構造
に特徴があり、例えば、キャパシタを構成する一方の電
極を熱処理によってグレイン成長する膨張性導電膜と熱
に対して安定な熱安定性導電膜とを交互に積層した構造
とし、これをパターニングした後、熱処理して膨張性導
電膜をグレイン成長させることによって製造することが
できる。膨張性導電膜がグレイン成長し、これにより該
膨張導電膜の周縁は熱安定性導電膜の周縁より突出した
構造となり、キャパシタを構成する一方の電極の側面
は、凹凸が形成された構造となる。
The semiconductor device of the present invention is characterized by the structure of the capacitor. For example, one of the electrodes forming the capacitor is an expansive conductive film that is grain-grown by heat treatment and a heat-stable conductive film that is stable against heat. Can be manufactured by alternately stacking the layers, patterning the layers, and then heat-treating the grains to grow the expansive conductive film. The expansive conductive film is grain-grown, whereby the peripheral edge of the expansive conductive film has a structure protruding from the peripheral edge of the heat-stable conductive film, and the side surface of one of the electrodes forming the capacitor has a structure in which irregularities are formed. .

【0008】従って、電極側面が凹凸形状であるので、
キャパシタの表面積が増加し、少ない専有面積でキャパ
シタの容量が増加する。また、工程は容易で確実にかか
る構造を得ることができる。この場合、膨張性導電膜と
してシリサイドが熱処理によるグレイン成長が著しいこ
とから好ましく、また、熱安定性導電膜としては、熱処
理に対して安定で膨張し難いポリシリコンが好適であ
る。
Therefore, since the side surface of the electrode is uneven,
The surface area of the capacitor is increased, and the capacity of the capacitor is increased with a small occupied area. In addition, the process is easy and a reliable structure can be obtained. In this case, silicide is preferable as the expansive conductive film because grain growth due to heat treatment is remarkable, and as the thermally stable conductive film, polysilicon that is stable and hardly expands against the heat treatment is preferable.

【0009】[0009]

【発明の実施の形態】以下、本発明の実施の形態につい
て、図面を参照しながら具体的に説明する。図1は、本
発明の半導体装置におけるキャパシタ素子を示す断面図
である。このキャパシタ1は、基板2と接続され、基板
2から突出した短軸柱状の下部電極3を絶縁膜4を介し
て上部電極5が被覆する構造である。この下部電極3
は、基板側から熱安定性導電膜31と膨張導電膜32と
が順次積層された積層体構造(図では5層)を有し、膨
張導電膜32の周縁32aは熱安定性導電膜31の周縁
31aより突出した構造となっている。このように膨張
導電膜32の周縁が熱安定性導電膜31より突出してい
ることにより、下部電極3及びキャパシタ1の側面には
凹凸が形成されており、単純な柱状のキャパシタに比較
して表面積が増加している。従って、キャパシタの容量
はキャパシタの専有面積に比べて大きくなる。
Embodiments of the present invention will be specifically described below with reference to the drawings. FIG. 1 is a sectional view showing a capacitor element in a semiconductor device of the present invention. The capacitor 1 is connected to the substrate 2 and has a structure in which a short-axis columnar lower electrode 3 protruding from the substrate 2 is covered with an upper electrode 5 via an insulating film 4. This lower electrode 3
Has a laminated structure (five layers in the figure) in which the heat stable conductive film 31 and the expanded conductive film 32 are sequentially stacked from the substrate side, and the peripheral edge 32 a of the expanded conductive film 32 is formed of the heat stable conductive film 31. It has a structure protruding from the peripheral edge 31a. Since the peripheral edge of the expanded conductive film 32 is projected from the heat-stable conductive film 31 in this manner, unevenness is formed on the side surfaces of the lower electrode 3 and the capacitor 1, and the surface area is larger than that of a simple columnar capacitor. Is increasing. Therefore, the capacitance of the capacitor is larger than the area occupied by the capacitor.

【0010】ここで、膨張性導電膜は、熱処理によって
グレイン成長する材料を選択する必要があり、これによ
り本構造を実現することができる。このような材料とし
ては、例えばタングステンシリサイド等のシリサイドを
例示することができる。また、熱安定性導電膜として
は、膨張性導電膜をグレイン成長させる熱処理に対して
安定で、その熱処理では膨張し難い材料で構成され、具
体的にはポリシリコンを例示することができる。
Here, for the expansive conductive film, it is necessary to select a material that causes grain growth by heat treatment, and this structure can be realized. Examples of such a material include silicide such as tungsten silicide. The heat-stable conductive film is made of a material that is stable to the heat treatment for grain-growing the expansive conductive film and hardly expands by the heat treatment, and specifically, polysilicon can be exemplified.

【0011】この下部電極を構成する各膜の厚さ、積層
数は特に制限されないが、例えば厚さは50〜100n
m、積層数は、2〜10層以上とすることができる。次
に、本発明にかかるキャパシタの製造方法について、図
2で説明する。 (A)積層膜形成工程 まず、図示しないが、下部電極とコンタクトをとるため
に、シリコンなどの基板2に例えば20kev、1015
/cm3 の条件でイオン注入する。次に、図2(A)に
示すように、熱安定性導電膜として例えば不純物をドー
ピングしたポリシリコン膜31と膨張性導電膜として例
えばタングステンシリサイド膜32’をCVD法により
例えば膜厚50nmで交互に成膜し、積層膜を形成す
る。 (B)パターニング工程 リソグラフィ法によりレジストパターニングした後、レ
ジストREをマスクとして異方性エッチング、例えばC
2 /O2 をエッチングガスとしたECRエッチング等
でキャパシタ下部電極をパターニングする。 (C)熱処理工程 レジストREを剥離した後、例えば850℃、N2 +O
2 ガス、10minの条件で熱処理を行う。これによ
り、ポリシリコン膜31は熱に対して安定であるので、
膨張しないが、タングステンシリサイド膜32’はその
グレインが成長し、図2(C)に示すように、タングス
テンシリサイド膜32の周縁がポリシリコン膜31の周
縁から突出し、突出部32bが形成される。従って、下
部電極3の側面には凹凸が形成され、表面積が増大す
る。
The thickness and the number of laminated layers of each film constituting the lower electrode are not particularly limited, but the thickness is, for example, 50 to 100 n.
m, and the number of laminated layers can be 2 to 10 or more. Next, a method of manufacturing the capacitor according to the present invention will be described with reference to FIG. (A) Laminated film forming step First, although not shown, for example, 20 keV, 10 15
Ion implantation under the condition of / cm 3 . Next, as shown in FIG. 2A, a polysilicon film 31 doped with impurities, for example, as a heat stable conductive film, and a tungsten silicide film 32 ', for example, as an expansive conductive film, are alternately formed with a film thickness of 50 nm by a CVD method. To form a laminated film. (B) Patterning Step After resist patterning by the lithography method, anisotropic etching, for example, C by using the resist RE as a mask.
The capacitor lower electrode is patterned by ECR etching or the like using l 2 / O 2 as an etching gas. (C) Heat treatment step After removing the resist RE, for example, at 850 ° C., N 2 + O
Heat treatment is performed under the conditions of 2 gas and 10 min. As a result, the polysilicon film 31 is stable against heat,
Although not expanded, the grains of the tungsten silicide film 32 'grow and the peripheral edge of the tungsten silicide film 32 protrudes from the peripheral edge of the polysilicon film 31 to form a protrusion 32b, as shown in FIG. 2C. Therefore, unevenness is formed on the side surface of the lower electrode 3 to increase the surface area.

【0012】なお、熱処理条件は上記条件に限らず、例
えば温度800〜850℃、熱処理時間10〜30分の
条件で行うことができる。 (D)キャパシタ上部電極形成工程 キャパシタ絶縁膜として、例えば減圧CVD装置を用い
て、TEOS(テトラエトキシシラン)により絶縁膜4
を成膜する。次いで、導電性膜、例えば不純物をドーピ
ングしたポリシリコンを成膜し、パターニングを行うこ
とによりキャパシタ上部電極5を形成する。
The heat treatment conditions are not limited to the above-mentioned conditions, but may be, for example, a temperature of 800 to 850 ° C. and a heat treatment time of 10 to 30 minutes. (D) Capacitor upper electrode forming step As the capacitor insulating film, the insulating film 4 is made of TEOS (tetraethoxysilane) by using, for example, a low pressure CVD apparatus.
To form a film. Next, a conductive film, for example, polysilicon doped with impurities is formed and patterned to form the capacitor upper electrode 5.

【0013】以上の工程により、図1に示したようなキ
ャパシタ素子を製造することができる。この工程は、容
易に実施可能である。得られたキャパシタは、少ない専
有面積でキャパシタ表面積を大きくとることが可能であ
り、容量確保が容易である。このようなキャパシタは、
例えばDRAM等のキャパシタを有する半導体装置全て
に適用でき、DRAM以外に例えば容量素子を有するL
CD(液晶装置)、あるいはFRAM(強誘電性薄膜メ
モリ)などにも適用することができる。
Through the above steps, the capacitor element as shown in FIG. 1 can be manufactured. This step can be easily performed. The obtained capacitor can have a large capacitor surface area with a small occupied area, and the capacity can be easily secured. Such a capacitor is
For example, the present invention can be applied to all semiconductor devices having capacitors such as DRAM, and in addition to DRAM, for example, L having a capacitive element.
It can also be applied to a CD (liquid crystal device), an FRAM (ferroelectric thin film memory), or the like.

【0014】[0014]

【発明の効果】本発明の半導体装置は、少ない専有面積
でキャパシタ容量を大きくでき、メモリセル面積の縮小
化の要望に応えるものである。また、本発明の半導体装
置の製造方法によれば、容易なプロセスでキャパシタを
形成することができる。
The semiconductor device of the present invention can increase the capacitance of a capacitor with a small occupied area and meet the demand for reduction of the memory cell area. Further, according to the method of manufacturing a semiconductor device of the present invention, the capacitor can be formed by an easy process.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の半導体装置のキャパシタの構造を示す
断面図である。
FIG. 1 is a sectional view showing a structure of a capacitor of a semiconductor device of the present invention.

【図2】(A)〜(D)は、本発明のキャパシタの製造
工程を示すそれぞれ断面図である。
2A to 2D are cross-sectional views showing a manufacturing process of the capacitor of the present invention.

【図3】(A)〜(C)は、従来のキャパシタの製造工
程を示す工程を示す概略断面図である。
3A to 3C are schematic cross-sectional views showing steps showing a conventional manufacturing process of a capacitor.

【符号の説明】[Explanation of symbols]

1 キャパシタ 2 基板 3 キャパシタ下部電極 31 熱安定性導電膜 32’ グレイン成長前の膨張性導電
膜 32 膨張導電膜 32b 突出部 4 キャパシタ絶縁膜 5 キャパシタ上部電極
1 Capacitor 2 Substrate 3 Capacitor Lower Electrode 31 Thermally Stable Conductive Film 32 'Expandable Conductive Film Before Grain Growth 32 Expandable Conductive Film 32b Projection 4 Capacitor Insulating Film 5 Capacitor Upper Electrode

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】キャパシタが多数形成された半導体装置に
おいて、該キャパシタを構成する一方の電極が、熱処理
によってグレイン成長した膨張導電膜と熱処理に対して
安定な熱安定性導電膜とが交互に積層された積層体であ
ると共に、該膨張導電膜の周縁部がその上下に積層され
ている熱安定性導電膜の周縁部から突出していることを
特徴とする半導体装置。
1. In a semiconductor device having a large number of capacitors formed therein, one of the electrodes constituting the capacitor is formed by alternately laminating expanded conductive films grain-grown by heat treatment and thermally stable conductive films stable against heat treatment. And a peripheral portion of the expanded conductive film projecting from the peripheral portions of the heat-stable conductive films stacked above and below the expanded conductive film.
【請求項2】前記膨張導電膜がシリサイドで構成されて
いる請求項1記載の半導体装置。
2. The semiconductor device according to claim 1, wherein the expanded conductive film is made of silicide.
【請求項3】前記熱安定性導電膜がポリシリコンで構成
されている請求項1又は2記載の半導体装置。
3. The semiconductor device according to claim 1, wherein the heat stable conductive film is made of polysilicon.
【請求項4】半導体装置のキャパシタを構成する一方の
電極を形成する半導体装置の製造方法において、 熱処理によってグレイン成長する膨張性導電膜と熱処理
に対して安定な熱安定性導電膜とを交互に成膜する積層
膜形成工程と、 積層膜形成工程によって積層された積層体をパターニン
グするパターニング工程と、 パターニングされた積層体を熱処理して膨張性導電膜を
グレイン成長させる熱処理工程とを有することを特徴と
する半導体装置の製造方法。
4. A method of manufacturing a semiconductor device, wherein one electrode constituting a capacitor of a semiconductor device is formed, wherein an expansive conductive film that is grain-grown by heat treatment and a heat stable conductive film that is stable against heat treatment are alternately formed. A laminated film forming step of forming a film; a patterning step of patterning the laminated body laminated by the laminated film forming step; and a heat treatment step of heat-treating the patterned laminated body to grain-expand the expansive conductive film. A method for manufacturing a characteristic semiconductor device.
【請求項5】前記膨張性導電膜がシリサイドであり、前
記熱安定性導電膜がポリシリコンである請求項4記載の
半導体装置の製造方法。
5. The method of manufacturing a semiconductor device according to claim 4, wherein the expansive conductive film is silicide, and the thermally stable conductive film is polysilicon.
JP7176427A 1995-07-12 1995-07-12 Semiconductor device and its manufacture Pending JPH0927597A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6611680B2 (en) 1997-02-05 2003-08-26 Telefonaktiebolaget Lm Ericsson (Publ) Radio architecture
JP2017108131A (en) * 2015-12-02 2017-06-15 株式会社半導体エネルギー研究所 Semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6611680B2 (en) 1997-02-05 2003-08-26 Telefonaktiebolaget Lm Ericsson (Publ) Radio architecture
JP2017108131A (en) * 2015-12-02 2017-06-15 株式会社半導体エネルギー研究所 Semiconductor device
US11056510B2 (en) 2015-12-02 2021-07-06 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US11710744B2 (en) 2015-12-02 2023-07-25 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device

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