JPH09275216A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a CMOS circuit having high characteristics. SOLUTION: The circuit, is composed of n- and p-channel type thin film transistors on the same substrate. The n-channel type thin film transistor has an LDD(light doped drain) region. The damage of an active layer due to the implanting of an impurity ion is set to be on the same level as that of the n- and p-channel type thin film transistors. Thus, the difference of the characteristics between these transistors is corrected to obtain a CMOS circuit having high characteristics.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD [0001] The invention disclosed in the present specification is:
The present invention relates to a configuration in which P-channel type and N-channel type thin film transistors are arranged on the same substrate. Further, the present invention relates to a manufacturing method thereof. Specifically, the present invention relates to a CMOS type circuit configuration formed by thin film transistors on a glass substrate. In addition, it relates to a manufacturing process thereof.

[0002]

2. Description of the Related Art There is known a technique of forming a silicon film on a glass substrate and manufacturing a thin film transistor using the silicon film. This technology is a technology that has been developed to manufacture an active matrix liquid crystal display device.

A liquid crystal display device has a structure in which liquid crystal is sandwiched and held between a pair of glass substrates, and an electric field is applied to the liquid crystal in each of a large number of pixels arranged in a matrix to change its optical characteristics. By doing so, the display is performed.

In the active matrix type liquid crystal display device, a thin film transistor is arranged in each of the pixels arranged in a matrix, and the electric charge which flows in and out of each pixel electrode is controlled by the thin film transistor.

At present, a circuit (called a peripheral driving circuit) for driving several hundreds × several hundreds or more thin film transistors arranged in an active matrix region is called a driver IC externally attached to a glass substrate by a TAB wiring or the like. It is composed of an IC circuit.

However, the external attachment of the driver IC to the glass substrate has a problem that the manufacturing process becomes complicated. For example, there is a problem that the alignment and operation inspection become complicated. In addition, unevenness is created by the amount of the driver IC. This is a factor that hinders its versatility in liquid crystal display devices incorporated in various electronic devices.

As a technique for solving such a problem, there is a technique in which the peripheral drive circuit is integrated on the glass substrate with thin film transistors.

With such a structure, the whole structure can be integrated, and the advantages such as simplification of the manufacturing process, improvement of reliability, and expansion of versatility can be obtained.

In the active matrix type liquid crystal display device in which such a peripheral drive circuit is also integrated, a CMOS circuit is required as a circuit constituting the peripheral drive circuit. The CMOS circuit has an N-channel type transistor and a P-type.
It is a circuit configured in a complementary manner with a channel type transistor, and is one of the basic configurations of electronic circuits.

As a method of obtaining a CMOS structure with a thin film transistor on a glass substrate, the following structure is known.

In the method shown in FIG. 4, first, as shown in FIG. 4A, a silicon oxide film 4 serving as a base film is formed on a glass substrate 401.
02, a semiconductor film 403 and a semiconductor layer 404 made of a silicon film (a crystalline silicon film or an amorphous silicon film) are further formed thereon, and a silicon oxide film 405 which covers them and functions as a gate insulating film. To form a film.

Here, 403 is an island-shaped region which becomes a semiconductor layer of an N-channel type thin film transistor, and 404 is P.
This is an island-shaped region that serves as a semiconductor layer of a channel thin film transistor.

Next, gate electrodes 406 and 407 made of a conductive material such as a silicide material are formed to obtain the state shown in FIG. 4 (B).

In this state, P (phosphorus) ions are implanted over the entire surface. This resulted in 408 and 410 areas, and 41 more
Regions 1 and 413 are N-type. (FIG. 4 (C))

The implantation of P ions is 1 × 10 ¹⁵ / cm.
The dose amount is ^{2 to} 2 × 10 ¹⁵ / cm ² , and the surface concentration is 1 × 10 ²⁰ / cm ² or more.

Next, the resist mask 414 is selectively arranged only in a region to be an N-channel type thin film transistor,
B (boron) ion implantation is performed. (FIG. 4 (D))

At this time, the above-mentioned P ion dose amount of 3 to
B ions are implanted with a dose amount of about 5 times.

Then, the conductivity type of the regions 411 and 413 (see FIG. 4C) which became N type is inverted to P type. Thus, the source region 41 of the P-channel type thin film transistor
5, the drain region 416 and the channel forming region 412 are formed in a self-aligned manner.

Heavy doping as described above is required because the regions 415, 412 and 416 must be PIP junctions.

In the structure shown in FIG.
Is a source region of an N-channel thin film transistor, 40
Reference numeral 9 is a channel forming region of the N-channel type thin film transistor, and 410 is a drain region of the N-channel type thin film transistor.

Reference numeral 416 is a drain region of a P-channel thin film transistor, 412 is a channel formation region of a P-channel thin film transistor, and 415 is a drain region of a P-channel thin film transistor.

The structure shown in FIG. 4 is significant in that the manufacturing process can be simplified because it is not necessary to form a resist mask in the process shown in FIG. 4C.
However, there are problems as described below.

First, since impurity ions are implanted into the resist mask 414 with an extremely high dose amount, alteration of the resist material becomes apparent, resulting in a high probability that process defects will occur. In particular,
The resist material cannot be removed after doping,
The problem of remaining remains.

Second, the drain region 415 adjacent to the channel forming region 412 of the thin film transistor (P-channel type thin film transistor) on the right side of FIG. 4 is required to have an extremely high concentration (P-channel type in order to invert the conductivity type). Channel region 412, since the impurity region has a dose of more than a certain amount)
The existence of the OFF current near the junction between the drain region 415 and the drain region 415 cannot be ignored.

Thirdly, due to the wraparound of ions due to the implantation of high concentration B ions, B is formed in the channel forming region 412.
Ions are inevitably added, and there is a problem in that the required characteristics cannot be obtained or often cannot be obtained.

Fourthly, the implantation of the impurity ions at the high dose required in the step (D) puts a heavy burden on the ion implantation apparatus and the plasma doping apparatus, and it is troublesome to pollute the inside of the apparatus and to maintain the apparatus. It causes various problems such as this.

Fifth, implanting impurity ions at a high dose also causes a problem of increasing the processing time.

Sixth, there is an inconvenience when performing annealing by laser light. Generally, after the state shown in FIG.
The resist mask 414 is removed, and an annealing process by laser light irradiation is required for activation of the implanted impurities and annealing of the region where the impurity ions are implanted. (This method is useful when using a glass substrate having low heat resistance.)

At this time, the impurity ions are implanted into the regions 415 and 416 with a large dose amount as compared with the regions 408 and 410, so that the crystallinity is significantly damaged.

Therefore, the wavelength dependence of the light absorption rate is 408.
The region of the group of 410 and the region of the group of 415 and 416 are significantly different. In such a state, the annealing effect due to the irradiation of the laser light is greatly different between the above two groups.

This is not preferable because it causes a large difference in electrical characteristics between the left N-channel thin film transistor and the right P-channel thin film transistor.

[0032]

SUMMARY OF THE INVENTION The invention disclosed in this specification addresses the problem of impurity ion implantation at a high dose, which is a problem when simultaneously forming an N-channel type thin film transistor and a P-channel type thin film transistor. The task is to avoid it.

The thin film transistor is used for the CMO.
It is an object to correct a difference in characteristics between an N-channel thin film transistor and a P-channel thin film transistor when an S circuit is formed and obtain a CMOS circuit having high characteristics.

[0034]

One of the inventions disclosed in the present specification has a structure in which an N-channel type thin film transistor and a P-channel type thin film transistor are integrated on the same substrate. Type thin film transistor is selectively formed with an LDD region, and a source region and a drain region of the P channel type thin film transistor are added with only an impurity imparting P type, and a source of the P channel type thin film transistor is added. And a region to which an impurity imparting N-type and P-type is added is formed adjacent to the drain region.

A specific example of the above structure is shown in FIG. The configuration shown in FIG. 3B is an example of a circuit (CMOS circuit) configured in a complementary manner with a left N-channel thin film transistor (NTFT) and a right P-channel thin film transistor (PTFT).

In this structure, the LDD region 124, which is a low-concentration impurity region, is selectively arranged only in the left N-channel type thin film transistor indicated by NTFT.

The LDD region is an abbreviation for lightly doped drain region. The LDD region is arranged between the channel forming region and the drain region. The LDD region has an effect of reducing the OFF current value and suppressing deterioration by relaxing the electric field intensity between the channel formation region and the drain region. It also has a function of substantially suppressing mobility in the thin film transistor by increasing the resistance between the source / drain.

When silicon is used as the semiconductor,
As an impurity imparting N-type, P (phosphorus) can be typically mentioned. Similarly, when silicon is used as a semiconductor, B is typically used as an impurity imparting P-type conductivity.
(Boron) can be mentioned.

On the other hand, in the structure shown in FIG.
The P-channel type thin film transistor does not have a buffer region like the LDD region. However, an offset gate region is arranged in each of the N-channel type and / or P-channel type thin film transistors by utilizing the insulating film formed on the side surface of the gate electrode. The offset gate region has the same function as the LDD region.

For example, the anodic oxide film 11 shown in FIG.
4 and 115 function as a mask at the time of ion implantation, and form an offset gate region corresponding to the film thickness (film thickness on the side surface of the gate electrode). However, if the film thickness is thin, it does not function as an effective offset gate region.

The characteristics of the semiconductor device to which the present invention is applied are as follows. The regions 128 and 130 (see FIG. 3B) which are behind the anodic oxide films 112 and 113 and which are not ion-implanted in the process of FIG.
Since B ions are implanted in the step (C), P
It contains only the impurities that give the mold. We have
Each of these regions 128 and 130 is defined as a source / drain region in a P-channel type thin film transistor.

As shown in FIG. 3B, the regions 127 and 131 adjacent to the regions 128 and 130 are shown in FIG.
Since the P ions are implanted in the step (E), both the N-type and P-type imparting impurities are contained. The present inventors define these regions 127 and 131 as regions that substantially only function as the extraction electrodes from the source region 128 and the drain region 130, and clearly distinguish them from the source / drain regions.

Therefore, in the semiconductor device to which the present invention is applied, the source region and the drain region of the P-channel type thin film transistor are sandwiched between the region to which the impurities imparting N-type and P-type are added and the channel forming region. It is characterized by

It is to be noted that adding an impurity imparting one conductivity type to a channel formation region of an N-channel type and / or P-channel type thin film transistor is effective in controlling a threshold value which is one of electric characteristics. Is. For example, N
In the case of a channel type thin film transistor, boron which imparts P type is added to the channel forming region, and in the case of a P channel type thin film transistor, phosphorus which imparts N type is added to the channel forming region.

Another structure of the present invention has a structure in which an N-channel type thin film transistor and a P-channel type thin film transistor are integrated on the same substrate, and the N-channel type thin film transistor includes a P-channel type thin film transistor. Also, an offset gate region having a long offset width is selectively formed, and only the impurity imparting P-type is added to the source region and the drain region of the P-channel type thin film transistor. N adjacent to source and drain regions
It is characterized in that a region to which an impurity imparting a p-type and a p-type is added is formed.

According to another aspect of the present invention, there is provided an active matrix region in which thin film transistors are arranged in a matrix on the same substrate, and a peripheral driving circuit for driving the thin film transistors arranged in the region. An N-channel type thin film transistor is arranged in the area, and a circuit in which an N-channel type thin film transistor and a P-channel type thin film transistor are configured in a complementary type is arranged in the peripheral driving circuit. LDD regions and / or offset gate regions are selectively formed in the arranged N-channel type thin film transistors, and P-type is given to the source region and drain region of the P-channel type thin film transistors arranged in the peripheral driving circuit. Only the impurities to be added are added. Wherein the region to which an impurity imparting N-type and P-type adjacent to the in-region has been added are formed.

According to another aspect of the present invention, there is provided an active matrix region in which thin film transistors are arranged in a matrix on the same substrate, and a peripheral drive circuit for driving the thin film transistors arranged in the region. A P-channel type thin film transistor is arranged in the peripheral driving circuit, and a circuit in which an N-channel type thin film transistor and a P-channel type thin film transistor are configured in a complementary type is arranged in the peripheral driving circuit and arranged in the peripheral driving circuit. LDD regions and / or offset gate regions are selectively formed in the N-channel type thin film transistors, and P is formed in the source region and the drain region of the P-channel type thin film transistors arranged in the active matrix region and the peripheral driving circuit. Only the impurities that give the mold are added Ri, wherein the area where impurity imparting N-type and P-type adjacent to the source and drain regions are added are formed.

According to another aspect of the invention, in the step of manufacturing the N-channel type thin film transistor and the P-channel type thin film transistor integrated on the same substrate, the side surface of the gate electrode made of an anodizable material is porous. 1. A first step of selectively forming the anodic oxide film, a second step of adding an impurity imparting N-type using the anodic oxide film as a mask, and a third step of removing the anodic oxide film. , The P
A fourth step of selectively masking a region to be a channel type thin film transistor with a photoresist, and a region where the anodic oxide film was formed by adding an impurity imparting N type by using the gate electrode and the photoresist as a mask A fifth step of forming an LDD region thereunder, a sixth step of removing the photoresist formed in the fourth step, and a region for making the N-channel type thin film transistor selectively masked with the photoresist. And an eighth step of adding an impurity imparting P-type by using the gate electrode and the photoresist as a mask,
And a region to which only an impurity imparting P-type is added is formed under the region where the anodic oxide film was present by the eighth step, and at the same time, N-type and P-type are formed adjacent to the region. It is characterized in that a region containing an impurity to be added is formed.

In the second step, the fifth step and the eighth step, the addition of the impurity imparting N-type or P-type is performed by implanting accelerated impurity ions through the gate insulating film. The damage to the semiconductor layer can be reduced.

According to another aspect of the invention, in the step of manufacturing the N-channel thin film transistor and the P-channel thin film transistor integrated on the same substrate, a porous electrode is formed on the side surface of the gate electrode made of an anodizable material. 1. A first step of selectively forming the anodic oxide film, a second step of adding an impurity imparting N-type using the anodic oxide film as a mask, and a third step of removing the anodic oxide film. , Said N
There is a fourth step of selectively masking a region to be a channel type thin film transistor with a photoresist, and a fifth step of adding an impurity imparting P-type with the gate electrode and the photoresist as a mask. However, an offset gate region, which is determined by the thickness of the porous anodic oxide film, is selectively formed in the N-channel thin film transistor by the second step.

The above-mentioned configuration is characterized by 505 in FIG.
With the thickness of the porous anodic oxide film shown by
The offset gate regions indicated by 5 and 517 are formed.

When the dense anodic oxide film 500 has a large thickness, the offset gate region 51 is equivalent to the thickness.
5, 517 will be contributed.

According to another aspect of the invention, when the crystalline silicon film forming the semiconductor layers of the N-channel type thin film transistor and the P-channel type thin film transistor is formed, a metal element that promotes crystallization is added to the amorphous silicon film. First to hold
And a second step of transforming the amorphous silicon film into a crystalline silicon film by heat treatment, and heat-treating the crystalline silicon film in an atmosphere containing a halogen element to obtain the surface of the crystalline silicon film. A third step of forming a thermal oxide film on
A fourth step of removing the thermal oxide film, wherein the metal element remaining in the crystalline silicon film is gettered into the thermal oxide film by the third step. .

At this time, the second step is performed in the temperature range of 500 to 700 ° C., and the third step is 700 to 1200 ° C.
It is characterized in that it is performed in the temperature range of.

The present invention having the above structure will be described in more detail with reference to Examples 1 to 10 described below.

[0056]

【Example】

[Embodiment 1] This embodiment is an example of forming a CMOS structure with a thin film transistor on a glass substrate. 1 to 3 show the manufacturing process of this embodiment.

First, as shown in FIG. 1A, a silicon oxide film 102 is formed as a base film on a glass substrate 101. As a method for forming the silicon oxide film 102, a sputtering method or a plasma CVD method may be used. The thickness is 3000
It should be about Å.

As the glass substrate 101, Corning 7
A 059 glass substrate or a Corning 1737 glass substrate can be used. Further, a quartz substrate can be used as a light-transmitting substrate which is expensive but has high heat resistance.

After forming the silicon oxide film 102, a silicon film to be a semiconductor layer of a thin film transistor is formed later. Here, first, an amorphous silicon film (not shown) is formed to a thickness of 500Å as a starting film. As a method for forming this amorphous silicon film, a plasma CVD method or a low pressure thermal CVD method may be used.

After the amorphous silicon film (not shown) is formed, the amorphous silicon film (not shown) is crystallized by a method of laser light irradiation or heat treatment, or a combination of laser light irradiation and heat treatment. Thus, a crystalline silicon film is obtained.

Further, at the time of this crystallization, a means for holding a metal element that promotes crystallization on the amorphous silicon film may be adopted. The details of this crystallization means are disclosed by the present inventors in Japanese Patent Laid-Open Nos. 6-232059 and 6-24.
It is disclosed in Japanese Patent No. 4103.

The crystalline silicon film (not shown) thus obtained is patterned to obtain an N-channel type thin film transistor semiconductor layer 104 and a P-channel type thin film transistor semiconductor layer 105. (See FIG. 1A)

After forming the semiconductor layers 104 and 105, a silicon oxide film 103 functioning as a gate insulating film is formed by plasma CVD. The thickness is 500 to 2000Å, typically 1000 to 1500Å. Further, as the gate insulating film, another insulating film such as a silicon oxynitride film or a silicon nitride film may be used.

Thus, the state shown in FIG. 1A is obtained. Here, an example in which a pair of N-channel thin film transistors and P-channel thin film transistors is formed is shown for simplicity of description. Generally, an N-channel type thin film transistor and a P-channel type thin film transistor are formed in units of several hundreds or more on the same glass substrate 101.

When the state shown in FIG.
As shown in (B), an aluminum film 106 which will later form the gate electrodes 11 and 12 is formed.

The aluminum film 106 contains scandium of 0.2 w in order to suppress the generation of hillocks and whiskers.
t weight% is included. The aluminum film 106 is formed by a sputtering method or an electron beam evaporation method.

Hillocks and whiskers are spine-like or needle-like protrusions caused by abnormal growth of aluminum. The presence of hillocks or whiskers causes short circuits or crosstalk between adjacent wirings or between wirings separated by an upper limit.

As the material other than aluminum, another anodizable metal such as tantalum can be used.

After forming the aluminum film 106, anodization is performed in the electrolytic solution using the aluminum film 106 as an anode to form a thin and dense anodic oxide film 107 on the surface.

Here, an ethylene glycol solution containing 3% tartaric acid neutralized with ammonia is used as an electrolytic solution. By using this anodizing method, an anodized film having a dense film quality can be obtained. The film thickness can be controlled by the applied voltage.

Here, the thickness of the anodic oxide film 107 is set to 100.
Å The anodic oxide film 107 has a role of improving adhesion with a resist mask formed later. Thus, the state shown in FIG. 1B is obtained.

Next, resist masks 108 and 109 are formed. Then, using the resist masks 108 and 109, the aluminum film 106 and the anodic oxide film 10 on the surface thereof are formed.
7 is patterned to form patterns 110 and 111. Thus, the state shown in FIG. 1C is obtained.

Next, using 3% oxalic acid aqueous solution as an electrolytic solution, anodic oxidation is performed with the patterns 110 and 111 made of the aluminum film remaining in this solution as anodes.

In this anodizing step, patterns 110 and 111 made of an aluminum film on which anodizing remains.
Selectively progresses in the aspect of. This is because the dense anodic oxide film 107 and the resist masks 108 and 109 remain on the upper surfaces of the aluminum films 110 and 111.

By this anodic oxidation, the anodic oxide films 112 and 11 having a porous (porous) film quality.
3 is formed. Porous anodic oxide film 112, 113
The growth distance can be controlled by the anodic oxidation time, and can be grown up to about several μm.

In this embodiment, the anodic oxide films 112, 1
The growth distance of 13, that is, the film thickness is 7,000 Å. The growth distance of the anodic oxide films 112 and 113 later determines the length of the low concentration impurity region. Empirically, the growth distance of the porous anodic oxide films 112 and 113 is 6000Å ~
It is desirable to set 8000Å. Thus, FIG. 1 (D)
The state shown in is obtained.

In this state, the gate electrodes 11 and 12 are defined. After obtaining the state shown in FIG. 1D, the resist masks 108 and 109 are removed.

Next, anodic oxidation is performed again by using an ethylene glycol solution containing 3% tartaric acid neutralized with ammonia as an electrolytic solution. In this step, the electrolytic solution penetrates into the porous anodic oxide films 112 and 113. As a result, dense anodic oxide films 114 and 115 shown in FIG. 1E are formed on the surfaces of the gate electrodes 11 and 12.

The thickness of the dense anodic oxide films 114 and 115 is set to 500Å to 4000Å. The film thickness is controlled by the voltage application time. The remaining portion of the dense anodic oxide film 107 previously formed is formed by the anodic oxide films 114 and 115.
Will be integrated with.

Next, in the state shown in FIG. 1E, the entire surface is doped with P (phosphorus) ions as an impurity imparting N-type.

This doping is 0.2-5 × 10 ¹⁵ / c
The dose is as high as m ² , preferably 1 to 2 × 10 ¹⁵ / cm ² . A plasma doping method or an ion doping method is used as the doping method.

As a result of the step shown in FIG. 1 (E), the regions 116, 117, 118 in which the P ions are implanted at a high concentration,
119 are formed respectively.

Next, the porous anodic oxide films 112 and 113 are removed using aluminum mixed acid. At this time, the anodic oxide film 1
The semiconductor layer regions located directly below the regions 12, 113 are substantially intrinsic because they are not ion-implanted.

Next, the resist mask 12 is formed so as to cover the element forming the P-channel type thin film transistor.
Form 0. Thus, the state is obtained as shown in FIG.

When the state shown in FIG.
As shown in (B), P ions are implanted again. This P
In ion implantation, the dose amount is 0.1 to 5 × 10 ¹⁴ / cm
² , preferably a low value of 0.3 to 1 × 10 ¹⁴ / cm ² .

That is, P performed in the step shown in FIG.
The dose of the ion implantation is set lower than the dose performed in the step shown in FIG.

As a result of this step, the regions 122 and 124 become lightly doped low concentration impurity regions. Also, 1
The regions 21 and 125 are high-concentration impurity regions in which P ions are implanted at a higher concentration.

In this step, the region 121 becomes the source region of the N-channel type thin film transistor. 122 and 124 are low concentration impurity regions, and 125 is a drain region. Further, the region indicated by 123 is a substantially intrinsic channel forming region. The low concentration impurity region indicated by 124 is a region generally called an LDD (lightly doped drain) region.

Although not particularly shown, the anodic oxide film 114
The region where the ion implantation is blocked by the channel forming region 123
And the low-concentration impurity regions 122 and 124.
This region is called an offset gate region and has a size corresponding to the film thickness of the anodic oxide film 114.

No ions are implanted into the offset gate region, which is substantially intrinsic. However, since the gate voltage is not applied (though not completely, it may be considered so), a channel is not formed and an electric field is not generated. It functions as a resistance component that relaxes strength and suppresses deterioration.

However, the distance (offset gate width)
Is short, it does not function as an effective offset gate region.

Next, the resist mask 120 is removed,
As shown in FIG. 2C, a resist mask 126 which covers the N-channel thin film transistor is formed.

Next, in the state shown in FIG.
Implant (boron) ions. Here, the dose amount of B ions is 0.2 to 10 × 10 ¹⁵ / cm ² , preferably 1
It is about 2 × 10 ¹⁵ / cm ² . This dose is shown in Figure 1.
It can be set to the same level as the dose amount in the step shown in (E).

127 and 131 formed by this process
The area indicated by is a pad for making contact with the extraction electrode (hereinafter referred to as a contact pad).
Becomes That is, unlike the N-channel thin film transistor on the left side, the regions 127 and 131 are clearly distinguished from the source / drain regions.

Regarding the P-channel type thin film transistor, the source region is defined by the region indicated by 128, and the drain region is defined by the region indicated by 130.

These regions 128 and 130 are formed by implanting only B ions into the substantially intrinsic region. Therefore, since other ions do not coexist, the impurity concentration can be easily controlled, and a PI junction with good compatibility can be realized. Further, the disorder of crystallinity due to ion implantation can be relatively small.

Although the offset gate region is formed in a self-aligned manner by using the anodic oxide film 115, empirically, the existence of the offset gate region is especially important because the P-channel type thin film transistor hardly deteriorates. It does not become a thing.

Thus, the source region 128 and the drain region 130 of the P-channel type thin film transistor are formed in a self-aligned manner. Further, the region 129 is not intrinsically doped with impurities and is substantially intrinsic and serves as a channel formation region.
Further, as described above, 127 and 131 serve as contact pads for taking out current from the source region 128 and the drain region 130, respectively.

Although the structure in which no impurity is added to the channel forming region is used here, the structure may be such that an impurity imparting a conductivity type is intentionally added to the channel forming region in order to control the threshold value.

Next, after the step shown in FIG. 2C is completed, the resist mask 126 is removed to obtain the state shown in FIG. Laser irradiation is performed on the entire surface in order to activate the impurities implanted in this state and anneal the regions where the impurity ions are implanted.

At this time, the region shown by the pair 121 and 125 which is the source / drain region of the N-channel type thin film transistor and the region shown by the set 128 and 130 which is the source / drain region of the P-channel type thin film transistor. Irradiation with laser light can be performed in a state in which the difference in crystallinity between and is not so large.

Thus, the difference in crystallinity does not become so large because the source / drain regions 128 of the P-channel type thin film transistor in the step shown in FIG.
This is because 130 is not greatly damaged during the ion implantation.

Therefore, in the state shown in FIG.
Even if the source / drain regions of thin film transistors of different conductivity types of N-channel type and P-channel type are simultaneously annealed by the irradiation of the laser light, the annealing effect is significantly different between the N-channel type thin film transistor and the P-channel type thin film transistor. There is no. Therefore, in this embodiment, the difference in the annealing effect can be corrected, and thus the difference in the characteristics of the obtained N and P channel type thin film transistors can be corrected.

After obtaining the state shown in FIG.
As shown in (A), an interlayer insulating film 132 is formed to a thickness of 4000Å. The interlayer insulating film 132 may be any of a silicon oxide film, a silicon oxynitride film, and a silicon nitride film, and may have a multilayer structure. The method for forming these silicified insulating films is plasma C
A VD method or a thermal CVD method may be used.

Next, contact holes are formed to form a source electrode 133 and a drain electrode 134 of an N-channel type thin film transistor (NTFT). At the same time, the source electrode 1 of the P-channel type thin film transistor (PTFT)
35 and the drain electrode 136 are formed. FIG.
The state shown in (B) is obtained.

Here, patterning is performed so that the drain electrode 134 of the N-channel type thin film transistor and the drain electrode 136 of the P-channel type thin film transistor are connected to each other, and the gate electrodes of two TFTs are connected to each other to realize a CMOS structure. To be done.

In the structure having the CMOS structure shown in FIG. 3B, the low-concentration impurity regions 122 and 124 are arranged toward the N-channel thin film transistor.

The low-concentration impurity regions 122 and 124 reduce: OFF current. -Prevents TFT deterioration due to hot carriers. -Increases the resistance between the source / drain and reduces the mobility of the NTFT. It has such an action.

Generally, when a CMOS structure as shown in FIG. 3B is used, a difference in characteristics between the N-channel type thin film transistor and the P-channel type thin film transistor becomes a problem.

For example, when the crystalline silicon film as in this embodiment is used, the mobility of the N-channel type thin film transistor is about 100 to 150 Vs / cm ² .
The mobility of a P-channel thin film transistor is 30 to 80.
Only Vs / cm ² can be obtained.

Further, the N-channel type thin film transistor has a problem of deterioration due to hot carriers. This problem does not occur particularly in the P-channel type thin film transistor.

In general, a CMOS circuit does not require a low OFF current characteristic.

In such a situation, the following significance can be obtained by arranging the low-concentration impurity regions 122 and 124 on the N-type thin film transistor side.

That is, in the CMOS structure, by lowering the mobility of the N-type thin film transistor and preventing its deterioration, the overall characteristic balance with the P-channel type thin film transistor is taken, and the characteristic as a CMOS circuit is obtained. Can be improved.

Further, FIG. 1E, FIG. 1B, and FIG. 1C.
In the step of implanting the impurity ions shown in FIG.
4, 105 are silicon oxide films 103 forming a gate insulating film
Being covered with is important.

By implanting the impurity ions in such a state, it is possible to suppress the surface roughness and contamination of the semiconductor layer. This greatly contributes to improving the yield and the reliability of the obtained device.

Furthermore, according to the present embodiment, impurity ions are not implanted with an extremely high dose amount throughout the entire process, so that the quality of the photoresist used as a mask is deteriorated,
It is possible to reduce the probability of occurrence of a defective process due to it.

[Embodiment 2] This embodiment shows a CMOS structure composed of thin film transistors, in which only an offset gate region is arranged in an N-channel thin film transistor. Unlike the first embodiment, the offset gate region in this embodiment is formed by using a porous anodic oxide film (in the case of the first embodiment, the anodic oxide film having a dense film quality that finally remains). Is used to form the offset gate region).

The offset gate region has the same action as the low concentration impurity region represented by the LDD region.
That is, the OFF current value is reduced. -The mobility between the thin film transistors is reduced because the resistance between the source and the drain is increased. -If it is an N-channel type, deterioration due to hot carriers is suppressed. This has the operational effect of:

FIG. 5 shows a manufacturing process of the CMOS structure shown in this embodiment. First, as described in the first embodiment, FIG.
~ By the process similar to that shown in FIG.
The state shown in FIG.

In FIG. 5A, reference numeral 500 is a dense anodic oxide film formed around the gate electrode. The thickness of the anodic oxide film 500 can be controlled within the range of 500 to 4000 Å. In this embodiment, the thickness of the anodic oxide film 500 is set to 60.
0 °.

The film thickness of the porous anodic oxide film indicated by 505 and 506 in FIG. 5A is 2000 to 4000.
Å. The thickness of the porous anodic oxide films 505 and 506 roughly determines the size of the offset gate region to be formed later.

To be precise, as shown in Example 1, the thickness of the dense anodic oxide film 500 inside the porous anodic oxide films 505 and 506 also affects the size of the offset gate region. However, its thickness is about 600Å, so its existence is ignored here.

In this state, P ions are added in an amount of 0.2 to 5 × 10 ¹⁵ c
^{Implant at} a dose of m ^-2 , preferably 1-2 x 10 ¹⁵ cm ^-2 . As a method for implanting impurity ions, a plasma doping method or an ion doping method is used.

This dose amount is heavy doping,
P ions are implanted at a high concentration in the regions 501 to 504. That is, the regions 501 to 504 are high-concentration impurity regions.

Next, porous anodic oxide films 505 and 506 are used.
Is removed. Thus, the state shown in FIG. 5B is obtained. In this state, regions 507 and 508 are regions where P ions are not implanted.

Then, as shown in FIG. 5C, a resist mask 509 is arranged in a portion to be an N-channel thin film transistor region. Then, B ions are implanted.

Implantation of B ion is 0.2 to 10 ¹⁵ cm ^-2 ,
The dose is preferably 1 to 10 ¹⁵ cm ^-2 . The B ion implantation method is a plasma doping method or an ion doping method.

In this step 510, 511, 51
Regions 3, 514 are P-type impurity regions, and 512 are substantially intrinsic channel forming regions. As shown in the first embodiment, the source region and the drain region are 51
Regions denoted by 1, 513, and regions denoted by 510, 514 function as contact pads connected to the source / drain regions 511, 513.

The source / drain regions 511 and 513 are
Since the regions were substantially intrinsic before the B ion implantation, these regions 511 and 513 easily become P type by the B ion implantation in the step of FIG. 5C. Therefore, the dose of B ions in this step can be set to the minimum required dose amount.

As described above, the drain region 511 and the channel forming region 51 of the P-channel type thin film transistor are formed.
2, source region 513, contact pads 510, 51
4 can be formed in a self-aligned manner.

Next, the resist mask 509 is removed, and the structure shown in FIG.
The state shown in (D) is obtained. In the state shown in FIG. 5D, 501 and 502 are the source and drain regions of the N-channel thin film transistor. Further, 516 is a channel formation region.

The offset gate regions 515 and 517 are not applied with the electric field from the gate electrode and do not function as the source / drain regions. This area is
It has a function of relaxing the electric field strength between the source / drain region (particularly the drain region) and the channel formation region.

These offset gate regions 515, 5
Reference numeral 17 is formed in a self-aligned manner by using the porous anodic oxide film 505.

On the other hand, in the P-channel type thin film transistor, the offset gate region does not exist. (To be precise, the offset gate region is formed by the film thickness of the finally remaining anodic oxide film having a dense film quality, but since its size is small, its existence is ignored here.)

As described in the first embodiment, such a structure substantially lowers the mobility of the N-channel type thin film transistor and further suppresses the deterioration of its characteristics. The balance between the p-type thin film transistor and the p-channel thin film transistor can be improved.

[Embodiment 3] In Embodiment 1, FIG.
The P ion implantation step shown in FIG. 2B and the B ion shown in FIG.
Even if the order of the ion implantation steps is changed, the same effect as that of the first embodiment can be obtained. This is because the concentration control of P ion and B
This means that the ion concentration can be controlled independently.

[Embodiment 4] In this embodiment, in the manufacturing process of Embodiment 1, the P ion implantation step (heavy dope) shown in FIG. 1E and the P ion implantation step (light) shown in FIG. An example in which the order of the steps of (dope) is changed is shown.

Since the description of the present embodiment is made by directly referring to FIGS. 1 to 3, the reference numerals used in the description are the same as those used in the first embodiment.

When the state of FIG. 1E is obtained according to the first embodiment, P ion implantation is performed in this state. The conditions of ion implantation at this time are the same as those of the light doping shown in FIG. Therefore, the regions 116 to 119 into which the impurities are formed at this time have a lower concentration than the example shown in the first embodiment.

Next, as shown in FIG. 2A, a resist mask 120 covering the P-channel type thin film transistor is formed,
P ion implantation is performed as shown in FIG. At this time, the ion implantation conditions are the same as those of the heavy dope shown in FIG. Therefore, the regions 122 and 124 formed at this time have a higher density than the example shown in the first embodiment.

After that, an N-channel type thin film transistor and a P-channel type thin film transistor are formed according to the first embodiment.

According to the present embodiment, since light doping is carried out and then heavy doping is carried out, damages due to ion implantation in the semiconductor layers 104 and 105 of the N-channel type thin film transistor and the P-channel type thin film transistor are the same. .

Therefore, when laser light irradiation is performed in the state shown in FIG. 2D to anneal the source / drain regions of the two thin film transistors, the difference in the annealing effect can be corrected. That is, the obtained N
The difference in characteristics between the P-channel thin film transistor and the P-channel thin film transistor can be corrected.

In the N-channel type thin film transistor, the impurity concentration of the LDD region 124 is different between the first embodiment and this embodiment. In this embodiment, since the impurities are injected at a higher concentration than in the first embodiment, the resistance becomes low, and the configuration is effective when the ON current characteristics are emphasized.

[Embodiment 5] In this embodiment, in order to control the threshold value of the N-channel type thin film transistor, the conductivity type of the channel of the N-channel type thin film transistor is set to a weak P.
Concerning the type of composition.

The manufacturing process of this embodiment is similar to that of the first embodiment (see FIGS.
It is basically the same as that shown in FIG. This example is different from example 1 in that an amorphous silicon film, which is a starting film for forming the semiconductor layers 104 and 105, is formed.
A small amount of diborane (B ₂ H ₆ ) is added to the raw material gas.

The addition of diborane may be determined in consideration of the threshold characteristics of the thin film transistor to be obtained. Specifically, the addition amount may be adjusted so that the concentration of the B element finally remaining in the channel formation region is about 1 × 10 ¹⁷ / cm ^{2 to} 5 × 10 ¹⁷ / cm ² .

By the action of the B ion added in a small amount,
It is possible to control the threshold artificially.

[Embodiment 6] In Embodiment 5, in order to control the threshold value of the N-channel type thin film transistor, the channel forming region of the N-channel type thin film transistor is weakly doped.
Here is an example of type. However, in the process shown in Example 3,
The threshold value of a P-channel type thin film transistor cannot be freely controlled.

Therefore, in this embodiment, for example, FIG.
In the state shown in FIG. 1A or in the state before the gate insulating film 103 is formed before the state shown in FIG. 1A, the semiconductor layer 104 and / or the semiconductor layer 105 is selectively doped with impurity ions. Make an injection.

For example, in the state before FIG. 1A, that is, in the state before the gate insulating film 103 is formed, the semiconductor layer 105 is masked, and the B ion is given to the semiconductor layer 104 with a predetermined dose amount. Injection. In this step, the semiconductor layer 104 is made a weak P type that requires it.

Next, the semiconductor layer 104 is masked, and P ions are implanted into the semiconductor layer 105 with a predetermined dose amount. In this process, a weak N that requires the semiconductor layer 105 is used.
Type.

By doing so, a structure in which the threshold values of the N-channel type thin film transistor and the P-channel type thin film transistor can be independently controlled is realized.

After implanting impurity ions into the semiconductor layer as shown in this embodiment, annealing is preferably performed by heat treatment or laser light irradiation. This annealing is effective for activating the implanted impurity ions and repairing the damage received by the implantation of the impurity ions.

[Embodiment 7] In this embodiment, in the structure shown in Embodiment 1, the low concentration impurity regions 122 and 124 (see FIG.
(See (B)), and further relates to a configuration in which an offset gate region is further arranged.

The offset gate region also has the effects of deterioration due to hot carriers, reduction of OFF current value, and substantial decrease in mobility due to increase in resistance value between source / drain. That is, the offset gate region has the same function as the low concentration impurity region represented by the LDD region.

The manufacturing process of this embodiment is shown in FIG. The basic manufacturing process is the same as in Example 1 (see FIGS. 1 to 3) unless otherwise specified. In FIG. 6, the same reference numerals as those in FIGS. 1 to 3 are the same as those described in the first embodiment.

The feature of this embodiment is that shown in FIG.
That is, the dense anodic oxide films 601 and 602 formed to cover the surfaces of the gate electrodes 11 and 12 shown in FIG.

The film thickness of the dense anodic oxide films 601 and 602 is set to 2000Å to 4000Å. The thickness of this anodic oxide film can be further increased, but the applied voltage at the time of anodic oxidation becomes a high voltage of 300 V or higher, which causes problems in reproducibility and safety.

The method of forming this dense anodic oxide film is basically the same as the method shown in the first embodiment. However, the applied voltage is changed according to the film thickness. There is a relationship between the film thickness and the applied voltage that the film thickness of the anodic oxide film increases as the applied voltage is increased.

Next, a resist mask 120 is formed to cover the element on the side of the P-channel type thin film transistor, and P ions are implanted in this state. The P ion implantation conditions are the same as in the first embodiment. (Fig. 6 (B))

By the implantation of the impurity ions, the source region 121 and the drain region 125 of the N-channel type thin film transistor and the channel forming region 123 are formed in a self-aligned manner. In addition, the low concentration impurity regions 122 and 12
4 are formed. Here, the low concentration impurity region 124 is the LD
It becomes the D area.

A region 603 that does not function as a channel and does not function as a source / drain region is formed as an offset gate region. One set of offset gate regions 603 is formed with a channel in between.

This offset gate area is shown in FIG.
In the step (1), the rough dimension is determined by the film thickness of the dense anodic oxide film 601 formed on the surface of the gate electrode.

After the step shown in FIG. 6B is completed, the resist mask 120 is removed, a resist mask 126 is newly placed to cover the N-channel type thin film transistor, and B ions are implanted. The B ion implantation conditions are the same as those shown in the first embodiment. (Fig. 6 (C))

In this step, the source region 128, the drain region 130 of the P-channel type thin film transistor,
The channel formation region 129 is formed in a self-aligned manner. Further, contact pads 127 and 131 are formed.

An offset gate region 604 is formed corresponding to the thickness of the anodic oxide film 602.

Then, the resist mask 126 is removed,
The state shown in FIG. 6D is obtained. Further, annealing is performed by irradiation with laser light.

When the configuration of this embodiment is adopted, N on the left side
The channel type thin film transistor has a low concentration impurity region 1
22 and 124 and the offset gate region 603 are used together. The present inventors collectively call the low-concentration impurity region and the offset gate region an HRD (high resistive drain) region.

The P-channel thin film transistor on the right side does not have a low-concentration impurity region, but can have a structure having an offset gate region 604.

As the film thicknesses of the dense anodic oxide films 601 and 602 are reduced, the offset gate region 603,
The function of 604 is reduced. The configuration is similar to that of the first embodiment.

Also, the offset gate regions 603, 60
There is no definite boundary as to how wide the width of 4, that is, the thickness of the anodic oxide film indicated by 601 and 602 or more can form the region recognized as the offset gate region.

Therefore, even in the case of the structure shown in the first embodiment, apart from the effect, the offset gate region exists between the source region and the channel forming region, and further between the drain region and the channel forming region. It can be said that

[Embodiment 8] This embodiment relates to a structure in which an active matrix region and a peripheral drive circuit for driving the active matrix region are integrated on a glass substrate.

One of the substrates constituting the integrated active matrix type liquid crystal display device has the following configuration. That is, in the active matrix region, at least one switching thin film transistor is arranged in each of the pixels arranged in a matrix, and peripheral circuits for driving the active matrix region are arranged around the active matrix region. ing. All of these circuits are integrated on one glass substrate (or quartz substrate).

When the invention disclosed in this specification is used for such a structure, an N-channel thin film transistor having a low OFF current characteristic is arranged in the pixel region, and the peripheral circuit is a CMOS circuit having a high characteristic. Can be configured.

That is, the peripheral circuit is formed by the CMOS structure shown in FIGS. 1 to 3, and at the same time, the N-channel type thin film transistor on the left side of FIGS. 1 to 3 is arranged in the active matrix region.

Since it is necessary for the thin film transistor arranged in the active matrix region to maintain the charge held in the pixel electrode for a predetermined time, it is desirable to make the OFF current value as small as possible.

Therefore, the thin film transistor having the low concentration impurity regions 122 and 124 as shown on the left side in FIG. 3B is optimal for this purpose.

On the other hand, a CMOS circuit is often used as the peripheral drive circuit. And in order to improve its characteristics, C
It is necessary to make the characteristics of the N-channel type thin film transistor and the P-channel type thin film transistor forming the MOS circuit uniform as much as possible.

For such a purpose, the CMOS structure as shown in the first embodiment (see FIGS. 1 to 3) is optimum.

In this way, it is possible to obtain an integrated active matrix type liquid crystal display device having a structure having preferable characteristics for each circuit.

In this embodiment, as an N-channel type thin film transistor, a low concentration impurity region (LDD region) is used.
An example of adopting a thin film transistor having is shown. However, as the N-channel type thin film transistor, a thin film transistor having an offset gate region as shown in Example 2 may be used. In addition, the HRD as shown in Example 7
A thin film transistor having a region may be used.

Further, the thin film transistor arranged in the active matrix region may be of P type. In this case, since the P-channel type thin film transistor has a strong resistance to deterioration, it is significant that a highly reliable image display region can be formed.

[Embodiment 9] In Embodiment 1, means for using a metal element that promotes crystallization when crystallizing the amorphous silicon film (nickel is used as an example of this metal element in this embodiment) It said that it can be taken. However, in this case, it is known that nickel remains in the crystalline silicon film after crystallization.

This nickel is above a certain concentration in the semiconductor layer (5 × 10 ¹⁹ pieces / cm ² according to the study by the present inventors).
Above), if contained, it adversely affects the electrical characteristics of the thin film transistor.

Therefore, in this example, an example using a technique of removing the metal element remaining in the crystalline silicon film forming the semiconductor layer of the thin film transistor will be described. This embodiment will be described with reference to FIG.

First, a substrate 701 having an insulating surface is prepared. However, when the crystalline silicon film is formed according to this embodiment, the processing temperature may be 1000 ° C. or higher,
It is necessary to prepare a substrate having excellent heat resistance.

In this embodiment, a quartz substrate is used as the substrate 701, and a silicon oxynitride film 702 is formed thereon as a buffer layer.
Is deposited to a thickness of 3000Å. This silicon oxynitride film 7
02 is formed by a sputtering method.

Next, an amorphous silicon film 703 is formed to a thickness of 500Å by the plasma CVD method or the low pressure thermal CVD method. Silane (SiH ₄ ), disilane (Si ₂ H ₆ ) or the like may be used as the film forming gas. When the amorphous silicon film 703 is formed by the low pressure thermal CVD method, it is convenient to increase the grain size (crystal grain size) because the generation rate of nuclei in the subsequent crystallization is small.

After forming the amorphous silicon film 703, UV light is irradiated in an oxygen atmosphere to form an extremely thin oxide film (not shown) on the surface of the amorphous silicon film 703. This oxide film is for improving the wettability of the solution in the solution applying step when Ni is introduced later (FIG. 7A).

Next, a nickel salt solution containing nickel at a predetermined concentration is dropped to form a water film 704 (FIG. 7).
(B)).

Considering residual impurities in the subsequent heating step, it is preferable to use a nickel nitrate salt solution as the nickel salt solution. It is possible to use a nickel acetate salt solution, but this is because the nickel acetate salt solution contains carbon, and there is a concern that it may be carbonized and remain in the silicon film in the subsequent heating step.

In the state of FIG. 7B, spin coating is performed using a spinner, and nickel in the water film 704 is held in contact with the amorphous silicon film 703 via an oxide film (not shown). And

Then, at 450 ° C. in an inert atmosphere,
After dehydrogenating for about 1 hour, 500-700
The amorphous silicon film 703 is crystallized by applying heat treatment at a temperature of 550 ° C., typically 550 to 600 ° C. for 1 to 24 hours. Thus, the crystalline silicon film 705 is obtained. (FIG. 7
(C))

Nickel is held in contact with the amorphous silicon film 703 via an oxide film (not shown) and then diffuses into the amorphous silicon film 703 through an oxide film (not shown) to serve as a catalyst for promoting crystallization. Function. Specifically, nickel and silicon react with each other to form a silicide, which serves as a nucleus to promote crystallization.

The concentration of nickel introduced at this time can be easily controlled by adjusting the concentration of the nickel salt solution in the solution coating step.

Further, it is effective to improve the crystallinity of the crystalline silicon film 705 by irradiating with laser light or intense light having energy equivalent to that after performing the above-mentioned crystallization by heat treatment. By this treatment, the amorphous portion slightly remaining after the heat treatment can be completely crystallized.

Next, the crystalline silicon film 705 obtained through the above steps is subjected to a heat treatment at a higher temperature. The temperature range of heat treatment is 700 to 1200 ° C., typically 800
The treatment time is 1 to 12 hours, typically 6 hours. At this time, it is important that the processing atmosphere is an atmosphere containing a halogen element (Cl is used in this embodiment). (FIG. 7 (D))

The feature of this embodiment is that the crystalline silicon film 70 is formed by performing heat treatment in an atmosphere containing a halogen element.
5 is to remove nickel. That is, the crystalline silicon film 705 is utilized by utilizing the gettering effect of the halogen element.
The purpose is to capture nickel in the thermal oxide film 706 formed above.

In the present embodiment, 10 is applied to the nitrogen atmosphere.
In an atmosphere containing oxygen at a concentration (volume concentration) of 3% and a concentration of HCl with respect to oxygen of 3%.
Heat treatment is performed at 50 ° C. for 6 hours. The reason for lowering the oxygen concentration is that if the oxygen concentration is high, the formation rate of the oxide film is too fast to obtain a sufficient gettering effect.

In this embodiment, C is used as the halogen element.
Although an example has been shown in which HCl gas is selected as a method of introducing l, HF, HBr, C are used as other gases.
It is possible to use one or more kinds selected from l ₂ , F ₂ and Br ₂ . Further, generally, a halogen hydride can also be used.

In this step, nickel in the crystalline silicon film 705 is converted to the thermal oxide film 706 by the action of the halogen element.
Gettered by. Therefore, nickel inside the crystalline silicon film 705 is removed, and a crystalline silicon film 707 containing almost no nickel in the film is obtained.

Since this heat treatment is performed at a relatively high temperature of 950 ° C., crystal defects such as dislocations and stacking faults almost disappear, and dangling bonds are recombined between silicon atoms. Furthermore, the unpaired bonds that cannot be compensated are crystalline silicon film 7
It is terminated by hydrogen and halogen elements contained in 07. That is, in other words, it can be said that the crystalline silicon film 707 contains hydrogen and halogen elements.

Next, when the step shown in FIG. 7D is completed, the thermal oxide film 706 which has become the gettering site is removed. As a result, nickel is added again to the crystalline silicon film 707.
Prevent it from spreading inside.

Next, the crystalline silicon film 707 formed according to the above steps is patterned into an island shape to form an N-channel type thin film transistor semiconductor layer 708 and a P-channel type thin film transistor semiconductor layer 709.
(FIG. 7E)

After that, N-channel and P-channel thin film transistors may be formed according to the first embodiment.

In the thin film transistor thus formed, the semiconductor layers 708 and 709 contain almost no metal element (nickel in this embodiment), so there is no fear of deterioration or characteristic deterioration due to the influence of the metal element.

That is, it is possible to form the active matrix region and the peripheral drive circuit with the thin film transistor having high reliability.

[Embodiment 10] This embodiment relates to a device for more thoroughly removing nickel element in the structure shown in Embodiment 9.

In this embodiment, a crystalline silicon film crystallized using nickel is obtained and then heat-treated in an oxidizing atmosphere containing a halogen element to form a thermal oxide film. This thermal oxide film absorbs nickel element and is contained at a higher concentration than in the crystalline silicon film.

After the thermal oxide film is formed, this thermal oxide film is removed. By doing so, the concentration of the nickel element remaining in the crystalline silicon film can be significantly reduced.

This effect can be obtained even when a metal element other than nickel that promotes crystallization of silicon is used.

A specific example is shown below. Here, by heating the crystalline silicon film crystallized using nickel in an oxygen atmosphere containing 3% by volume of HCl,
A thermal oxide film is formed.

The thickness of the thermal oxide film is preferably 200 Å or more. Then, this thermal oxide film is removed after the formation. This makes it possible to reduce the concentration of nickel element remaining in the crystalline silicon film.

Further, as the thermal oxide film is formed, unstable silicon components are consumed for forming the thermal oxide film, so that defects in the crystalline silicon film can be reduced. Then, the crystallinity can be increased.

[0218]

By using the invention disclosed in this specification, the following effects can be obtained. (1) Since it is not necessary to perform extreme heavy doping throughout the process, the problem of resist alteration can be avoided. (2) The OFF current can be reduced by disposing the low-concentration impurity region only in the N-channel thin film transistor. (3) In the case of adopting a CMOS structure by combining N-channel type and P-channel type thin film transistors, the difference in characteristics between the two can be corrected and a balance can be achieved. (4) When the impurity ions imparting P-type are implanted, the region adjacent to the channel is substantially intrinsic, so that the PI junction can be easily formed and damage to the semiconductor layer can be minimized. . (5) When the impurity ions are implanted, the semiconductor layer is covered with an insulating film such as a silicon oxide film, so that the problem of contamination and the problem of surface roughness can be avoided.

[Brief description of drawings]

FIG. 1 is a diagram showing a manufacturing process of a thin film transistor circuit having a CMOS structure according to a first embodiment.

2A to 2D are diagrams showing a manufacturing process of a thin film transistor circuit having a CMOS structure of Embodiment 1. FIGS.

3A to 3D are diagrams showing a manufacturing process of a thin film transistor circuit having a CMOS structure of Embodiment 1. FIGS.

FIG. 4 is a diagram showing a conventional manufacturing process of a thin film transistor circuit having a CMOS structure.

5A to 5C are diagrams showing a manufacturing process of a thin film transistor circuit having a CMOS structure of Example 2;

6A and 6B are diagrams showing a process of manufacturing a thin film transistor circuit having a CMOS structure according to a seventh embodiment.

FIG. 7 is a diagram showing a process of forming a semiconductor layer of Example 9;

[Explanation of symbols]

Reference Signs List 101 glass substrate 102 base film (silicon oxide film) 103 gate insulating film 104 semiconductor layer for N-channel type thin film transistor 105 semiconductor layer for P-channel type thin film transistor 106 aluminum film 107 dense anodic oxide film 108, 109 resist mask 110 , 111 Remaining aluminum film 112, 113 Porous anodic oxide film 11, 12 Gate electrodes 114, 115 Dense anodic oxide film 116-119 High concentration impurity region 120 Photoresist 121 Source region 122 Low concentration impurity region 123 Channel formation Region 124 Low-concentration impurity region (LDD region) 125 Drain region 126 Resist mask 127 Contact pad 128 Source region 129 Channel formation region 130 Drain region 131 Contact pad 1 2 interlayer insulating film 133 source electrode 134 drain electrode 135 source electrode 136 drain electrode 500 dense anodic oxide film 501 source region 502 drain regions 505 and 506 porous anodic oxide film 509 resist mask 510, 514 contact pad 511 source region 512 Channel forming region 513 Drain region 515, 517 Offset gate region 516 Channel forming region 601, 602 Dense anodic oxide film 603, 604 Offset gate region 703 Amorphous silicon film 704 Water film containing nickel 705 Crystallinity before nickel removal Silicon film 706 Thermal oxide film 707 Crystalline silicon film after removal of nickel 708 Semiconductor layer for N-channel thin film transistor 709 Semiconductor layer for P-channel thin film transistor

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code Agency reference number FI Technical display location H01L 29/78 627G

Claims (19)

[Claims] 1. A structure in which an N-channel type thin film transistor and a P-channel type thin film transistor are integrated on the same substrate, and only the N-channel type thin film transistor has L selectively.
A DD region is formed, and a source region and a drain region of the P-channel type thin film transistor are added only with an impurity imparting P-type conductivity. A semiconductor device having a region to which an impurity imparting p-type and p-type is added. 2. An N-channel thin film transistor and a P-channel thin film transistor are integrated on the same substrate, and the N-channel thin film transistor has a longer offset width than the P-channel thin film transistor. An offset gate region is selectively formed, and a source region and a drain region of the P-channel type thin film transistor are added with only an impurity imparting P-type conductivity. A semiconductor device, wherein a region to which an impurity imparting N-type and P-type is added is formed adjacent to each other. 3. The source region and the drain region according to claim 1 or 2, wherein the source region and the drain region are sandwiched between a region to which an impurity imparting N-type and P-type is added and a channel forming region. Semiconductor device. 4. The region to which an impurity imparting N-type and P-type is added has a function substantially only as an extraction electrode from a source region and a drain region. Characteristic semiconductor device. 5. The semiconductor device according to claim 1, wherein an impurity imparting one conductivity type is added to a channel formation region of an N-channel type and / or P-channel type thin film transistor. . 6. The N-channel type and / or P-channel type thin film transistor according to claim 1 or 2, wherein an offset gate region is arranged by using an insulating film formed on a side surface of the gate electrode. A semiconductor device characterized in that 7. The semiconductor device according to claim 1, wherein the semiconductor layers of the N-channel type and P-channel type thin film transistors contain hydrogen and a halogen element. 8. An active matrix region having thin film transistors arranged in a matrix on the same substrate, and a peripheral driving circuit for driving the thin film transistors arranged in the region, wherein the active matrix region has N-channels. Type thin film transistors are arranged, and in the peripheral driving circuit, a circuit in which an N-channel type thin film transistor and a P-channel type thin film transistor are configured in a complementary type is arranged, and the N-channel type thin film transistor arranged in the peripheral driving circuit is arranged. Type thin film transistors are selectively formed with LDD regions and / or offset gate regions, and only the impurity imparting P type is added to the source region and drain region of the P channel type thin film transistors arranged in the peripheral driving circuit. Adjacent to the source and drain regions. To N-type and P
A semiconductor device having a region to which an impurity imparting a mold is added. 9. An active matrix region having thin film transistors arranged in a matrix on the same substrate, and a peripheral drive circuit for driving the thin film transistors arranged in the region, wherein the active matrix region has a P channel. Type thin film transistors are arranged, and in the peripheral driving circuit, a circuit in which an N-channel type thin film transistor and a P-channel type thin film transistor are configured in a complementary type is arranged, and the N-channel type thin film transistor arranged in the peripheral driving circuit is arranged. LDD regions and / or offset gate regions are selectively formed in the thin film transistors, and P type is given to the source region and the drain region of the P channel type thin film transistors arranged in the active matrix region and the peripheral driving circuit. Only impurities are added. Adjacent to the scan and drain regions N-type and P
A semiconductor device having a region to which an impurity imparting a mold is added. 10. The semiconductor according to claim 8, wherein the source region and the drain region are sandwiched between a region to which an impurity imparting N-type and P-type is added and a channel forming region. apparatus. 11. A semiconductor device according to claim 8, wherein an impurity imparting one conductivity type is added to a channel forming region of an N-channel type and / or P-channel type thin film transistor. . 12. The semiconductor device according to claim 8, wherein the semiconductor layers of the N-channel type and P-channel type thin film transistors contain hydrogen and a halogen element. 13. A porous anodic oxide film is formed on a side surface of a gate electrode made of an anodic oxidizable material in a step of integrating and manufacturing an N-channel type thin film transistor and a P-channel type thin film transistor on the same substrate. A first step of selectively forming, a second step of adding an impurity imparting N-type with the anodized film as a mask, a third step of removing the anodized film, the P-channel type And a fourth step of selectively masking a region to be a thin film transistor with a photoresist, and using the gate electrode and the photoresist as a mask to add an impurity imparting N-type to a region below the region where the anodic oxide film was present. A fifth step of forming an LDD region, a sixth step of removing the photoresist formed in the fourth step, and the N-channel thin film transistor. A seventh step of selectively masking a region to be a transistor with a photoresist, and an eighth step of adding an impurity imparting P-type with the gate electrode and the photoresist as a mask, The eighth step forms a region under the region where the anodic oxide film was present, to which only an impurity imparting P-type is added, and at the same time, includes an impurity imparting N-type and P-type adjacent to the region. A method for manufacturing a semiconductor device, characterized in that a dark region is formed. 14. A porous anodic oxide film is formed on a side surface of a gate electrode made of an anodizable material in a process of integrating and manufacturing an N-channel type thin film transistor and a P-channel type thin film transistor on the same substrate. A first step of selectively forming, a second step of adding an impurity imparting N-type with the anodized film as a mask, a third step of removing the anodized film, the N-channel type A fourth step of selectively masking a region to be a thin film transistor with a photoresist, and a fifth step of adding an impurity imparting P-type using the gate electrode and the photoresist as a mask, An offset gate region, which is determined by the thickness of the porous anodic oxide film, is selected in the N-channel thin film transistor by the second step. A method for manufacturing a semiconductor device, which is formed selectively. 15. The method according to claim 13 or 14,
A method for manufacturing a semiconductor device, wherein the addition of impurities is performed by implanting accelerated impurity ions through a gate insulating film. 16. The method according to claim 13 or 14,
In the N-channel thin film transistor using the anodic oxide film formed in the first step, the LDD region and / or
Alternatively, a method for manufacturing a semiconductor device is characterized in that an offset gate region is formed and a source / drain region is formed in a P-channel thin film transistor. 17. The method according to claim 13 or 14,
When forming a crystalline silicon film forming a semiconductor layer of an N-channel type thin film transistor and a P-channel type thin film transistor, a first step of holding a metal element that promotes crystallization in the amorphous silicon film; A second step of transforming the crystalline silicon film into a crystalline silicon film by heat treatment; and heat-treating the crystalline silicon film in an atmosphere containing a halogen element to form a thermal oxide film on the surface of the crystalline silicon film. A third step of removing the thermal oxide film, and a fourth step of removing the thermal oxide film, wherein the metal element remaining in the crystalline silicon film by the third step is gettered in the thermal oxide film. A method for manufacturing a semiconductor device, which comprises ringing. 18. The method according to claim 17, wherein the second step is 50.
A method for manufacturing a semiconductor device, which is performed in a temperature range of 0 to 700 ° C. and the third step is performed in a temperature range of 700 to 1200 ° C. 19. The method for manufacturing a semiconductor device according to claim 17, wherein the atmosphere containing a halogen element is an atmosphere in which a halogen element is added to an oxidizing atmosphere.