JPH0927496A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPH0927496A
JPH0927496A JP7176992A JP17699295A JPH0927496A JP H0927496 A JPH0927496 A JP H0927496A JP 7176992 A JP7176992 A JP 7176992A JP 17699295 A JP17699295 A JP 17699295A JP H0927496 A JPH0927496 A JP H0927496A
Authority
JP
Japan
Prior art keywords
wiring layer
superconductor
current
integrated circuit
semiconductor integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7176992A
Other languages
Japanese (ja)
Inventor
Katsumi Tsuneno
克己 常野
Shinichiro Wada
真一郎 和田
Fumio Otsuka
文雄 大塚
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP7176992A priority Critical patent/JPH0927496A/en
Publication of JPH0927496A publication Critical patent/JPH0927496A/en
Pending legal-status Critical Current

Links

Classifications

    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E40/00Technologies for an efficient electrical power generation, transmission or distribution
    • Y02E40/60Superconducting electric elements or equipment; Power systems integrating superconducting elements or equipment

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Superconductors And Manufacturing Methods Therefor (AREA)
  • Superconductor Devices And Manufacturing Methods Thereof (AREA)

Abstract

PROBLEM TO BE SOLVED: To make a special protective circuit unnecessary by forming a wiring layer made of a normal conductor and a superconductor on a semiconductor substrate. SOLUTION: An Si oxide film 2 is attached on to an Si substrate 1, and on the Si oxide film 2 a wiring layer 3 of a specified pattern is formed. This wiring layer 3 is formed into a two-layer construction made by forming a superconductor 5 on a normal conductor 4 of metal etc. If the current of the wiring layer 3 exceeds a critical current value, the superconductor 5 changes to a normal conducting state, and the resistance value becomes the parallel resistance value (R1 +R2 )/R1 R2 of the resistance value R1 of the superconductor 5 being in a normal conducting state and the resistance value R2 of the normal conductor 4. Accordingly, a current flowing in the wiring layer 3 is controlled by the parallel resistance value (R1 +R2 )/R1 R2 , and does not exceed a critical current value. Besides, when the current flowing in the wiring layer 3 becomes the critical current value or less, the resistance value of the superconductor 5 returns to zero automatically, and the current flowing in the wiring layer 3 is controlled by the resistance value R2 of the normal conductor 4.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体集積回路装置に
関し、特に、過電流からの保護が必要なメモリLSI、
マイクロプロセッサまたはプリント基板回路等を有する
半導体集積回路装置に適用して有効な技術に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a memory LSI requiring protection from overcurrent,
The present invention relates to a technique effectively applied to a semiconductor integrated circuit device having a microprocessor or a printed circuit board.

【0002】[0002]

【従来の技術】近年、半導体集積回路装置の高速化およ
び低電力化が進められている。ところが、低電力化を進
めると、各素子自体の過電流に対するマージンが小さく
なるため、通常は過電流に対して素子を保護するため
に、半導体集積回路装置に保護回路を接続し、過電流状
態を回避している。
2. Description of the Related Art In recent years, semiconductor integrated circuit devices have been advanced in speed and power consumption. However, as the power consumption is reduced, the margin for the overcurrent of each element itself becomes smaller, so normally, in order to protect the element against the overcurrent, a protection circuit is connected to the semiconductor integrated circuit device, and Is avoiding.

【0003】なお、このような技術としては、1985
年1月10日、岩波書店発行、渡辺誠、浅田邦博、可児
賢二、大附辰夫(著)「岩波講座マイクロエレクトロニ
クス3 VLSIの設計」P91〜P93に開示されて
いる。
Incidentally, as such a technique, 1985
Published by Iwanami Shoten on January 10, 2004, Makoto Watanabe, Kunihiro Asada, Kenji Kani, Tatsuo Otsuki (Author), "Design of Iwanami Course Microelectronics 3 VLSI", P91 to P93.

【0004】[0004]

【発明が解決しようとする課題】ところが、前述した半
導体集積回路装置においては、次のような問題点がある
ことが本発明者により見い出された。
However, the present inventor has found that the above-described semiconductor integrated circuit device has the following problems.

【0005】すなわち、新たに保護回路を必要とするの
で、コスト高になる。また、保護回路を半導体集積回路
装置に接続しなければならないため、半導体集積回路装
置のレイアウトが複雑になると共に、製造工程が煩雑化
し、半導体集積回路装置が大型化する。
That is, since a new protection circuit is required, the cost becomes high. Further, since the protection circuit must be connected to the semiconductor integrated circuit device, the layout of the semiconductor integrated circuit device becomes complicated, the manufacturing process becomes complicated, and the semiconductor integrated circuit device becomes large.

【0006】本発明の目的は、特別な保護回路を必要と
しない半導体集積回路装置を提供することにある。
An object of the present invention is to provide a semiconductor integrated circuit device which does not require a special protection circuit.

【0007】本発明の前記ならびにその他の目的と新規
な特徴は、本明細書の記述および添付図面から明らかに
なるであろう。
[0007] The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

【0008】[0008]

【課題を解決するための手段】本願において開示される
発明のうち、代表的なものの概要を簡単に説明すれば、
以下のとおりである。
SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

【0009】(1)本発明の半導体集積回路装置は、半
導体基板上に常伝導体および超伝導体からなる配線層が
形成されたものである。
(1) The semiconductor integrated circuit device of the present invention has a wiring layer made of a normal conductor and a superconductor formed on a semiconductor substrate.

【0010】(2)本発明の半導体集積回路装置は、半
導体基板上に超伝導体からなり、電流経路が絶縁体によ
り絶縁された配線層が形成されたものである。
(2) The semiconductor integrated circuit device of the present invention comprises a wiring layer formed of a superconductor and having a current path insulated by an insulator on a semiconductor substrate.

【0011】(3)本発明の半導体集積回路装置は、半
導体基板上に超伝導体からなり、電流経路が絶縁体によ
り絶縁され、超伝導体の上面および下面の少なくとも一
方に常伝導体が形成された配線層を有するものである。
(3) The semiconductor integrated circuit device of the present invention comprises a superconductor on a semiconductor substrate, a current path is insulated by an insulator, and a normal conductor is formed on at least one of an upper surface and a lower surface of the superconductor. And a wiring layer that has been formed.

【0012】(4)本発明の半導体集積回路装置は、半
導体基板上に超伝導体からなり、電流経路が絶縁体によ
り一部絶縁された配線層が形成されたものである。
(4) In the semiconductor integrated circuit device of the present invention, a wiring layer made of a superconductor and having a current path partially insulated by an insulator is formed on a semiconductor substrate.

【0013】(5)本発明の半導体集積回路装置は、半
導体基板上に常伝導体および超伝導体からなり、電流経
路を絶縁する絶縁体が常伝導体と超伝導体との界面に形
成された配線層を有するものである。
(5) The semiconductor integrated circuit device of the present invention comprises a normal conductor and a superconductor on a semiconductor substrate, and an insulator for insulating a current path is formed at an interface between the normal conductor and the superconductor. It has a wiring layer.

【0014】(6)本発明の半導体集積回路装置は、半
導体基板上に第1の常伝導体および超伝導体ならびに第
1の常伝導体と超伝導体との界面に形成され電流経路を
絶縁する絶縁体と、第1の常伝導体および超伝導体の上
面および下面の少なくとも一方に形成された第2の常伝
導体とからなる配線層を有するものである。
(6) The semiconductor integrated circuit device of the present invention is formed on a semiconductor substrate at a first normal conductor and a superconductor and at an interface between the first normal conductor and the superconductor, and insulates a current path. And a second normal conductor formed on at least one of the upper surface and the lower surface of the first normal conductor and the superconductor.

【0015】[0015]

【作用】前述した手段によれば、配線層を常伝導体およ
び超伝導体により形成したので、配線層に流れる電流が
臨界電流値を越えると、超伝導体は常伝導状態に転移
し、配線層は超伝導体が常伝導状態のときの抵抗値と常
伝導体の抵抗値との並列抵抗値によって制御される。配
線層に流れる電流が臨界電流値以下の場合、配線層の電
流は超伝導状態となる。
According to the above-mentioned means, since the wiring layer is formed of the normal conductor and the superconductor, when the current flowing through the wiring layer exceeds the critical current value, the superconductor is transformed into the normal conduction state and the wiring The layer is controlled by the parallel resistance value of the resistance value of the normal conductor and that of the normal conductor. When the current flowing through the wiring layer is less than or equal to the critical current value, the current in the wiring layer becomes superconducting.

【0016】また、前述した手段によれば、超伝導体か
らなる配線層の電流経路を絶縁体により絶縁したので、
配線層に流れる電流が臨界電流値以下の場合、超伝導体
中の絶縁体にトンネル電流が流れる。配線層に流れる電
流が臨界電流値以上になると、超伝導体は常伝導状態に
転移するため、配線層に流れる電流は絶縁体により完全
に遮断される。
Further, according to the above-mentioned means, since the current path of the wiring layer made of the superconductor is insulated by the insulator,
When the current flowing through the wiring layer is below the critical current value, a tunnel current flows through the insulator in the superconductor. When the current flowing in the wiring layer exceeds the critical current value, the superconductor transitions to the normal conduction state, so that the current flowing in the wiring layer is completely blocked by the insulator.

【0017】さらに、前述した手段によれば、超伝導体
からなる配線層の電流経路を絶縁体により絶縁し、超伝
導体の上面および下面の少なくとも一方に常伝導体を形
成したので、超伝導体が超伝導状態のとき、絶縁体にト
ンネル電流が流れ、配線層に流れる電流が臨界電流値以
上になると、超伝導体は常伝導状態に転移するため、超
伝導体に流れる電流は絶縁体により遮断されるが、配線
層には常伝導体の抵抗値により制御された電流が流れ
る。
Further, according to the above-mentioned means, the current path of the wiring layer made of the superconductor is insulated by the insulator, and the normal conductor is formed on at least one of the upper surface and the lower surface of the superconductor. When the body is in the superconducting state, a tunnel current flows in the insulator, and when the current flowing in the wiring layer exceeds the critical current value, the superconductor transitions to the normal state, so the current flowing in the superconductor is the insulator. However, a current controlled by the resistance value of the normal conductor flows through the wiring layer.

【0018】また、前述した手段によれば、超伝導体か
らなる配線層の電流経路を絶縁体により一部絶縁したの
で、超伝導体が超伝導状態のとき、電流は配線層の全て
の断面を流れる。配線層に流れる電流が臨界電流値以上
になると、超伝導体は常伝導状態に転移するため、絶縁
体が配線層の有効断面積を減らし、実効的な配線層の抵
抗値が増加する。
Further, according to the above-mentioned means, since the current path of the wiring layer made of the superconductor is partially insulated by the insulator, when the superconductor is in the superconducting state, the current flows in all the cross sections of the wiring layer. Flowing through. When the current flowing in the wiring layer exceeds the critical current value, the superconductor transitions to the normal conduction state, so that the insulator reduces the effective sectional area of the wiring layer and the effective resistance value of the wiring layer increases.

【0019】さらに、前述した手段によれば、常伝導体
および超伝導体からなる配線層の電流経路を絶縁する絶
縁体を常伝導体と超伝導体との界面に形成したので、超
伝導体が超伝導状態のとき、絶縁体にトンネル電流が流
れる。配線層に流れる電流が臨界電流値以上になると、
超伝導体は常伝導状態に転移するため、配線層に流れる
電流は絶縁体により完全に遮断される。
Further, according to the above-mentioned means, since the insulator for insulating the current path of the wiring layer composed of the normal conductor and the superconductor is formed at the interface between the normal conductor and the superconductor, the superconductor When is in the superconducting state, a tunnel current flows through the insulator. When the current flowing in the wiring layer exceeds the critical current value,
Since the superconductor transitions to the normal state, the current flowing in the wiring layer is completely cut off by the insulator.

【0020】さらにまた、前述した手段によれば、第1
の常伝導体および超伝導体からなる配線層の電流経路を
絶縁する絶縁体を第1の常伝導体と超伝導体との界面に
形成し、第1の常伝導体および超伝導体の上面および下
面の少なくとも一方に第2の常伝導体を形成したので、
超伝導体が超伝導状態のとき、絶縁体にトンネル電流が
流れる。配線層に流れる電流が臨界電流値以上になる
と、超伝導体は常伝導状態に転移するため、超伝導体に
流れる電流は絶縁体により遮断され、配線層には第2の
常伝導体の抵抗値により制御された電流が流れる。
Furthermore, according to the above-mentioned means, the first
And an upper surface of the first normal conductor and the superconductor by forming an insulator at the interface between the first normal conductor and the superconductor to insulate the current path of the wiring layer including the normal conductor and the superconductor. And since the second normal conductor is formed on at least one of the lower surface,
When the superconductor is in the superconducting state, a tunnel current flows in the insulator. When the current flowing in the wiring layer exceeds the critical current value, the superconductor transitions to the normal conduction state, so the current flowing in the superconductor is blocked by the insulator, and the resistance of the second normal conductor in the wiring layer. A current controlled by the value flows.

【0021】[0021]

【実施例】以下、本発明の半導体集積回路装置に係る実
施例を図面に基づいて詳細に説明する。なお、実施例を
説明するための全図において同一の機能を有するものは
同一の符号を付け、その繰り返しの説明は省略する。
Embodiments of the semiconductor integrated circuit device according to the present invention will be described below in detail with reference to the drawings. In all the drawings for explaining the embodiments, those having the same function are designated by the same reference numerals, and the repeated description thereof will be omitted.

【0022】(実施例1)図1(a)は、本発明の第1
実施例に係る半導体集積回路装置の横断面図、(b)は
本発明の第1実施例に係る配線層の縦断面図である。
(Embodiment 1) FIG. 1A shows a first embodiment of the present invention.
1B is a horizontal cross-sectional view of a semiconductor integrated circuit device according to an embodiment, and FIG. 1B is a vertical cross-sectional view of a wiring layer according to the first embodiment of the present invention.

【0023】図1において、半導体集積回路装置は、シ
リコン基板1上にシリコン酸化膜2が被着され、シリコ
ン酸化膜2上には所定パターンの配線層3が形成されて
いる。この配線層3は金属等の常伝導体4上にNbまた
はY−B−Cu−O系のペロブスカイト構造の超伝導体
5が積層された2層構造に形成されている。
In FIG. 1, in a semiconductor integrated circuit device, a silicon oxide film 2 is deposited on a silicon substrate 1, and a wiring layer 3 having a predetermined pattern is formed on the silicon oxide film 2. The wiring layer 3 is formed in a two-layer structure in which a superconductor 5 having a perovskite structure of Nb or YB-Cu-O system is laminated on a normal conductor 4 such as metal.

【0024】超伝導体5では、臨界電流値以上の電流が
流れた場合、超伝導状態が破られ、常伝導状態に転移す
るが、臨界電流値以下の電流が流れている間は、超伝導
状態が保たれる。また、超伝導体5の臨界電流値は、磁
界、温度および配線層3の断面積によって制御される。
In the superconductor 5, the superconducting state is broken and the state is changed to the normal conducting state when a current more than the critical current value flows, but the superconducting state is maintained while the current less than the critical current value flows. The state is maintained. Moreover, the critical current value of the superconductor 5 is controlled by the magnetic field, the temperature, and the cross-sectional area of the wiring layer 3.

【0025】従って、配線層3に流れる電流が臨界電流
値を越えると、超伝導体5は常伝導状態に転移し、配線
層3の抵抗値は超伝導体5が常伝導状態のときの抵抗値
1と常伝導体4の抵抗値R2 との並列抵抗値(R1
2)/R1 2 になる。よって、配線層3を流れる電流
は、並列抵抗値(R1 +R2)/R1 2 によって制御さ
れ、配線層3に臨界電流値を越える電流が流れることは
ない。
Therefore, when the current flowing through the wiring layer 3 exceeds the critical current value, the superconductor 5 is transformed into the normal conduction state, and the resistance value of the wiring layer 3 is the resistance when the superconductor 5 is in the normal conduction state. Parallel resistance value of the value R 1 and the resistance value R 2 of the normal conductor 4 (R 1 +
R 2 ) / R 1 R 2 . Therefore, the current flowing through the wiring layer 3 is controlled by the parallel resistance value (R 1 + R 2 ) / R 1 R 2 , and the current that exceeds the critical current value does not flow through the wiring layer 3.

【0026】また、配線層3に流れる電流が臨界電流値
以下になると、超伝導体5が超伝導状態、つまり、抵抗
値が0に自動復帰し、配線層3を流れる電流は常伝導体
4の抵抗値R2 によって制御される。
When the current flowing through the wiring layer 3 becomes equal to or lower than the critical current value, the superconductor 5 is in a superconducting state, that is, the resistance value is automatically returned to 0, and the current flowing through the wiring layer 3 is the normal conductor 4. Is controlled by the resistance value R 2 of.

【0027】このように、第1実施例によれば、超伝導
体5が電流の大きさにより超伝導状態または常伝導状態
に切り換わることにより、電流リミッターとして動作す
るので、過電流が阻止でき、過電流より半導体集積回路
装置の各素子を保護することができる。
As described above, according to the first embodiment, since the superconductor 5 is switched to the superconducting state or the normal conducting state according to the magnitude of the current, the superconductor 5 operates as a current limiter, so that the overcurrent can be prevented. It is possible to protect each element of the semiconductor integrated circuit device from overcurrent.

【0028】(実施例2)図2(a)は、本発明の第2
実施例に係る半導体集積回路装置の横断面図、(b)は
本発明の第2実施例に係る配線層の縦断面図である。
(Embodiment 2) FIG. 2A shows a second embodiment of the present invention.
FIG. 3B is a horizontal cross-sectional view of the semiconductor integrated circuit device according to the embodiment, and FIG. 3B is a vertical cross-sectional view of the wiring layer according to the second embodiment of the present invention.

【0029】図2において、半導体集積回路装置は、シ
リコン基板1上にシリコン酸化膜2が被着され、シリコ
ン酸化膜2上には所定パターンの配線層6が形成されて
いる。この配線層6は超伝導体5からなり、配線層6の
電流経路が薄い絶縁体7により絶縁されている。
In FIG. 2, in the semiconductor integrated circuit device, a silicon oxide film 2 is deposited on a silicon substrate 1, and a wiring layer 6 having a predetermined pattern is formed on the silicon oxide film 2. The wiring layer 6 is made of a superconductor 5, and the current path of the wiring layer 6 is insulated by a thin insulator 7.

【0030】配線層6に流れる電流が臨界電流値以下の
場合、すなわち、超伝導体5が超伝導状態のとき、超伝
導体5中の絶縁体7を電流が通過する(トンネル効
果)。
When the current flowing through the wiring layer 6 is below the critical current value, that is, when the superconductor 5 is in the superconducting state, the current passes through the insulator 7 in the superconductor 5 (tunnel effect).

【0031】従って、配線層6に流れる電流が臨界電流
値以下のとき、超伝導体5は超伝導状態なので、絶縁体
7にトンネル電流が流れる。配線層6に流れる電流が臨
界電流値以上になると、超伝導体5は常伝導状態に転移
するため、配線層6に流れる電流は絶縁体7により完全
に遮断される。
Therefore, when the current flowing through the wiring layer 6 is below the critical current value, the superconductor 5 is in the superconducting state, so that the tunnel current flows through the insulator 7. When the current flowing through the wiring layer 6 becomes equal to or higher than the critical current value, the superconductor 5 transitions to the normal conduction state, so that the current flowing through the wiring layer 6 is completely cut off by the insulator 7.

【0032】このように、第2実施例によれば、配線層
6に臨界電流値以上の電流が流れると、超伝導体5およ
び絶縁体7が電流リミッターとして動作するので、半導
体集積回路装置の各素子を過電流より保護することがで
きる。
As described above, according to the second embodiment, when a current exceeding the critical current value flows through the wiring layer 6, the superconductor 5 and the insulator 7 operate as a current limiter. Each element can be protected from overcurrent.

【0033】(実施例3)図3(a)は、本発明の第3
実施例に係る半導体集積回路装置の横断面図、(b)は
本発明の第3実施例に係る配線層の縦断面図である。
(Embodiment 3) FIG. 3A shows a third embodiment of the present invention.
FIG. 3B is a horizontal cross-sectional view of the semiconductor integrated circuit device according to the embodiment, and FIG. 3B is a vertical cross-sectional view of the wiring layer according to the third embodiment of the present invention.

【0034】図3において、半導体集積回路装置は、シ
リコン基板1上にシリコン酸化膜2が被着され、シリコ
ン酸化膜2上には所定パターンの配線層8が形成されて
いる。この配線層8は超伝導体5からなり、配線層8の
電流経路が薄い絶縁体7により絶縁され、超伝導体5の
上面および下面には常伝導体4が形成されている。
In FIG. 3, in the semiconductor integrated circuit device, a silicon oxide film 2 is deposited on a silicon substrate 1, and a wiring layer 8 having a predetermined pattern is formed on the silicon oxide film 2. The wiring layer 8 is made of a superconductor 5, the current path of the wiring layer 8 is insulated by a thin insulator 7, and the normal conductor 4 is formed on the upper surface and the lower surface of the superconductor 5.

【0035】超伝導体5が超伝導状態のとき、絶縁体7
にトンネル電流が流れ、配線層8に流れる電流が臨界電
流値以上になると、超伝導体5は常伝導状態に転移する
ため、超伝導体5に流れる電流は絶縁体7により遮断さ
れるが、配線層8には常伝導体4の抵抗値R2 により制
御された電流が流れる。
When the superconductor 5 is in the superconducting state, the insulator 7
When a tunnel current flows through the wiring layer 8 and the current flowing through the wiring layer 8 exceeds the critical current value, the superconductor 5 transitions to the normal state, so that the current flowing through the superconductor 5 is blocked by the insulator 7. A current controlled by the resistance value R 2 of the normal conductor 4 flows through the wiring layer 8.

【0036】このように、第3実施例によれば、配線層
8に臨界電流値以上の電流が流れると、超伝導体5およ
び絶縁体7が電流リミッターとして動作し、配線層8を
流れる電流は常伝導体4の抵抗値R2 のみにより制御さ
れるので、超伝導体5の常伝導状態時の抵抗値を考慮す
ることなく、配線層8の電流が容易に制御でき、半導体
集積回路装置の各素子を過電流より保護することができ
る。
As described above, according to the third embodiment, when a current exceeding the critical current value flows through the wiring layer 8, the superconductor 5 and the insulator 7 act as a current limiter, and the current flowing through the wiring layer 8 is increased. Is controlled only by the resistance value R 2 of the normal conductor 4, the current of the wiring layer 8 can be easily controlled without considering the resistance value of the superconductor 5 in the normal conduction state. Each element can be protected from overcurrent.

【0037】(実施例4)図4(a)は、本発明の第4
実施例に係る半導体集積回路装置の横断面図、(b)は
本発明の第4実施例に係る配線層の縦断面図である。
(Embodiment 4) FIG. 4A shows a fourth embodiment of the present invention.
FIG. 6B is a horizontal cross-sectional view of the semiconductor integrated circuit device according to the embodiment, and FIG. 7B is a vertical cross-sectional view of the wiring layer according to the fourth embodiment of the present invention.

【0038】図4において、半導体集積回路装置は、シ
リコン基板1上にシリコン酸化膜2が被着され、シリコ
ン酸化膜2上には所定パターンの配線層9が形成されて
いる。この配線層9は超伝導体5からなり、配線層9の
電流経路の一部分が薄い絶縁体7により絶縁されてい
る。
In FIG. 4, in the semiconductor integrated circuit device, a silicon oxide film 2 is deposited on a silicon substrate 1, and a wiring layer 9 having a predetermined pattern is formed on the silicon oxide film 2. The wiring layer 9 is made of a superconductor 5, and a part of the current path of the wiring layer 9 is insulated by a thin insulator 7.

【0039】超伝導体5が超伝導状態のとき、電流は配
線層9の全ての断面を流れる。また、配線層9に流れる
電流が臨界電流値以上になると、超伝導体5は常伝導状
態に転移するため、絶縁体7が配線層9の有効断面積を
減らし、実効的な配線層9の抵抗値が増加するので、常
伝導体4を付加することなく電流が制御される。よっ
て、半導体集積回路装置の各素子を過電流より保護する
ことができる。
When the superconductor 5 is in the superconducting state, the current flows in all the cross sections of the wiring layer 9. Further, when the current flowing in the wiring layer 9 becomes equal to or higher than the critical current value, the superconductor 5 transitions to the normal conduction state, so that the insulator 7 reduces the effective cross-sectional area of the wiring layer 9 and the effective wiring layer 9 Since the resistance value increases, the current is controlled without adding the normal conductor 4. Therefore, each element of the semiconductor integrated circuit device can be protected from overcurrent.

【0040】(実施例5)図5(a)は、本発明の第5
実施例に係る半導体集積回路装置の横断面図、(b)は
本発明の第5実施例に係る配線層の縦断面図である。
(Embodiment 5) FIG. 5A shows a fifth embodiment of the present invention.
FIG. 7B is a horizontal cross-sectional view of the semiconductor integrated circuit device according to the embodiment, and FIG. 7B is a vertical cross-sectional view of the wiring layer according to the fifth embodiment of the present invention.

【0041】図5において、半導体集積回路装置は、シ
リコン基板1上にシリコン酸化膜2が被着され、シリコ
ン酸化膜2上には所定パターンの配線層10が形成され
ている。この配線層10は常伝導体11および超伝導体
5からなり、配線層10の電流経路を絶縁する絶縁体7
が常伝導体11と超伝導体5との界面に形成されてい
る。
In FIG. 5, in the semiconductor integrated circuit device, a silicon oxide film 2 is deposited on a silicon substrate 1, and a wiring layer 10 having a predetermined pattern is formed on the silicon oxide film 2. The wiring layer 10 includes a normal conductor 11 and a superconductor 5, and an insulator 7 that insulates a current path of the wiring layer 10.
Are formed at the interface between the normal conductor 11 and the superconductor 5.

【0042】超伝導体5が超伝導状態のとき、絶縁体7
にトンネル電流が流れる。また、配線層10に流れる電
流が臨界電流値以上になると、超伝導体5は常伝導状態
に転移するため、配線層10に流れる電流は絶縁体7に
より完全に遮断される。
When the superconductor 5 is in the superconducting state, the insulator 7
Tunnel current flows through Further, when the current flowing through the wiring layer 10 becomes equal to or higher than the critical current value, the superconductor 5 transitions to the normal conduction state, so that the current flowing through the wiring layer 10 is completely cut off by the insulator 7.

【0043】このように、第5実施例によれば、配線層
10に臨界電流値以上の電流が流れると、超伝導体5お
よび絶縁体7が電流リミッターとして動作するので、半
導体集積回路装置の各素子を過電流より保護することが
できる。
As described above, according to the fifth embodiment, when a current exceeding the critical current value flows through the wiring layer 10, the superconductor 5 and the insulator 7 operate as a current limiter, so that the semiconductor integrated circuit device Each element can be protected from overcurrent.

【0044】(実施例6)図6(a)は、本発明の第6
実施例に係る半導体集積回路装置の横断面図、(b)は
本発明の第6実施例に係る配線層の縦断面図である。
(Embodiment 6) FIG. 6A shows a sixth embodiment of the present invention.
FIG. 11B is a horizontal cross-sectional view of the semiconductor integrated circuit device according to the embodiment, and FIG. 9B is a vertical cross-sectional view of the wiring layer according to the sixth embodiment of the present invention.

【0045】図6において、半導体集積回路は、シリコ
ン基板1上にシリコン酸化膜2が被着され、シリコン酸
化膜2上には所定パターンの配線層12が形成されてい
る。この配線層12は常伝導体11および超伝導体5か
らなり、配線層12の電流経路を絶縁する絶縁体7が常
伝導体11と超伝導体5との界面に形成され、常伝導体
11および超伝導体5の上面および下面に常伝導体4が
形成されている。
In FIG. 6, in a semiconductor integrated circuit, a silicon oxide film 2 is deposited on a silicon substrate 1, and a wiring layer 12 having a predetermined pattern is formed on the silicon oxide film 2. The wiring layer 12 is composed of a normal conductor 11 and a superconductor 5, and an insulator 7 that insulates the current path of the wiring layer 12 is formed at the interface between the normal conductor 11 and the superconductor 5. The normal conductor 4 is formed on the upper and lower surfaces of the superconductor 5.

【0046】超伝導体5が超伝導状態のとき、絶縁体7
にトンネル電流が流れる。また、配線層12に流れる電
流が臨界電流値以上になると、超伝導体5は常伝導状態
に転移するため、超伝導体5に流れる電流は絶縁体7に
より遮断され、配線層12には常伝導体4の抵抗値R2
により制御された電流が流れる。
When the superconductor 5 is in the superconducting state, the insulator 7
Tunnel current flows through Further, when the current flowing in the wiring layer 12 becomes equal to or higher than the critical current value, the superconductor 5 transitions to the normal conduction state, so that the current flowing in the superconductor 5 is blocked by the insulator 7 and the wiring layer 12 is normally closed. Resistance value of conductor 4 R 2
An electric current controlled by is flowing.

【0047】このように、第6実施例によれば、配線層
12に臨界電流値以上の電流が流れると、超伝導体5お
よび絶縁体7が電流リミッターとして動作し、配線層1
2を流れる電流は常伝導体4の抵抗値R2 のみにより制
御されるので、超伝導体5の常伝導状態時の抵抗値を考
慮することなく、配線層12の電流が容易に制御でき、
半導体集積回路装置の各素子を過電流より保護すること
ができる。
As described above, according to the sixth embodiment, when a current exceeding the critical current value flows through the wiring layer 12, the superconductor 5 and the insulator 7 operate as a current limiter, and the wiring layer 1
Since the current flowing through 2 is controlled only by the resistance value R 2 of the normal conductor 4, the current of the wiring layer 12 can be easily controlled without considering the resistance value of the superconductor 5 in the normal conduction state,
Each element of the semiconductor integrated circuit device can be protected from overcurrent.

【0048】以上、本発明者によってなされた発明を、
実施例に基づき具体的に説明したが、本発明は、前記実
施例に限定されるものではなく、その要旨を逸脱しない
範囲で種々変更可能であることは言うまでもない。
As described above, the invention made by the present inventor is
Although the present invention has been specifically described based on the embodiments, it is needless to say that the present invention is not limited to the embodiments and various modifications can be made without departing from the scope of the invention.

【0049】[0049]

【発明の効果】本願によって開示される発明のうち、代
表的なものによって得られる効果を簡単に説明すれば、
以下のとおりである。
Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

【0050】(1)本発明の半導体集積回路装置によれ
ば、配線層を常伝導体および超伝導体により形成したの
で、超伝導体が電流リミッターとして動作し、過電流を
阻止できるので、過電流より半導体集積回路装置の各素
子を保護することができる。
(1) According to the semiconductor integrated circuit device of the present invention, since the wiring layer is formed of the normal conductor and the superconductor, the superconductor acts as a current limiter and can prevent an overcurrent. Each element of the semiconductor integrated circuit device can be protected from the electric current.

【0051】(2)本発明の半導体集積回路装置によれ
ば、超伝導体からなる配線層の電流経路を絶縁体により
絶縁したので、配線層に臨界電流値以上の電流が流れる
と、超伝導体および絶縁体が電流リミッターとして動作
するので、半導体集積回路装置の各素子を過電流より保
護することができる。
(2) According to the semiconductor integrated circuit device of the present invention, the current path of the wiring layer made of a superconductor is insulated by the insulator. Therefore, when a current exceeding the critical current value flows in the wiring layer, the superconductivity is reduced. Since the body and the insulator operate as a current limiter, each element of the semiconductor integrated circuit device can be protected from overcurrent.

【0052】(3)本発明の半導体集積回路装置によれ
ば、超伝導体からなる配線層の電流経路を絶縁体により
絶縁し、超伝導体の上面および下面の少なくとも一方に
常伝導体を形成したので、配線層に臨界電流値以上の電
流が流れると、超伝導体および絶縁体が電流リミッター
として動作し、配線層を流れる電流は常伝導体の抵抗値
のみにより制御されるので、超伝導体の常伝導状態時の
抵抗値を考慮することなく、配線層の電流が容易に制御
でき、半導体集積回路装置の各素子を過電流より保護す
ることができる。
(3) According to the semiconductor integrated circuit device of the present invention, the current path of the wiring layer made of a superconductor is insulated by the insulator, and the normal conductor is formed on at least one of the upper surface and the lower surface of the superconductor. Therefore, when a current exceeding the critical current value flows in the wiring layer, the superconductor and the insulator act as a current limiter, and the current flowing in the wiring layer is controlled only by the resistance value of the normal conductor. The current of the wiring layer can be easily controlled without considering the resistance value of the body in the normal conduction state, and each element of the semiconductor integrated circuit device can be protected from overcurrent.

【0053】(4)本発明の半導体集積回路装置によれ
ば、超伝導体からなる配線層の電流経路を絶縁体により
一部絶縁したので、配線層に流れる電流が臨界電流値以
上になると、絶縁体が配線層の有効断面積を減らし、実
効的な配線層の抵抗値が増加するので、常伝導体を付加
することなく電流を制御することができ、半導体集積回
路装置の各素子を過電流より保護することができる。
(4) According to the semiconductor integrated circuit device of the present invention, since the current path of the wiring layer made of a superconductor is partially insulated by the insulator, when the current flowing in the wiring layer becomes equal to or higher than the critical current value, Since the insulator reduces the effective sectional area of the wiring layer and increases the effective resistance value of the wiring layer, the current can be controlled without adding a normal conductor, and each element of the semiconductor integrated circuit device can be controlled. It can be protected from electric current.

【0054】(5)本発明の半導体集積回路装置によれ
ば、常伝導体および超伝導体からなる配線層の電流経路
を絶縁する絶縁体を常伝導体と超伝導体との界面に形成
したので、配線層に臨界電流値以上の電流が流れると、
超伝導体および絶縁体が電流リミッターとして動作する
ので、半導体集積回路装置の各素子を過電流より保護す
ることができる。
(5) According to the semiconductor integrated circuit device of the present invention, the insulator for insulating the current path of the wiring layer made of the normal conductor and the superconductor is formed at the interface between the normal conductor and the superconductor. Therefore, if a current exceeding the critical current value flows in the wiring layer,
Since the superconductor and the insulator act as a current limiter, each element of the semiconductor integrated circuit device can be protected from overcurrent.

【0055】(6)本発明の半導体集積回路装置によれ
ば、第1の常伝導体および超伝導体からなる配線層の電
流経路を絶縁する絶縁体を第1の常伝導体と超伝導体と
の界面に形成し、第1の常伝導体および超伝導体の上面
および下面の少なくとも一方に第2の常伝導体を形成し
たので、配線層に臨界電流値以上の電流が流れると、超
伝導体および絶縁体が電流リミッターとして動作し、配
線層を流れる電流は常伝導体の抵抗値のみにより制御さ
れるので、超伝導体の常伝導状態時の抵抗値を考慮する
ことなく、配線層の電流が容易に制御でき、半導体集積
回路装置の各素子を過電流より保護することができる。
(6) According to the semiconductor integrated circuit device of the present invention, the insulator for insulating the current path of the wiring layer composed of the first normal conductor and the superconductor is the first normal conductor and the superconductor. Since the second normal conductor is formed on the interface between the first normal conductor and the superconductor, and the second normal conductor is formed on at least one of the upper surface and the lower surface of the first normal conductor and the superconductor, when a current exceeding the critical current value flows in the wiring layer, Since the conductor and the insulator act as a current limiter and the current flowing through the wiring layer is controlled only by the resistance value of the normal conductor, the resistance value of the superconductor in the normal conduction state is not taken into consideration. Can be easily controlled, and each element of the semiconductor integrated circuit device can be protected from overcurrent.

【0056】(7)本発明の半導体集積回路装置によれ
ば、前述した(1)〜(6)により、特殊な保護回路を
用いることなく、配線層に過電流に対する保護回路を形
成することができるので、レイアウトの自由度を増大す
ることができると共に、製造工程を簡便化でき、安価
で、コンパクトな半導体集積回路装置が実現できる。
(7) According to the semiconductor integrated circuit device of the present invention, according to the above (1) to (6), a protection circuit against an overcurrent can be formed in the wiring layer without using a special protection circuit. Therefore, the degree of freedom in layout can be increased, the manufacturing process can be simplified, and an inexpensive and compact semiconductor integrated circuit device can be realized.

【図面の簡単な説明】[Brief description of drawings]

【図1】(a)は本発明の実施例1である半導体集積回
路装置の横断面図、(b)は本発明の第1実施例である
配線層の縦断面図である。
FIG. 1A is a horizontal sectional view of a semiconductor integrated circuit device according to a first embodiment of the present invention, and FIG. 1B is a vertical sectional view of a wiring layer according to a first embodiment of the present invention.

【図2】(a)は本発明の実施例2である半導体集積回
路装置の横断面図、(b)は本発明の第2実施例である
配線層の縦断面図である。
2A is a horizontal cross-sectional view of a semiconductor integrated circuit device according to a second embodiment of the present invention, and FIG. 2B is a vertical cross-sectional view of a wiring layer according to a second embodiment of the present invention.

【図3】(a)は本発明の実施例3である半導体集積回
路装置の横断面図、(b)は本発明の第3実施例である
配線層の縦断面図である。
3A is a cross-sectional view of a semiconductor integrated circuit device according to a third embodiment of the present invention, and FIG. 3B is a vertical cross-sectional view of a wiring layer according to a third embodiment of the present invention.

【図4】(a)は本発明の実施例4である半導体集積回
路装置の横断面図、(b)は本発明の第4実施例である
配線層の縦断面図である。
FIG. 4A is a horizontal sectional view of a semiconductor integrated circuit device according to a fourth embodiment of the present invention, and FIG. 4B is a vertical sectional view of a wiring layer according to a fourth embodiment of the present invention.

【図5】(a)は本発明の実施例5である半導体集積回
路装置の横断面図、(b)は本発明の第5実施例である
配線層の縦断面図である。
5A is a horizontal cross-sectional view of a semiconductor integrated circuit device according to a fifth embodiment of the present invention, and FIG. 5B is a vertical cross-sectional view of a wiring layer according to a fifth embodiment of the present invention.

【図6】(a)は本発明の実施例6である半導体集積回
路装置の横断面図、(b)は本発明の第6実施例である
配線層の縦断面図である。
6A is a horizontal sectional view of a semiconductor integrated circuit device according to a sixth embodiment of the present invention, and FIG. 6B is a vertical sectional view of a wiring layer according to a sixth embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1 シリコン基板 2 シリコン酸化膜 3,6,8,9,10,12 配線層 4,11 常伝導体 5 超伝導体 7 絶縁体 1 Silicon substrate 2 Silicon oxide film 3,6,8,9,10,12 Wiring layer 4,11 Normal conductor 5 Superconductor 7 Insulator

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】 半導体基板上に常伝導体および超伝導体
からなる配線層が形成されたことを特徴とする半導体集
積回路装置。
1. A semiconductor integrated circuit device having a wiring layer made of a normal conductor and a superconductor formed on a semiconductor substrate.
【請求項2】 半導体基板上に超伝導体からなる配線層
が形成され、前記配線層の電流経路が絶縁体により絶縁
されたことを特徴とする半導体集積回路装置。
2. A semiconductor integrated circuit device, wherein a wiring layer made of a superconductor is formed on a semiconductor substrate, and a current path of the wiring layer is insulated by an insulator.
【請求項3】 前記超伝導体の上面および下面の少なく
とも一方に常伝導体が形成されたことを特徴とする請求
項2記載の半導体集積回路装置。
3. The semiconductor integrated circuit device according to claim 2, wherein a normal conductor is formed on at least one of an upper surface and a lower surface of the superconductor.
【請求項4】 半導体基板上に超伝導体からなる配線層
が形成され、前記配線層の電流経路が絶縁体により一部
絶縁されたことを特徴とする半導体集積回路装置。
4. A semiconductor integrated circuit device, wherein a wiring layer made of a superconductor is formed on a semiconductor substrate, and a current path of the wiring layer is partially insulated by an insulator.
【請求項5】 半導体基板上に常伝導体および超伝導体
からなる配線層が形成され、前記配線層の電流経路を絶
縁する絶縁体が前記常伝導体と前記超伝導体との界面に
形成されたことを特徴とする半導体集積回路装置。
5. A wiring layer made of a normal conductor and a superconductor is formed on a semiconductor substrate, and an insulator for insulating a current path of the wiring layer is formed at an interface between the normal conductor and the superconductor. A semiconductor integrated circuit device characterized by the above.
【請求項6】 半導体基板上に配線層が形成され、前記
配線層は第1の常伝導体および超伝導体と、前記第1の
常伝導体と前記超伝導体との界面に形成され電流経路を
絶縁する絶縁体と、前記第1の常伝導体および前記超伝
導体の上面および下面の少なくとも一方に形成された第
2の常伝導体とからなることを特徴とする半導体集積回
路装置。
6. A wiring layer is formed on a semiconductor substrate, and the wiring layer is formed on a first normal conductor and a superconductor, and at an interface between the first normal conductor and the superconductor. A semiconductor integrated circuit device comprising: an insulator that insulates a path; and a second normal conductor formed on at least one of an upper surface and a lower surface of the first normal conductor and the superconductor.
JP7176992A 1995-07-13 1995-07-13 Semiconductor integrated circuit device Pending JPH0927496A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7176992A JPH0927496A (en) 1995-07-13 1995-07-13 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7176992A JPH0927496A (en) 1995-07-13 1995-07-13 Semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPH0927496A true JPH0927496A (en) 1997-01-28

Family

ID=16023297

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7176992A Pending JPH0927496A (en) 1995-07-13 1995-07-13 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPH0927496A (en)

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