JPH0927493A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance the leakage characteristics by suppressing the production of hillocks in the surface part of a wiring pattern made of aluminum or an aluminum alloy in a semiconductor device. SOLUTION: An insulating film 2 of a first layer is deposited on a semiconductor substrate 1 by normal pressure CVD. Next, on the insulating film 2 of the first layer an aluminum alloy film 3A of the first layer is deposited by PVD, and after that a wiring pattern 3B of the first layer is formed by etching. Next, ions 4 of a substance harder than time aluminum alloy are implanted into the wiring pattern 3B of the first layer by ion implantation, and a hard layer is formed in line surface part of the wiring pattern of the first layer. Next, an insulating film 6 of a second layer is formed by low pressure CVD to manufacture a semiconductor device.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device having a wiring layer made of aluminum or aluminum alloy.

[0002]

2. Description of the Related Art In recent years, aluminum or aluminum alloys have come to be used for wiring of semiconductor integrated circuits due to higher density of semiconductor devices.

An example of a conventional method of manufacturing a semiconductor device in which wiring of an integrated circuit is formed of aluminum or aluminum alloy will be described below with reference to the drawings.

8A to 8E are schematic process diagrams of a conventional method for manufacturing a semiconductor device. In FIG. 8, 11 is a semiconductor substrate, 12 is a first-layer insulating film formed on the upper surface of the semiconductor substrate 11, 13A is a first-layer aluminum film that forms a wiring pattern, and 13B is a first-layer aluminum film 1.
3A, the first layer wiring pattern, 14 is the second layer insulating film formed on the first layer wiring pattern 13B, and 15 is the second layer by the same method as the first layer wiring pattern 13B. 2 is a second layer wiring pattern formed on the insulating film 14 of FIG.

A method of manufacturing the semiconductor device having the above structure will be described below.

First, as shown in FIG. 8A, the insulating film 1 of the first layer is formed on the upper surface of the semiconductor substrate 11 by the atmospheric pressure CVD method or the like.
2 is deposited.

Next, as shown in FIG. 8B, a first-layer aluminum film 13A is deposited on the upper surface of the first-layer insulating film 12 by the PVD method or the like.

Next, as shown in FIG. 8C, the first layer aluminum film 13A is subjected to photolithography and etching to form a first layer wiring pattern 13B.

Next, as shown in FIG. 8D, a second layer insulation film such as a TEOS film is formed on the upper surfaces of the first layer wiring pattern 13B and the first layer insulation film 12 by a high temperature CVD method or the like. The film 14 is deposited, and the upper surface of the second insulating film 14 is flattened by a flattening etchback process.

Next, as shown in FIG.
A second layer wiring pattern 15 is formed on the upper surface of the second layer insulating film 14 by the same method as shown in FIGS. 8B and 8C.

[0011]

However, in the conventional method for manufacturing a semiconductor device described above, in the step shown in FIG. 8D, the wiring pattern 13B of the first layer and the insulating film 12 of the first layer are formed on the upper surface of the wiring pattern 13B. A two-layer insulating film 14 is formed, and the second
A high temperature CVD method and a heat treatment are required to flatten the upper surface of the insulating film 14 of the layer. Because of the heat treatment at about 450 ° C. at this time, as indicated by reference numeral 13b in FIG.
Protrusions called hillocks are generated due to thermal stress in the wiring pattern 13B of the first layer, and the insulating film 14 of the second layer grows while generating cracks. This second layer insulating film 14
Is often formed of a TEOS film, but TE
Since the OS film has a high hygroscopic property, the moisture penetrating through the cracks corrodes the wiring pattern 13B of the first layer, increases the leak current between the different layers of the first layer and the second layer, and further causes hillocks. There is a problem that 13b causes a short circuit between the wirings.

Hereinafter, the leakage current generated between the wiring patterns of the first layer and the second layer is referred to as the leakage current between different layers, whereas the leakage current generated between the wiring patterns in the first layer. Will be referred to as a leak current in the same layer.

In order to avoid the above-mentioned problems, it is possible to form the second insulating film 14 by the low temperature CVD method instead of the high temperature heat treatment method. However, the low temperature CV
According to the D method, the film forming conditions are difficult, and since the temperature is low, the reliability of the film quality is not sufficient. Further, forming the refractory metal film for forming the second layer wiring pattern 15 above the first layer wiring pattern 13B causes incomplete adhesion or corrosion due to a multilayer film. Occur,
A new problem arises that the etching conditions become difficult.

Therefore, the present invention solves the above-mentioned conventional problems. By suppressing the generation of hillocks, short-circuits between wiring patterns are prevented, leak characteristics between different layers are improved, and reliability is further improved. An improved method of manufacturing a semiconductor device is provided.

[0015]

In order to achieve the above object, the present invention provides a wiring pattern made of aluminum or an aluminum alloy by implanting ions of a substance having a hardness higher than that of aluminum or the aluminum alloy. A hard layer is formed on the surface of the pattern.

Specifically, a solution means taken by the invention of claim 1 is a method of manufacturing a semiconductor device, comprising a first step of forming an insulating film of a first layer on a semiconductor substrate, and insulation of the first layer. A second step of depositing a metal film made of aluminum or an aluminum alloy on the film, a third step of etching the metal film to form a wiring pattern, and a hardness of the wiring pattern higher than that of aluminum or an aluminum alloy. Of forming a hard layer on the surface of the wiring pattern by injecting ions of a substance having a large amount, and a fifth step of forming a second insulating film on the wiring pattern on which the hard layer is formed.
And the process.

With the above structure, since the ions of a substance having a hardness higher than that of aluminum or an aluminum alloy are injected into the wiring pattern made of aluminum or an aluminum alloy, a hard layer is formed on the surface portion of the wiring pattern.

According to a second aspect of the present invention, in the structure of the first aspect, a step of removing the surface layer of the first insulating film by etching is provided between the fourth step and the fifth step. The configuration that it is further provided is added.

With the above structure, since the surface layer of the first insulating film is removed by etching, the insulating property of the first insulating film is improved.

According to a third aspect of the present invention, in the structure of the first aspect, the hard layer of the wiring pattern and the surface layer of the insulating film of the first layer are provided between the fourth step and the fifth step. Is added to the structure in which the step of oxidizing or nitriding is further provided.

With the above structure, since the hard layer on the surface of the wiring pattern is oxidized or nitrided, the hard layer on the surface of the wiring pattern is further hardened. Further, since the surface layer of the first insulating film is oxidized or nitrided, the insulating property of the surface layer of the first insulating film is improved.

The invention of claim 4 is the addition of the structure of claim 1, wherein the ions in the fourth step are carbon ions.

With the above structure, since the ions of the substance to be injected into the wiring pattern are carbon ions, the hard layer on the surface of the wiring pattern is extremely hardened, and the insulating property of the first insulating film is impaired. I can't.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below with reference to the drawings.

1A to 1E show schematic steps of a method of manufacturing a semiconductor device according to the first embodiment of the present invention. In FIG. 1, 1 is a semiconductor substrate and 2 is a semiconductor substrate 1.
A first-layer insulating film formed on the upper surface of the substrate, 3A is a first-layer aluminum alloy film for forming wiring of an integrated circuit, and 3B is a first-layer wiring pattern formed of the first-layer aluminum alloy film 3A. Reference numeral 4 denotes an ion of a substance having a hardness higher than that of the aluminum alloy injected to harden the surface portion of the wiring pattern 3B of the first layer, and 6 denotes a second ion formed on the wiring pattern 3B of the first layer. Layer is an insulating film.

A method of manufacturing the semiconductor device having the above structure will be described below.

First, as shown in FIG. 1A, a first insulating film 2 made of a BPSG film containing boron and phosphorus is deposited on the upper surface of a semiconductor substrate 1 by atmospheric pressure CVD.

Next, as shown in FIG. 1B, a first aluminum alloy film 3A of aluminum and copper (0.5%) is deposited on the upper surface of the first insulating film 2 by the PVD method or the like.

Next, as shown in FIG. 1C, a first layer wiring pattern 3B is formed from the first layer aluminum alloy film 3A by photolithography and etching.

Next, as shown in FIG. 1D, ions 4 of a substance having a hardness higher than that of the aluminum alloy are used for the wiring pattern 3B of the first layer and the insulating film 2 of the first layer by the ion implantation method. Is injected to form a hard layer on the surface of the first-layer wiring pattern 3B. The ions of a substance having a hardness higher than that of the aluminum alloy mentioned here are, for example, tungsten ions.

Next, as shown in FIG. 1 (e), a reduced pressure is applied to the upper surface of the insulating film 2 of the first layer in which the ions 4 are implanted and the wiring pattern 3B of the first layer whose surface is hardened. CV
A second layer insulating film 6 such as a TEOS film is deposited by the D method.

According to the first embodiment, since the ions 4 of the substance having a hardness higher than that of the aluminum alloy are implanted into the wiring pattern 3B of the first layer, the wiring pattern 3B of the first layer is formed.
Since the surface portion of the first layer is hardened, it is possible to remove the first
Hillocks generated from the layer wiring pattern 3B can be suppressed.

A second embodiment of the present invention will be described below with reference to the drawings.

2A to 2C and 3A to 3C.
(C) shows the schematic process of the manufacturing method of the semiconductor device concerning the 2nd Embodiment of this invention. Since the steps shown in FIGS. 2A to 2C and FIG. 3A are the same as those in the first embodiment, the same reference numerals are given and omitted.

As shown in FIG. 3B, the insulating film 2 of the first layer is etched by dry etching using a fluorine-based gas, and is harder than the aluminum alloy of the surface layer of the insulating film 2 of the first layer. Ion 4 of a substance having a large

Next, as shown in FIG.
A second-layer insulating film 6 such as a TEOS film is deposited by the low pressure CVD method on the upper surface of the first-layer insulating film 2 from which is removed and the first-layer wiring pattern 3B whose surface is hardened.

According to the second embodiment, in addition to the first embodiment, the ions 4 in the surface layer of the first insulating film 2 are removed, so that the leak current in the same layer is reduced.

The third embodiment of the present invention will be described below with reference to the drawings.

4A to 4C and 5A to 5C.
(C) shows the schematic process of the manufacturing method of the semiconductor device which concerns on the 3rd Embodiment of this invention. In FIG. 5B,
Reference numeral 4a is a hard layer having an insulating property formed of an oxide layer or a nitride layer, which is formed by oxidizing or nitriding ions of a substance having a hardness higher than that of the aluminum alloy. FIG. 4 (a)
The steps shown in (c) to (c) of FIG. 5 are the same as those of the first embodiment, and therefore the same reference numerals are given and the description thereof is omitted.

As shown in FIG. 5B, the hard layer having the insulating property is formed by oxidizing or nitriding the surface layer of the first insulating film 2 and the hard layer of the first wiring pattern 3B by the sputtering method. Form the layer 4a.

Next, as shown in FIG. 5C, a low pressure CVD method is applied to the upper surfaces of the first insulating film 2 and the first wiring pattern 3B on which the hard layer 4a having an insulating property is formed. A second insulating film 6 such as a TEOS film is deposited.

According to the third embodiment, since the hard layer of the first wiring pattern 3B is oxidized or nitrided by the sputtering method, the hard layer is further hardened. Therefore, the second layer insulating film 6 is subjected to the high temperature heat treatment. It is possible to further suppress the hillock generated from the wiring pattern 3B of the first layer during the flattening and etching back. Further, since the hard layer on the surface portion of the wiring pattern 3B of the first layer and the surface layer 4a of the insulating film 2 of the first layer both serve as an insulating layer, the leak current in the same layer and the leak current between different layers are It will decrease further.

The fourth embodiment of the present invention will be described below with reference to the drawings.

6A to 6C and 7A to 7C.
(C) shows the schematic process of the manufacturing method of the semiconductor device concerning the 4th Embodiment of this invention. In FIG. 7 (a),
Reference numeral 5 is a carbon ion injected to harden the surface portion of the wiring pattern 3B of the first layer, and in FIG. 7B, 5a is an aluminum carbide layer generated by reacting with aluminum. The steps shown in FIGS. 6A to 6C are
Since it is the same as that of the first embodiment, the same reference numerals are given and description thereof is omitted.

As shown in FIG. 7A, carbon ions 5 are implanted into the first-layer wiring pattern 3B and the first-layer insulating film 2 by an ion implantation method.

Next, as shown in FIG. 7B, the implanted carbon ions 5 react with the wiring pattern 3B of the first layer to form an aluminum carbide layer 5a.

Next, as shown in FIG. 7 (c), on the upper surface of the first layer wiring pattern 3B in which the first layer insulating film 2 into which carbon ions are implanted and the hard layer in the surface portion are carbonized, A second layer insulating film 6 such as a TEOS film is formed by the low pressure CVD method.

According to the fourth embodiment, the carbon ions 5 injected into the surface portion of the wiring pattern 3B of the first layer react with aluminum and are very hard to form the aluminum carbide layer 5a.
When the second layer insulating film 6 is flattened and etched by a high temperature heat treatment to form the first layer, the first layer wiring pattern 3B is formed.
Therefore, it is possible to further suppress the generation of hillocks, so that the cracks generated in the second insulating film 6 are minimized and the leak current between different layers is extremely reduced. Further, since the first layer insulating film 2 does not affect the leak characteristic in the same layer even when the carbon ions 5 are implanted, the dry etching step and the sputtering step are unnecessary,
The number of steps is reduced and the throughput of the semiconductor device is improved.
Therefore, the reliability is improved, and the manufacturing cost of the semiconductor device can be reduced.

[0049]

As described above, according to the method of manufacturing a semiconductor device of the first aspect of the present invention, since the hard layer is formed on the surface portion of the wiring pattern, when the insulating film is flattened by heat treatment, Since hillocks are prevented from being generated from the wiring pattern, a short circuit between the wirings can be prevented and the number of cracks can be reduced. Thus, according to the present invention,
Since the occurrence of cracks is reduced, the leak current between different layers can be reduced.

According to the semiconductor device manufacturing method of the second aspect of the present invention, the insulating property of the surface portion of the insulating film is improved.
Leakage current in the same layer can be reduced.

According to the semiconductor device manufacturing method of the third aspect of the present invention, since the hard layer of the wiring pattern is further hardened, hillocks are generated from the wiring pattern when the insulating film is planarized by heat treatment. Is further suppressed, so
It further prevents short circuits between wires and further reduces the occurrence of cracks. Therefore, according to the present invention, since the occurrence of cracks is further reduced, the leak current between different layers can be further reduced. In addition, since a hard layer having an insulating property is formed on the surface of the wiring pattern and the insulating property of the surface of the insulating film can be maintained without performing an etching process, it is possible to reduce the leak current in the same layer. it can.

According to the method of manufacturing a semiconductor device of the fourth aspect, since the hard layer of the wiring pattern is extremely hardened, hillocks are generated from the wiring pattern when the insulating film is planarized by heat treatment. Is minimized, so that a short circuit between wirings can be further prevented and the occurrence of cracks can be further reduced. Therefore, according to the present invention, since the occurrence of cracks is extremely reduced, the leak current between different layers can be minimized. Further, since the carbon ions do not affect the leak characteristic of the insulating film, the dry etching step of claim 2 and the sputtering step of claim 3 are unnecessary.

[Brief description of drawings]

1A to 1E are diagrams showing schematic steps of a method for manufacturing a semiconductor device according to a first embodiment of the present invention.

2A to 2C are diagrams showing a first half of a schematic process of a method for manufacturing a semiconductor device according to a second embodiment of the present invention.

3 (a) to 3 (c) are diagrams showing a latter half of schematic steps of the method for manufacturing a semiconductor device according to the second embodiment of the present invention.

FIG. 4A to FIG. 4C are diagrams showing the first half of the schematic steps of the method for manufacturing a semiconductor device according to the third embodiment of the present invention.

5A to 5C are diagrams showing a second half of the schematic steps of the method for manufacturing a semiconductor device according to the third embodiment of the present invention.

FIGS. 6A to 6C are diagrams showing the first half of the schematic steps of the method for manufacturing a semiconductor device according to the fourth embodiment of the present invention.

FIG. 7A to FIG. 7C are diagrams showing the latter half of the schematic steps of the method for manufacturing a semiconductor device according to the fourth embodiment of the present invention.

FIG. 8A to FIG. 8E are diagrams showing schematic steps of a conventional method for manufacturing a semiconductor device.

FIG. 9 is a diagram showing a problem in a conventional method of manufacturing a semiconductor device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Insulating film of 1st layer 3A Aluminum alloy film of 1st layer 3B Wiring pattern of 1st layer 4 Ion of a substance having a higher degree than aluminum alloy 4a Hard layer having insulating property 5 Carbon ion 5a Aluminum carbide layer 6 Second-Layer Insulating Film 11 Semiconductor Substrate 12 First-Layer Insulating Film 13A First-Layer Aluminum Film 13B First-Layer Wiring Pattern 13b Hillock 14 Second-Layer Insulating Film 15 Second Wiring Pattern

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[Procedure amendment]

[Submission date] November 20, 1995

[Procedure amendment 1]

[Document name to be amended] Drawing

[Correction target item name] Fig. 8

[Correction method] Change

[Correction contents]

[Figure 8]

Claims (4)

[Claims] 1. A first step of forming a first-layer insulating film on a semiconductor substrate, and a second step of depositing a metal film made of aluminum or an aluminum alloy film on the first-layer insulating film. And a third step of forming a wiring pattern by etching the metal film, and implanting ions of a substance having a hardness higher than that of aluminum or an aluminum alloy into the wiring pattern to form a hard layer on the surface portion of the wiring pattern. A method of manufacturing a semiconductor device, comprising: a fourth step of forming and a fifth step of forming an insulating film of a second layer on the wiring pattern on which the hard layer is formed. 2. The method according to claim 1, further comprising a step of removing a surface layer of the first insulating film by etching between the fourth step and the fifth step. A method of manufacturing a semiconductor device according to item 1. 3. The method further comprises a step of oxidizing or nitriding the hard layer of the wiring pattern and the surface layer of the insulating film of the first layer between the fourth step and the fifth step. The method for manufacturing a semiconductor device according to claim 1, further comprising: 4. The method of manufacturing a semiconductor device according to claim 1, wherein the ions in the fourth step are carbon ions.