JPH09274055A - Semiconductor tester and probe unit and manufacture of semiconductor tester - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor tester, which can maintain an electric contact state under the high-temperature environment of a wafer burn-in test excellently and a probe unit for the tester. SOLUTION: A probe unit 10 is formed in correspondence with each semiconductor chip 8 of a semiconductor wafer 2. The units are combined, and a probe plate 11 is constituted. The wafer 2 is contained in a wafer holder 1. The probe plate 11 is applied and the wafer is pushed by a pouching unit 15. For the holder 1, material having the thermal expansion coefficient close to that of the wafer is used. A bump 20, which is the contact piece of the probe unit 10 corresponding as a chip unit, is contact with the electrode pad of each chip 8. Thus, the amount of the position deviation at every probe unit 10 becomes about several μm when exposed to the high temperature of about 125 deg.C. Therefore, the amount of the maximum position deviation can be made less than 1/10 comparison with the entire wafer, and the replacement of the probe unit 10 is simplified.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor test apparatus suitable for a burn-in test of a semiconductor device, a probe unit for the semiconductor test apparatus, and a manufacturing method thereof.

[0002]

2. Description of the Related Art In semiconductor devices such as integrated circuits,
As one of the semiconductor tests for ensuring the quality of products, there is a burn-in test, for example. This is because a thermal stress and an electrical stress are simultaneously applied to the semiconductor device by applying a power supply voltage of about 1.2 times the standard voltage in a high temperature atmosphere of about 75 ° C. to 150 ° C., for example. In this state, it is determined whether or not the predetermined level is maintained even if the state is maintained for the predetermined time.

In such a semiconductor test, conventionally, a semiconductor wafer on which a large number of semiconductor chips are formed is cut and divided into individual semiconductor chips, which are sealed in a resin package or TAB (tape automated bondin).
It was generally done in the final product state with bare chip mounting such as g).

However, in order to perform a semiconductor test with the semiconductor chip mounted in a package or the like in this way, it is necessary to provide a test device or a package member for each semiconductor chip, and a test for one semiconductor chip is required. There is a problem that the cost for Further, regarding a semiconductor chip that has been determined to be a defective product after performing the semiconductor test in this way, there is a problem that the cost for mounting becomes wasteful.

Further, in recent years, with the improvement of the bare chip mounting technique described above, a semiconductor device in which a semiconductor chip is sealed in a resin package is not mounted on a printed circuit board, but is directly mounted on the ceramic substrate in a bare chip state. MCM (multi chip module) technology, which is designed to significantly reduce the mounting area by mounting the same on a device such as a computer, has been introduced.

In response to such a situation, it has been demanded to carry out a semiconductor test of each semiconductor chip in a wafer state or in a bare chip state, and if this can be realized, cost reduction can be realized. This will make a great contribution, and the above-mentioned problems will be resolved. Therefore, for example, JP-A-5-281260 or JP-A-6-29361 proposes carriers, sockets or probe substrates for performing a burn-in test in a wafer state or a chip state.

[0007]

However, the above-described burn-in test apparatus in a wafer state still has technical problems to be solved as shown in the following (1) to (4), The reality is that it has not reached the stage of practical use.

(1) It is difficult to obtain a uniform contact state over the entire surface of the wafer when the probe is brought into contact with the electrodes of each semiconductor chip on the wafer. (2) Due to the increase in the number of electrodes of the semiconductor chip and the increase in the arrangement density accompanying the improvement in the integration degree of the semiconductor device, a high alignment accuracy is required when the probe is brought into contact with the probe.

(3) It is difficult to obtain electrical contact with all electrodes of each semiconductor chip by independent wiring over the entire surface of the wafer. (4) Since the semiconductor wafer is exposed to a high temperature environment in the burn-in test, if there is a large difference in the coefficient of thermal expansion between the semiconductor wafer and the probe substrate, a positional shift occurs in the peripheral portion and the like, resulting in a poor electrical contact state. May occur.

With respect to the above technical problems, for example,
With regard to the configuration (1) for obtaining a uniform contact state, in order to make good electrical contact between each electrode pad of the semiconductor chip and the tip of the probe on the probe substrate side, a flexible contactor is used. Although proposed (for example, those having a membrane structure or the like, see JP-A-3-28652 and JP-A6-1).
60432, "Silicon Microprobing Array for Tes
ting and Burn-in ”； Proceeding of IEEE Multi-Chip
Module Conference, '94, etc.), the structure is complicated and the cost increases, and because it is assumed that a silicon wafer is used as the material of the probe substrate, independent wiring is derived from each electrode pad of the semiconductor chip. There is a problem that is difficult to do.

With respect to the above-described technical problems (2) and (3), the wiring pitch from the probe substrate for the burn-in test also depends on the arrangement pitch of the electrode pads of the semiconductor chips of the semiconductor wafer. Although it becomes difficult as the density becomes higher, a concretely feasible structure is not presented.

With respect to the problem of the positional deviation due to the difference in the coefficient of thermal expansion of (4), it has been proposed to use a substrate of the same material as the semiconductor wafer (such as a silicon substrate) as the material of the probe substrate.が (“A cost-effecti
ve wafer-level burn-in technology ”Proc. Int. Co
nf. on MCM '94, etc.), in this case, it is difficult to make electrical contact to the electrode pads of each semiconductor chip by using independent wiring, so the technical problem shown in (3) above. Remains, and the outer leads are led out from the periphery of the probe board by the common wiring.

Further, in the conventional case, when a defect or a damaged portion occurs in a part of the probe substrate, it is difficult to repair the defective portion, so that the probe substrate itself is eventually replaced. This is a cause of problems that increase the test cost.

To solve the above problems, the present invention can perform a semiconductor test on a plurality of semiconductor chips formed on a semiconductor wafer in a wafer state, and even in that case, the semiconductor test can be performed under a high temperature environment. And a probe unit used in the semiconductor test apparatus and a method for manufacturing the same.

[0015]

According to the invention of claim 1, since a plurality of probe units corresponding to each semiconductor chip are combined to form a probe plate, the adverse effect of thermal expansion as a whole is exerted on the entire wafer. Therefore, it is possible to prevent the positional deviation between the semiconductor chip and the contact of the probe unit even under a high temperature environment, and to maintain a good electrical contact state.

According to the second aspect of the present invention, since the probe units can be individually replaced, it is only necessary to replace the target probe unit at the time of failure, so that the repair cost can be reduced.

According to the third aspect of the present invention, the contact unit of each probe unit provided on the probe plate with respect to the semiconductor wafer housed in the wafer holder is brought into contact with the electrode pad of the semiconductor chip by the pressing unit. Since it is fixed in a pressed state, it becomes possible to locate a good electrical contact state.

According to the sixth aspect of the present invention, the contactor is arranged at a position corresponding to the plurality of electrode pads provided on the semiconductor chip to enable electrical contact, and the lead wire is provided from the contactor. Since the connecting electrode for leading out can be wider than the space between the contacts, it is easy to perform connecting work such as soldering the lead wire to the outside.

According to the seventh aspect of the present invention, since the other portions of the contactor other than the tip end portion are covered with the elastic resin surface layer, the contact state can be flexibly contacted with the electrode pad of the semiconductor chip. Can hold. Further, according to the invention of claim 9, the groove portion formed around each contact increases the flexibility of the contact portion and increases the degree of freedom.

According to the eleventh and twelfth aspects of the present invention, the contacting position of the pressing portion of the pressing unit is defined by the dam portion, so that the alignment work can be facilitated and the positional deviation can be prevented.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION A first embodiment in which the present invention is applied to a semiconductor wafer burn-in test apparatus will be described below with reference to FIGS. In the burn-in test, the semiconductor wafer is subjected to the determination of the electrical performance of each semiconductor chip in a state where the semiconductor chip is not separated and kept in a high temperature environment of, for example, about 125 ° C., which will be described below. The one used in such a burn-in test.

In FIG. 1 showing a vertical side surface of the overall structure and FIG. 2 showing an exploded perspective view, a wafer holder 1 is a rectangular plate-like member, and a silicon wafer is used as a semiconductor wafer 2 as a device under test. Assuming a case, it is a material having a thermal expansion coefficient close to that of silicon (3.5 × 10 ⁻⁶ / ° C.), such as Kovar or 42.
It is made of alloy, AlN (aluminum nitride), molybdenum (Mo), or the like. A circular wafer accommodating portion 3 corresponding to the size of the semiconductor wafer 2 is formed on the upper surface side of the wafer holder 1. Also,
As shown in FIG. 3, the wafer holder 1 is provided with positioning pins 4 and fixing screw holes 5 at the four corners of the upper surface, and the position when the semiconductor wafer 2 is housed in the center of each side of the upper surface. A matching pattern 6 is attached.

The semiconductor wafer 2 is mounted on the wafer holder 1
When the wafer is accommodated in the wafer accommodating portion 3, the semiconductor wafer 2 is accommodated with a buffer sheet 7 having the same size and elasticity interposed therebetween. Further, in such a state that the semiconductor wafer 2 is accommodated, the depth dimension thereof is set so that the upper surface of the semiconductor wafer 1 is located at a position lower than the surface of the opening of the wafer accommodating portion 3.

A large number of semiconductor chips 8 are formed on the semiconductor wafer 2.
Are formed in an undivided state, and each of these semiconductor chips 8 is provided with an integrated circuit in which semiconductor elements are formed, and electrode pads (for example, 100 μm square) for exchanging signals with the outside are provided. Rectangular shape 9) are formed in large numbers (several tens to several hundreds). Note that such electrode pads 9 are arranged along the outer peripheral portion of the semiconductor chip 8, for example, and some of them have a size of about 100 μm square and are arranged at a pitch of about 200 μm.

Then, with the semiconductor wafer 2 accommodated in the wafer accommodating portion 3 of the wafer holder 1, each of the semiconductor chips 8 provided on the upper surface side is electrically contacted with the electrode pad 9 on the surface thereof. Multiple probe units 1
0 is arranged (in FIG. 2, it is shown enlarged on the right side, but the details of the configuration will be described later).

These probe units 10 are arranged side by side to form a probe plate 11 so as to be in the same arrangement as the semiconductor chips 8 formed on the semiconductor wafer 2.
This probe plate 11 is mounted on the wafer holder 1 with the outer peripheral frame 12 for positioning,
It is adapted to be mounted in the opening 12a of the. The outer peripheral frame 12 has fitting holes 13 at four corners corresponding to the positioning pins 4 when the wafer holder 1 is mounted.
And a screw hole 14 for fixing is formed.

The pressing unit 15 includes the outer peripheral frame 12
Is fixed to the wafer holder 1 using screws 16 and springs 16a from above. As shown in FIGS. 4 and 5, screw holes 17 are provided at positions corresponding to the screw holes 5 of the wafer holder 1 at the four corners. Has been formed. Further, a pressing portion 18 is formed on the central portion side of the pressing unit 15 so as to press each probe unit 10 from above corresponding to the shape of the probe plate 11. In addition, an opening 18 a for leading the lead wire 10 a led out to the back surface (upper side) of the probe unit 10 to the outside is formed in the holding portion 18 in correspondence with each probe unit 10. . The peripheral frame 12 and the pressing unit 15 have the same thermal expansion coefficient (3.5) as that of the wafer holder 1, assuming that a silicon wafer is used as the semiconductor wafer 2 as the device under test.
It is formed of a material having a thermal expansion coefficient close to × 10 ⁻⁶ / ° C., for example, Kovar, 42 alloy, AlN, molybdenum, or the like.

Now, the structure of the probe unit 10 will be described in detail with reference to FIGS. 6 to 10. FIG. 6 shows a probe unit 10, which has a structure in which, for example, a multilayer wiring board 19 of three layers is used as a substrate. The material of the multilayer wiring board 19 is, for example, a low temperature firing substrate (heat It is effective to use one having a value close to the thermal expansion coefficient of silicon, such as an expansion coefficient of 5.5 × 10 −6 / ° C.). On the lower surface side of the multilayer wiring board 19, that is, the surface facing the semiconductor chip 8,
Au (gold) bumps 2 as contacts are provided at respective positions corresponding to the arrangement state of the electrode pads 9 of the semiconductor chip 8.
0 is formed (see FIG. 8A).

On the upper surface side of the multilayer wiring board 19, that is, the surface to which the lead wire 10a for connecting to the outside is connected, the connection electrodes 21 are formed by the conductor pattern by the number corresponding to the bumps 20. , Their placement interval is
The bumps 20 are arranged and formed with a predetermined space therebetween so as to be wider than the space between the bumps 20. And on this side,
The positioning dam portion 22 is formed in a rectangular shape so that positioning can be performed when the pressing portion 18 of the pressing unit 15 is brought into contact with the pressing unit 18. The connecting electrode 21 is provided inside the positioning dam portion 22, and the holding portion 18 abuts on the outer peripheral side so as to be pressed downward (see FIG. 7).

In this case, the above-mentioned multilayer wiring board 19 has three
A structure for stacking a plurality of wiring boards 19a to 19c and for obtaining the above-described arrangement of the bump 20 and the connecting electrode 21 will be described with reference to FIG. That is, for example, when 36 electrode pads 9 of the semiconductor chip 8 are arranged in the peripheral portion, 36 bumps 20 are provided on the wiring substrate 19a on the lower layer side at positions corresponding thereto. In this case, the bump 20 can be formed by various basic forming methods described later.

Now, for example, as compared with the case where the bumps 20 are formed in a pattern in which 36 connection electrodes 21 are evenly arranged to the inside, as shown in FIG. The connection electrodes 21 are formed in a 6 × 6 array so that 36 electrodes are formed. Then, by the wiring board 19b of the intermediate layer, the conductor pattern 23 is formed so as to electrically connect each bump 20 and the corresponding connection electrode 21 so as to be electrically connected. As a result, the connection electrodes 21 can be arranged at an interval wider than the arrangement interval of the bumps 20, and when connecting the lead wires 10a, work such as soldering is facilitated.

Next, a method of forming the above-mentioned bumps 20 will be described with reference to FIGS. 9 and 10. First, the first method will be described with reference to FIG. The first method is composed of the following first to fourth steps and groove forming step. First step (see FIG. 9A) The bumps 2 are formed on the wiring board 19a which is a layer for forming the bumps 20 of the multilayer wiring board 19.
The conductor pattern 24 is formed so as to correspond to the arrangement position of 0. Second step (see FIG. 11A) A ball bump (stud bump) 25 with a wire is formed on the conductor pattern 24 portion.
It is formed by a u (gold) bonding wire. For example,
After bonding by the ball bonding technique, the wire 2 from the bonding portion 25a to a predetermined length.
Cut leaving 5b.

Third step (see FIG. 9B) The surface of the wiring board 19a is coated with a flexible resin layer 26 to the extent that the tip of the wire 25b of the ball bump 25 with wire is exposed. . As the resin in this case, for example,
Polyimide, high-molecular thermoplastic resin, or the like is suitable, and it is preferable that the undiluted resin solution be applied by means such as dispensing so as to prevent the wire 25b from bending and falling during coating.

Fourth step (see FIG. 6C) Resin layer 2
The tip portion of the wire 25b exposed from the above is pressed from above by a molding tool 27, for example, to form the bump 20. At this time, the molding tool 27 is heated if necessary. Groove forming step: After forming the bumps 20, a rectangular or circular groove portion 28 is formed by a laser processing machine or the like so as to surround each bump 20 (see FIG. 10). As a result, the bump 20 portion is easily bent, so that a structure having a high degree of freedom and flexibility can be obtained.

Next, the second method will be described. In the second method, the first to third steps in the first method are performed in the same manner, and the following fourth step is performed instead of the subsequent fourth step.

Step 4a ... (Refer to FIG. 3D) A probe tip member 29 is separately fixed to the tip of the wire-equipped ball bump 25 exposed from the resin layer 2 by a method such as pressure bonding. By doing so, the bump 20 is formed. In this case, Au (gold) is used as the probe tip member 29.
Method of forming bump 20 by pressure bonding using a ball bump, forming bump 20 by transfer using a conductive resin, or forming bump 20 by performing pressure bonding and solder reflow processing using a solder bump There is.

As the third method, the following fifth and sixth steps are added between the third step and the fourth or 4a step in the first or second method. It is a method of forming.

Fifth step (see FIG. 6E) Resin layer 2
After 6 is cured, its surface is polished by a mechanical polishing machine or the like to be flat, and the tip end of the wire 25b of the wire-equipped ball bump 25 is cut.
Perform processing to make the lengths uniform.

Sixth step (see FIG. 6F) Resin layer 2
Only the portion of 6 is removed by a predetermined thickness dimension by an etching process such as dry etching. At this time, the tip of the wire 25b of the ball bump with wire 25 remains without being removed, so that it is formed in an exposed state by a predetermined dimension. As a result, even if there are variations in the dimensions of the wire 25b when it is cut, it is possible to finally obtain a uniform length dimension.

Next, the operation of this embodiment will be described. First, the semiconductor wafer 2 to be subjected to the wafer burn-in test is housed in the wafer housing portion 3 of the wafer holder 1 with the buffer sheet 7 interposed therebetween. At this time, a mark for alignment (not shown) is attached to the semiconductor wafer 2, and the alignment mark and the alignment pattern 6 on the wafer holder 1 side.
The semiconductor wafer 2 is arranged at a fixed position by adjusting the positions of and under predetermined alignment conditions. in this case,
The alignment work may be performed by recognizing an image by photographing with a CCD camera or by visually recognizing it with an optical microscope.

On the other hand, in the outer peripheral frame 12, the probe plate 11 in which the probe units 10 have been assembled in advance is fixed to the holding unit 15 with the screw 16 via the spring 16a in a state of being mounted in the opening 12a. At this time, the leader lines 10 a led out from the back side of each probe unit 10 are respectively attached to the pressing units 15.
Of the pressing unit 1 is pulled out upward from the corresponding opening 18a of the pressing unit 15 by an adhesive resin or the like so that the probe unit 10 does not drop off.
In some cases, it may be detachably temporarily fixed to 8.

The probe plate 11 in such a state is fixed to the wafer holder 1 side with the screw 16. At this time, the probe plate 11 is provided with pins 4 for positioning the wafer holder 1.
Since the bumps 20 of each probe unit 10 are fixed in a state of being arranged at a predetermined position, the bumps 20 of each probe unit 10 are arranged at a position corresponding to the electrode pad 9 formed on each semiconductor chip 8 of the semiconductor wafer 2.

In this case, since the semiconductor wafer 2 is fixed in the wafer holder 1 by the buffer sheet 7 and the spring 16a, there is some variation in the warp of the wafer, the unevenness of the surface, or the height of the bump 20 of the probe unit 10. Even in such a case, a good contact state can be obtained over the entire surface of the semiconductor wafer 2. Further, since each probe unit 10 of the probe plate 11 has a structure in which it is individually pressed by the pressing portion 18 on the pressing unit 15 side, a stable contact state can be obtained.

Then, with the semiconductor wafer 2 mounted in this manner, the lead wire led out from the pressing unit 15 side is connected to the electric test apparatus side (not shown), and in this state, for example, in a high temperature tank at 125 ° C. Store and carry out burn-in test. In this case, an electric stress is applied to each semiconductor chip 8 from the electric test apparatus side under a predetermined condition, so that the semiconductor chip 8 is tested under both thermal stress and electric stress. Is carried out.

At this time, for example, assuming that the diameter of the semiconductor wafer 2 is 6 inches (diameter 152.4 mm) and silicon (coefficient of thermal expansion is 3.5 × 10 ⁻⁶ / ° C.), the influence of thermal expansion is assumed. Ask for. In the burn-in test, when the temperature is raised to 125 ° C, assuming that the room temperature is 25 ° C, 100
The temperature rises to ℃. Here, in the case where the probe plate 11 such as the conventional one is an integral body, when the same low temperature firing substrate (coefficient of thermal expansion of 5.5 × 10 ⁻⁶ / ° C.) as in this embodiment is used, the semiconductor wafer 2 of The positional displacement of the peripheral portion with respect to the central portion is about 15.2 μm.

On the other hand, when a plurality of probe units 10 are combined as in this embodiment, for example, the size of one probe unit 10 is 25 m.
Even when the angle is m-square, the amount of displacement is about 2.5 μm. Therefore, with the configuration according to the present embodiment, the degree of misalignment due to thermal expansion can be significantly reduced even when the temperature is raised to a high temperature. Since the amount of misalignment caused by the individual probe units 10 is thus small, it is possible to prevent a large misalignment from occurring in the outer probe units 10 by accumulating from the central portion to the outer extending portion.

As described above, the electrode pad 9 is 100 μm.
When the pitch is about 200 μm at m-square, the conventional structure causes a displacement of 15% or more at the maximum, and in some cases, the electrode pad 9 and the bump 20 cause poor contact. There are cases. In this respect, in the configuration of the present embodiment, since the range is about several percent, the contact state can be maintained without any trouble.

Further, the bump 20 of the probe unit 10 is formed with a flexible resin layer 24, and a groove 28 is formed around the bump 20 to increase the degree of freedom. By absorbing a slight amount of positional deviation, the contact state can be reliably maintained.

According to this embodiment, the following effects can be obtained.

First, since the probe plate 11 is constructed by synthesizing a plurality of probe units 10,
Even when exposed to a high-temperature environment such as a burn-in test, the amount of displacement of the bump 20 of the probe unit 10 with respect to each semiconductor chip 8 of the semiconductor wafer 2 is significantly reduced, which ensures the electrical contact state. Will be able to hold. In addition, since only the failed probe unit 10 can be replaced, the cost for repair can be reduced and the maintainability can be improved.

Second, the cushioning sheet 7 and the spring 1
Since the pressing unit 15 is attached to the wafer holder 1 in the state where the semiconductor wafer 2 is accommodated via 6a, each semiconductor chip 8 can be accommodated while absorbing the warp and unevenness of the semiconductor wafer 2.
The electric contact state with the electrode pad 9 can be surely obtained. Thirdly, the resin layer 26 is formed on the bump 20 of the probe unit 10, and the groove 2 is formed on the outer peripheral portion thereof.
Since 8 is formed, the degree of freedom is increased and the contact characteristics with the semiconductor chip 8 can be improved.

Fourth, the bump 2 of the probe unit 10
Since 0 is formed by any of the first to third forming methods, the size and the protruding amount of the bump 20 can be formed uniformly, and the electrical contact state can be improved. Fifth, since the distance between the connecting electrodes 21 can be made larger than the distance between the bumps 20 of the probe unit 10, the soldering work and the like can be facilitated when attaching the lead wires.

11 and 12 show a second embodiment of the present invention. The difference from the first embodiment is that the probe unit 10 is replaced with a probe unit 30 as shown in FIG. The pressing unit 15 is replaced by a pressing unit 31 as shown in cross section in FIG.

In the probe unit 30, a positioning step portion 32 is formed by a method such as polishing or etching in place of the positioning dam portion 22, and the outer periphery of the step portion 32 is pressed by the pressing portion 33 of the pressing unit 31. The lead wire (not shown) led out from the upper surface side of each probe unit 30 is drawn upward from the opening 33 a of the holding portion 33. The burn-in test can be carried out in the second embodiment as well as in the first embodiment.

13 to 15 show the third embodiment of the present invention. The difference from the first embodiment is that the probe unit 10 is replaced by a probe unit 34 as shown in FIG. Instead of the pressing unit 15, a pressing unit 35 as shown in cross section in FIG. 15 is provided.

In the probe unit 34, the connecting electrode 21 is formed on the outer peripheral side of the upper surface, and the positioning dam 36 is formed near the center by a method such as resin printing, and the inside of the dam 36. Is pressed by the pressing portion 37 of the pressing unit 35. Unlike the first embodiment, the pressing unit 35 is different from the pressing unit 37 in that the pressing unit 35 is configured so as to be bridged in the diagonal direction, as shown in FIG. The lead wire can be led out to the outside through the opening portion 37a formed in the pressing portion 37.

The probe unit 34 is the pressing unit 3
It is mounted such that the central portion of the upper surface is pressed by the pressing portion 37 of No. 5, and electrical contact between each electrode pad 9 of the semiconductor chip 8 and the bump 20 is obtained. At this time, since the semiconductor chip 8 is pressed from the central portion side, it is possible to flexibly deal with a good contact state even when the inclination is generated. The burn-in test can be carried out in the same manner as in the first embodiment.

FIGS. 16 and 17 show a fourth embodiment of the present invention, which is different from the third embodiment in that a probe unit 38 is provided in place of the probe unit 34. In place of the positioning dam portion 36, a positioning step portion 39 is formed in the probe unit 38 so as to lower the central portion by a method such as etching. As a result, the burn-in test can be carried out in substantially the same manner as in the third embodiment.

18 to 20 show a fifth embodiment of the present invention. The difference from the fourth embodiment is that a probe unit 40 is provided instead of the probe unit 38. Probe unit 40
18 differs from the probe unit 38 shown in FIG. 18 in that it has an upper layer portion 41 additionally formed so as to project upward from the central portion side, which corresponds to the probe unit 38 of the fourth embodiment. A large number of connection electrodes 42 are also formed on the side surface of 41.

In this case, the connection electrode 4 exposed on the side surface
As shown in FIG. 19, the upper layer 41 includes a multilayer wiring board 43 of, for example, three layers, which is used as a lower wiring board 43.
The conductor pattern 44 is formed so as to extend outward at the portion of the wiring board 43b of a or the intermediate layer, and the end portion is cut in the laminated state to form the conductor pattern 44.
It is formed by exposing. Further, the connection electrode 21 is formed on the upper wiring board 43c in the same manner as in the fourth embodiment.
And a positioning step 39 is formed in the center. The upper layer portion 41 is the original multilayer wiring board 19
It is fixed to the side of and has a two-stage configuration.

The pressing unit 45 is fixed to the wafer holder 1 side by pressing downward from the positioning step 39 at the center of each probe unit 40 by the pressing unit 46, and in this embodiment. According to this, the burn-in test can be performed in the same manner as in the first embodiment, and the probe unit 40 is provided with the upper layer portion 41 and the connection electrode 42 is also provided on the side surface side thereof, so that the electrode of the semiconductor chip 8 is formed. Even if the number of pads 9 is large, it is possible to cope with the situation.

21 and 22 show a sixth embodiment of the present invention. The difference from the fifth embodiment is that a probe unit 48 is provided instead of the probe unit 40 and a holding unit 46 is provided. Instead, the pressing unit 49 is provided.

The upper layer portion 50 of the probe unit 48 is provided with the connecting electrode 42 on the side surface portion, but not on the upper surface. On the other hand, the pressing unit 49 is formed in a concave shape so as to press the upper layer portion 50 of the probe unit 48 so as to cover the upper portion 50 by the pressing portion 51. Therefore, also by this, the burn-in test is performed in substantially the same manner as the fifth embodiment. Can be carried out.

FIG. 23 shows a seventh embodiment of the present invention. The difference from the first embodiment is that the burn-in test can be carried out for each semiconductor chip 8 of the semiconductor wafer 2. It has just been applied to the chip burn-in test equipment.

The chip holder 52 has a chip accommodating portion 53 having a rectangular recess, and the semiconductor chip 8 divided from the semiconductor wafer 1 is accommodated via a buffer sheet 54. There is. As the probe unit, for example, the probe unit 34 having the configuration of FIG. 14 shown in the third embodiment is used. This probe unit 3
The pressing unit 55 presses the inside of the positioning dam portion 36 from the back surface side (upper surface side) of 4 and is fixed by screws from the four corners.

As a result, the probe unit 34 can be used even when performing a burn-in test for each chip. In this embodiment, the probe unit 34
The probe unit 1 used in each of the above examples
Any of 0, 30, 34, 38, 40 and 48 can be used.

The present invention is not limited to the above embodiment, but can be modified or expanded as follows. A probe unit corresponding to each semiconductor chip may be used, or a probe unit corresponding to a plurality of semiconductor chips may be used. The position of the groove 28 is determined by the individual bumps 20.
You may form independently so that a part may be enclosed. After the semiconductor wafer 2 is housed in the wafer holder 1, the outer peripheral frame may be mounted first, and then the probe units may be mounted individually. The pressing unit may be formed of stainless steel, a resin having high hardness, or the like other than the above.

[Brief description of drawings]

FIG. 1 is a vertical sectional side view of the overall configuration showing a first embodiment of the present invention.

FIG. 2 is an exploded perspective view

FIG. 3 is a top view of a wafer holder and a wafer.

FIG. 4 is a top view of the pressing unit.

FIG. 5 is a vertical sectional side view of the pressing unit.

FIG. 6 is an external perspective view of a probe unit.

FIG. 7 is a vertical cross-sectional side view of the holding unit shown with the probe unit held down.

FIG. 8 is a vertical cross-sectional side view of the probe unit and a plan view of each wiring board layer forming the probe unit.

FIG. 9 is a vertical cross-sectional side view of each step for explaining the first to third methods of forming the bumps of the probe unit.

FIG. 10 is an external perspective view of the probe unit shown from the bump side.

FIG. 11 is a view corresponding to FIG. 7 showing a second embodiment of the present invention.

FIG. 12 is a diagram corresponding to FIG. 6;

FIG. 13 is a plan view of a holding portion of a holding unit showing a third embodiment of the present invention.

FIG. 14 is a view corresponding to FIG.

FIG. 15 is a diagram corresponding to FIG. 7;

FIG. 16 is a view corresponding to FIG. 6 showing a fourth embodiment of the present invention.

FIG. 17 is a diagram corresponding to FIG. 7;

FIG. 18 is a view corresponding to FIG. 6 showing a fifth embodiment of the present invention.

FIG. 19 is a view showing an upper layer portion of the probe unit in FIG.
Equivalent figure

FIG. 20 is a view equivalent to FIG. 7.

FIG. 21 is a view corresponding to FIG. 6 showing a sixth embodiment of the present invention.

FIG. 22 is a view equivalent to FIG. 7.

FIG. 23 is a view corresponding to FIG. 2 showing a seventh embodiment of the present invention.

[Explanation of symbols]

1 is a wafer holder, 2 is a semiconductor wafer, 3 is a wafer accommodating portion, 4 is a positioning pin, 7 and 54 are buffer sheets, 8 is a semiconductor chip, 9 is an electrode pad, 10, 30, 34 and 3
8, 40, 48 are probe units, 11 is a probe plate, 12 is an outer frame, 15, 31, 35, 46, 4
9, 55 is a holding unit, 16 is a screw, 16a is a spring, 18 is a holding portion, 18a is an opening portion, 19, 43
Is a multilayer wiring board, 20 is a bump (contact), 21 and 42
Are connecting electrodes, 22 and 36 are positioning weirs, and 24 and 4
4 is a conductor pattern, 25 is a ball bump with a wire, 2
6 is a resin layer, 28 is a groove portion, 32 and 39 are positioning step portions, 41 and 50 are upper layer portions, 52 is a chip holder, and 53 is a chip accommodating portion.

Claims (19)

[Claims] 1. A semiconductor test apparatus capable of performing a characteristic test on each of a plurality of semiconductor chips formed on a semiconductor wafer in the state of the semiconductor wafer, wherein the semiconductor test apparatus is formed on the surface of each semiconductor chip. A semiconductor test apparatus comprising a plurality of probe units each having a plurality of contacts capable of electrically contacting each of a plurality of electrode pads, the probe plate being configured by combining the plurality of probe units. 2. The semiconductor test apparatus according to claim 1, wherein the plurality of probe units of the probe plate are individually detachably provided. 3. A wafer holder having a concave portion capable of accommodating the semiconductor wafer, and a holding unit for fixing the plurality of probe units constituting the probe plate to the wafer holder in a state of being pressed from the back surface portion. The semiconductor test apparatus according to claim 1, wherein the semiconductor test apparatus is a semiconductor test apparatus. 4. The probe unit has a connecting electrode formed so that a lead wire electrically connected to the contactor can be led out from a region excluding a peripheral portion of the back surface, and the pressing unit is provided in the probe unit. 4. The semiconductor test apparatus according to claim 3, wherein the window portion is formed so as to hold down the back surface portion from the peripheral portion and lead out a lead wire connected to the connection electrode. 5. The probe unit is provided with a connecting electrode so that a leader line electrically conducting to the contactor can be led out from a region excluding a central portion of a back surface, and the pressing unit is a probe unit of the probe unit. 4. The semiconductor test apparatus according to claim 3, wherein the window portion is formed so as to hold down the back surface portion from the central portion and lead out a lead wire connected to the connection electrode. 6. A multilayer wiring substrate formed in a shape corresponding to a semiconductor chip formed on a semiconductor wafer under test, and a plurality of electrodes of the semiconductor chip formed on one surface side of the multilayer wiring substrate. A plurality of contacts arranged corresponding to the positions corresponding to the pads, and provided in a predetermined region on the other surface side of the multilayer wiring board so as to correspond to the plurality of contacts, respectively, the semiconductor chip And a connecting electrode for a plurality of leader lines arranged and formed so as to be wider than the interval dimension between the electrode pads, and the contactor and the connecting electrode are electrically connected to the intermediate layer of the multilayer wiring board. A probe unit for a semiconductor test device, wherein a conductor pattern is formed so as to be electrically connected. 7. A contact electrode pattern provided on the surface of the multilayer wiring board on which the contact is provided, and a resin surface having elasticity provided on the surface of the contact provided. A layer and a bonding wire that is bonded to the contact electrode pattern and is provided so that its wire portion protrudes from the surface layer, and the contact is a tip of the bonding wire of a portion protruding from the surface layer. The probe unit for a semiconductor test device according to claim 6, wherein the probe unit is formed in the portion. 8. The probe unit for a semiconductor test apparatus according to claim 7, wherein the contactor is composed of a bump member fixed in a state of being in electrical contact with a tip portion of the bonding wire. 9. A groove portion is formed in a surface layer of the multilayer wiring board on a surface side on which the contact is arranged so as to surround a portion where the contact is arranged. The probe unit for a semiconductor test device according to claim 7. 10. A multilayer wiring board portion protruding from a peripheral portion is provided on a surface side of the multilayer wiring board on which the contacts are arranged, and the multilayer wiring board portion also has a side surface portion for connection. The probe unit for a semiconductor test device according to claim 6, wherein an electrode is formed. 11. A projecting dam portion is formed on a surface side of the multilayer wiring board on which the contacts are arranged, the projection dam portion defining a portion with which a holding portion of a holding unit provided in a semiconductor test apparatus contacts. The probe unit for a semiconductor test device according to claim 6, wherein the probe unit is a semiconductor test device. 12. A step is defined on a surface side of the multilayer wiring board on which the contactor is arranged, which defines a portion with which a holding portion of a holding unit provided in a semiconductor test apparatus contacts. The probe unit for a semiconductor test device according to any one of claims 6 to 10. 13. A method of manufacturing a probe unit having a contact for making electrical contact with an electrode pad of a semiconductor chip formed on a semiconductor wafer, wherein a surface side on which the contact is formed is a multilayer wiring board. The first step of forming an electrode pattern connected to the contactor on the surface, the second step of bonding a ball bump with a wire to this electrode pattern, and the ball bump portion cut to a predetermined length to the wire It is formed through a third step of covering the tip end portion with a flexible resin layer to the extent that it is exposed, and a fourth step of processing the wire tip end portion of the ball bump portion into a bump shape by heating or pressing. A method for manufacturing a probe unit for a semiconductor test device, comprising: 14. In the fourth step, a ball bump member is separately pressure-bonded to the wire tip of the ball bump portion to form a bump serving as a contactor.
3. A method for manufacturing a probe unit for a semiconductor test device according to 3. 15. The semiconductor device according to claim 13, wherein in the fourth step, a bump portion to be a contact is formed by separately transferring a conductive resin to a wire tip of the ball bump portion. Method for manufacturing probe unit for test equipment. 16. The semiconductor test according to claim 13, wherein in the fourth step, a bump as a contactor is formed by separately crimping and reflowing a solder bump on the wire tip of the ball bump portion. Method for manufacturing probe unit for device. 17. The method according to claim 13, wherein the ball bump portion is formed through a fifth step of forming a groove portion by laser processing around the bump portion formed at the tip of the wire of the ball bump portion. A method for manufacturing a probe unit for a semiconductor testing device as described above. 18. Between the third step and the fourth step, a sixth step of flattening and polishing the resin layer to make the wire portions of the ball bump uniform in length, and only the resin layer. 18. A method of manufacturing a probe unit for a semiconductor testing device according to claim 13, further comprising a seventh step of removing a predetermined thickness. 19. A chip holder having a concave portion capable of accommodating the semiconductor chip, the probe unit according to claim 6, and the chip holder which is held in a state in which the probe unit is pressed from the rear surface. A semiconductor testing device comprising: a holding unit for fixing.