JPH09270706A - Pll circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a DDS capable of stable reception by revising optionally a reference oscillating frequency so that harmonics do not enter a reception band. SOLUTION: An up-down switch 8 of an operation section is operated to enter a setting numeral of a desired oscillating frequency, then a CPU 5 sets the numeral to a DDS 6. A phase comparison signal sampled based on the set numeral is fed to a phase comparator 3. An oscillated frequency from a VCO 1 is given to a DDS 2 as a clock signal and the output of the DDS 2 is sampled based on the clock signal and fed to the phase comparator 3, in which the phase comparison signal outputted from the DDS 6 and based on the entered numeral is compared with the sampled signal from the DDS 2 and from which an error signal is outputted. The error signal is fed to the VCO 1 as the oscillated frequency control signal via an LPF 4.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a PLL circuit using a DDS.

[0002]

2. Description of the Related Art In the prior art, FIG. 3 is a diagram showing a configuration of a PLL circuit, in which a reference oscillation frequency output from a reference oscillator is used as a clock signal to set a numerical value corresponding to the oscillation frequency. Digit
a PLL circuit that compares an output signal that is input to and sampled into an Al Synthesizer) with the output of the voltage-controlled oscillator as a phase comparison signal.

The configuration of the PLL circuit of FIG. 3 is as follows: 1 is a voltage controlled oscillator (VCO), 3 is a phase comparator, 4 is an LPF (low pass filter), 5 is a control CPU, 6 is a DDS, 7
Is a reference oscillator, and 8 is a frequency setting up / down switch.

The operation of the PLL circuit shown in FIG. 3 will be described. The DDS 6 which takes in the frequency oscillated by the reference oscillator 7 as a clock signal receives the desired frequency set value by the up / down switch 8 and outputs the data to the CPU 5
To the DDS 6 for setting, a signal based on the setting data is output to the phase comparator 3 as a phase comparison signal. The oscillation frequency signal output from the VCO 1 is supplied to the phase comparator 3 and is phase-compared by the phase comparison signal input from the DDS 6. The error signal output from the phase comparator 3 is smoothed through the LPF 4 to obtain the VCO 1 Is supplied as an oscillation frequency control signal. When the PLL circuit locks up, a stable desired frequency is output from the VCO 1.

Here, the oscillation frequency of the VCO 1 of the PLL circuit is F, the reference oscillation frequency output from the reference oscillator 7 is Fref, the step up / down step of the oscillation frequency of the VCO 1 is Δf, and the phase comparison signal output from the DDS 6 is generated. For the setting of, the data of either the frequency setting value set by the up / down switch 8 or the channel frequency selected from a plurality of channels stored in advance in the memory of the CPU 5 is supplied as the setting value D of DDS, and D
Assuming that the DS counting range is 2 ⁿ , the oscillation frequency F of the VCO 1 is F = Fref × D / 2 ⁿ . The step-up / down step of the oscillation frequency F of the VCO 1 is dF / dD = Δf = Fref / 2 ⁿ .... 2, and in order to set Δf to 1 Hz, Fref = 2 ⁿ
(Hz) is a necessary condition. Therefore, in order to obtain the desired accurate frequency step, the reference oscillation frequency is limited to 2 ⁿ , and the reference oscillation frequency Fref is set to 8 MHz.
In the vicinity, 2 ⁿ becomes 2 ²³ , which is 8.388608 MH.
z. In the vicinity of 16MHz, it becomes 2 ²⁴ , which is 16.777.
Must be 216 MHz.

Here, when the reception frequency band is the VHF band centered at 140 MHz, the oscillation frequency of the VCO 1 is
For example, if the local oscillation frequency is set above the reception frequency, the output frequency Fref of the reference oscillator 7 becomes 16.777216.
If MHz, the multiplier n of 2 ⁿ may be set to 28,
The reference oscillation frequency Fref is 16.7772216 MHz, which is a frequency of 2 ²⁷ , which is 134.217744 MHz, and 2 ⁸ higher harmonics enter the reference oscillation frequency Fref. Since the vicinity of this reception frequency is affected by harmonics, in order to avoid this, the PLL circuit should strengthen the shield even if the cost increases, or it may be larger than the necessary bit and become large scale, which is not accurate.
There is a soft processing method that obtains a pseudo required step frequency.

The PLL circuit described above has one DDS.
Although frequency selection processing is performed by itself, in the actual circuit, the frequency is 140 MHz band of VHF or 430 MH in UHF.
If you use the z band, you can set the frequency band finely,
Although not shown in the case of this PLL circuit, when the output frequency of the VCO 1 is supplied to the phase comparator 3 through a divider, or a circuit for passing the phase comparison signal output from the DDS through the divider is also provided for frequency division processing of the signal. PLL configured to share
There is also a circuit.

[0008]

The output of the reference oscillator is input as a clock signal to the DDS in which the desired oscillation frequency is set as the set value D, and the output is added as a phase comparison signal to the phase comparator to add the oscillation frequency of the VCO. P of the method of comparing the phases of VCO and controlling the oscillation frequency of the VCO with the error signal.
In the LL circuit, in order to make the frequency an integer such as 1 Hz step, the reference oscillation frequency Fref supplied to the DDS is set.
And the oscillation frequency F of the VCO, F = Fref × D
Since there is a formula of / 2 ⁿ , the reference oscillation frequency must be limited to 2 ⁿ in the counting range, and therefore harmonics of the reference oscillation frequency may enter the reception band.
An object of the present invention is to provide a PLL circuit equipped with a DDS that can stably receive signals by arbitrarily changing the reference oscillation frequency so that higher harmonics of the oscillation frequency of the reference oscillator do not enter the reception band.

[0009]

A DDS for inputting an output of a reference oscillator as a clock signal, and an error signal output obtained by inputting an output signal of the DDS and an output signal based on a voltage controlled oscillator into a phase comparator for phase comparison. In a PLL circuit configured to supply the voltage controlled oscillator to the voltage controlled oscillator through an LPF, a first DD for inputting an output of the voltage controlled oscillator as a clock signal between the voltage controlled oscillator and the phase comparator.
S and a second DDS for inputting the output of the reference oscillator as a clock signal are provided, and the output signal of the first DDS and the second DDS output signal are supplied to the phase comparator for phase comparison. And a first PLL circuit configured as described above.
The PLL circuit is characterized in that it can be changed to an arbitrary reference oscillation frequency by changing the set value of the DDS with a value conforming to the reference oscillation frequency.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a P according to an embodiment of the present invention.
It is a block diagram of an LL circuit. The figure will be described. 1 in the figure
Entered VCO, 2 is the output of the VCO as a clock signal, a first DDS, 3 the output signal of the second DDS to output to the phase comparator 3 and a frequency-converted by D _1/2 ^m selected set A phase comparator for phase comparing the output of the first DDS as a phase comparison signal, 4 is an LPF for smoothing the error signal output from the phase comparator 3, 5 is a control CPU, 6
The reference frequency Fref that is output from the reference oscillator 7 is inputted as a clock signal, the second DDS, 8 are up-down switch of the operation unit for outputting a phase comparison signal is converted by the set value of D _2/2 ⁿ is is there.

The setting of each part of this PLL circuit is performed by the VCO1.
The oscillation frequency F is converged to the phase comparison signal output based on the setting value D ₂ of the second DDS 6 when the PLL circuit is locked up. Set value of the first DDS2 is the D _1/2 ^m, the set value of the second DDS6 is D
_2/2 ^n, the phase comparator 3 the reference oscillation frequency as Fref for PLL circuit and the phase comparator are locked up, in ^{_{F × D 1/2 m =}} Fref × D 2/2 n ......... 3 Therefore, the oscillation frequency of the VCO ₁ is F = Fref × D 1/2 ⁿ × 2 ⁿ / D ₂ . ……… 4

This equation will be described. Reference oscillation frequency Fref output from the reference oscillator 7 is sampled by the set value of input to the second DDS6 as the clock signal D _2/2 ^n. Of these values, for 2 ⁿ , the second DDS6 is a numerical value in the counting range, which is determined by the DDS IC used. As for D ₂ , when the desired oscillation frequency is operated by operating the up / down switch 8 of the operation unit to input a set numerical value, the CPU 5 causes the second D
It is set to DS6. The set 2 ⁿ counting range and D
^The phase comparison signal sampled by ² is output to the phase comparator 3.

[0013] oscillation frequency of VCO1 is D is set to enter the first DDS2 as a clock signal _1/2 ^m
Is sampled and input to the phase comparator 3, and phase comparison is performed by the phase comparison signal based on the set value D ₂ output from the second DDS 6 and the error signal is output from the phase comparator 3. This error signal is smoothed by the LPF 4 and supplied to the VCO 1 as an oscillation frequency control signal.
When the circuit locks up, the oscillation frequency F converges on the phase comparison signal by D ₂ of the second DDS 6 set by the up / down switch 8.

[0014] VCO1 of the oscillation frequency F of the up-down steps dF / dD ₂ = Δf is, F = a ^{_{Fref × D 2/2 n ×}} 2 m / D 1 ......... 5 In this equation, Δf = Fref × 2 ^mn / D ₁ ……… 6 and Δf becomes 1 Hz because D ₁ = Fref × 2
^mn . From this formula, D ₁ set to the first DDS2
It is sufficient that / 2 ⁿ is a numerical value corresponding to the reference oscillation frequency output from the reference oscillator 7. Therefore, if the count range of the first DDS 2 and the second DDS 6 is 2 ⁿ = 2 ^m , the D ₁ setting value of the _first DDS 2 may be set to the reference frequency, and thus the reference oscillation frequency can be freely selected. Even in this case, the up / down variable setting can be made in 1 Hz steps. Even if 2 ⁿ ≠ 2 ^m , the reference oscillation frequency can be freely selected by setting D ₁ including the difference. Therefore, a plurality of reference oscillation frequencies of the reference oscillator 7 are prepared and switched as necessary. As a result, it is possible to prevent reception interference due to harmonics caused by the reference oscillation frequency.

As described above, two sets of the first DDS2,
By incorporating the second DDS 6 in the PLL circuit and setting it to a relatively necessary setting value, the desired frequency of 1 Hz step can be obtained from the VCO 1, but in the actual circuit, the The phase comparison signal output from the DDS 6 is limited to a certain range, and the frequency signal obtained by dividing the output of the VCO 1 through a divider is output to the first DDS 2 and supplied to the phase comparator 3 in accordance with this. It is also performed in accordance with the phase comparison signal that has been made, and further, if necessary, the output of the second DDS 6 is also output to the phase comparator 3 as a phase comparison signal after passing through a divider.

[0016]

FIG. 2 shows a DDS in a PLL circuit having a divider.
It is a block diagram of the Example which provided. The configuration and operation of the figure will be described. 1 is VCO, 2 is first DDS, 3
Is a phase comparator, 4 is an LPF, 5 is a CPU, and 6 is a second D
DS, 7 is a reference oscillator, 8 is an up / down switch, 9
Is a divider.

The operation of this PLL circuit is performed at a V of 140 MHz.
The 140 MHz band when used as a local oscillator of a receiver in the HF band and the UHF band of 430 MHz will be described. Assuming that the local oscillation frequency for the reception frequency of 140 MHz is 140 MHz to 200 MHz, the reference frequency F
The ref and 40 MHz, the multiplier n of 2 ⁿ is a counting range of the second DDS6 a 30bit, D _2/2 ⁿ is 140MHz~200MHz / 2 ^30, and the second DD
5.215 MHz to 7.45 sampled at S6
It is in the range of 0 MHz. 2 ³⁰ Of this number DDS I
It is fixed by the C hardware and is a fixed value. next,
The value of D ₂ is set in the desired frequency range of 140 MHz to 200 MHz by the up / down switch 8. In this case, the sum or difference frequency with the IF frequency converted when the reception frequency is input is set by the software of the CPU 5. is, from the CPU5 the second DDS6 D _2/2 ⁿ
Is set.

Next, the output of VCO 1 is from 140 MHz to 200
The frequency of MHz is first divided by the divider 9 by ⅕ to be 28 MHz to 40 MHz, which is input to the first DDS 2 as a clock signal, and the D of the first DDS 2 is input.
_1/2 ^m of but are sampled by the setting, this setting divider _{9, F = Fref × D 2} /2 n × 2 m / D 1 × D ( division) ......... 7 becomes, D ₁ = Fref × 2 ^mn × D (frequency division) ………… 8. The multiplier n of 2 of the counting range of the second DDS 6 is set to 30
And then, the multipliers m 2 according to the first DDS2 the DDS IC hardware and 25 bits, because the reference oscillation frequency Fref is 40 MHz, the D ₁ to 8 Formula 25
It becomes 0 KHz. The output of the first DDS 2 is a signal capable of being locked up, while the output signal of the first DDS 2 is a lock-up signal with respect to the phase comparison signal output from the second DDS 6 input to the phase comparator 3.

Considering the case where the wireless communication device receives the VHF band around 140 MHz and the UHF band around 430 MHz, the frequency signal for phase comparison by the phase comparator 3 of the PLL circuit is around 5 MHz when the frequency signal is in the VHF band. On the other hand, in the case of the UHF band, the frequency becomes three times as high, so in such a case, the output of the second DDS 6 is also frequency-divided by a divider (not shown) as a phase comparison signal. In this case, the frequency division ratio of the divider 9 must be changed as well.

[0020]

According to the present invention, the phase comparison signal supplied to the phase comparator of the PLL circuit is supplied to the second DDS using the reference oscillation frequency as a clock signal and is sampled at the set desired oscillation frequency. The phase comparison signal and the output of the VCO are also supplied as clock signals to the first DDS, and the output thereof is phase-compared with the phase comparison signal and PLL
When the circuit locks up, a desired oscillation frequency is output, and the reference oscillation frequency can be arbitrarily set by setting the first DDS setting value to a value based on the reference oscillation frequency. The influence of harmonics can also be avoided. Besides, DDS is a digital IC
Therefore, it has an excellent practical effect that it is relatively inexpensive and highly safe.

[Brief description of drawings]

FIG. 1 is a block diagram of a main part of a PLL circuit showing an embodiment of the present invention.

FIG. 2 is a block diagram of another embodiment in which a divider is arranged in a PLL circuit including a DDS of the present invention.

FIG. 3 is a block diagram of a conventional PLL circuit.

[Explanation of symbols]

 1 Voltage Controlled Oscillator (VCO) 2 First DDS 3 Phase Comparator (PD) 4 LPF 5 CPU 6 Second DDS 7 Reference Oscillator 8 Up-Down Switch 9 Divider

Claims (1)

[Claims] 1. A voltage controlled oscillator, a phase comparator, and an LPF.
And a reference oscillator, and a DDS which inputs the output of the reference oscillator as a clock signal and outputs a phase comparison signal corresponding to a set frequency value to the phase comparator, wherein the voltage controlled oscillator and the phase A first DDS that inputs the output of the voltage controlled oscillator as a clock signal between the comparators and outputs a signal whose frequency is changed according to the set value, and the output of the reference oscillator as the clock signal to generate a phase comparison signal. A PLL circuit having a second DDS for outputting, a first
A PLL circuit characterized in that the reference oscillation frequency can be arbitrarily changed by changing the set value of the DDS to a value conforming to the reference oscillation frequency.