JPH09266198A - Dry etching method - Google Patents

Dry etching method

Info

Publication number
JPH09266198A
JPH09266198A JP8074103A JP7410396A JPH09266198A JP H09266198 A JPH09266198 A JP H09266198A JP 8074103 A JP8074103 A JP 8074103A JP 7410396 A JP7410396 A JP 7410396A JP H09266198 A JPH09266198 A JP H09266198A
Authority
JP
Japan
Prior art keywords
film
etching
silicon oxide
gas
oxide film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8074103A
Other languages
Japanese (ja)
Other versions
JP2836569B2 (en
Inventor
Keiichi Harashima
啓一 原島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP8074103A priority Critical patent/JP2836569B2/en
Priority to KR1019970011209A priority patent/KR970067691A/en
Publication of JPH09266198A publication Critical patent/JPH09266198A/en
Application granted granted Critical
Publication of JP2836569B2 publication Critical patent/JP2836569B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31105Etching inorganic layers
    • H01L21/31111Etching inorganic layers by chemical means
    • H01L21/31116Etching inorganic layers by chemical means by dry-etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching

Abstract

PROBLEM TO BE SOLVED: To obtain a means for forming self-aligned contact holes by dry etching a BPSG film/PSG film anisotropically and selectively to a silicon oxide film, using a compd. gas contg. C, F and/or H mixed with CH2 F2 . SOLUTION: Using silicone oxide films 4, 7 as an etching stopper, a BPSG film is anisotropically dry etched to form contact holes 10, using an etching gas composed of a compd. gas contg. C, F and/or H mixed with CH2 F2 . Even if the contact holes are larger than the electrode interconnection line spacing, they can be formed, without short-circuiting with the electrode interconnection. Thus it is possible to reserve an allowance for forming the contact holes by the lithography even if the electrode interconnection line spacing of a semiconductor device is very small.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は半導体装置の製造方
法に関し、特にシリコン酸化膜に対し、BPSG膜もし
くはPSG膜を選択的にドライエッチングする方法に関
する。
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for selectively dry-etching a BPSG film or a PSG film with respect to a silicon oxide film.

【0002】[0002]

【従来の技術】半導体装置の高集積化に伴い、コンタク
トホール径、電極配線幅及び電極配線間隔の微細化が要
求されている。このため図4(a)に示す様にコンタク
トホール10を電極配線6の間に形成する場合、電極配
線パターンに対するコンタクトホールパターンの小量の
目ずれで電極配線とコンタクトホールがショートしてし
まう危険性が増大する。これを解決するために自己整合
的にコンタクトホールを開口する必要がある。
2. Description of the Related Art As semiconductor devices become more highly integrated, finer contact hole diameters, electrode wiring widths, and electrode wiring intervals are required. Therefore, when the contact hole 10 is formed between the electrode wirings 6 as shown in FIG. 4A, there is a risk that the electrode wiring and the contact hole are short-circuited due to a small misalignment of the contact hole pattern with respect to the electrode wiring pattern. Sex is increased. In order to solve this, it is necessary to open contact holes in a self-aligned manner.

【0003】自己整合的なコンタクトホール形成方法と
して例えば特開平3−76230に、コンタクトホール
開口後に熱酸化を行なう方法が開示されている。これに
よれば、コンタクトホールと電極配線がオーバーラップ
した場合でも、酸素雰囲気中の熱酸化により電極配線側
面にシリコン酸化膜が形成され、これによりコンタクト
ホールと電極配線間の絶縁性が確保されるため、自己整
合的なコンタクトホール形成が可能となる。しかしなが
ら、酸化により電極配線幅の変化が起きるため、64M
DRM,256MDRM等、電極配線幅が0.35μm
〜0.25μmとなった場合、トランジスタ特性の変化
が顕著になり、半導体装置の安定した製造は困難とな
る。
As a method of forming a self-aligned contact hole, for example, Japanese Patent Laid-Open No. 3-76230 discloses a method of performing thermal oxidation after opening a contact hole. According to this, even when the contact hole and the electrode wiring overlap, a silicon oxide film is formed on the side of the electrode wiring by thermal oxidation in an oxygen atmosphere, thereby ensuring insulation between the contact hole and the electrode wiring. Therefore, a self-aligned contact hole can be formed. However, since the width of the electrode wiring changes due to oxidation, 64M
Electrode wiring width is 0.35μm such as DRM and 256MDRM
When the thickness is up to 0.25 μm, the change in transistor characteristics becomes remarkable, and stable manufacture of the semiconductor device becomes difficult.

【0004】又、図4(b)に示すように、自己整合的
なコンタクトホール開口方法が考案されている。ここで
は電極配線6の上面及び側面をシリコン窒化膜のエッチ
ングストッパ11であらかじめ覆っておく。このように
エッチングストッパ11を設けておき、エッチングスト
ッパ11に対して層間絶縁膜であるPSG膜もしくはB
PSG膜を選択的にエッチングすれば、コンタクトホー
ルパターンが目ずれした場合でも電極配線とショートさ
せることなくコンタクトホールを開口することができ
る。
As shown in FIG. 4B, a method of opening a contact hole in a self-aligned manner has been devised. Here, the upper and side surfaces of the electrode wiring 6 are previously covered with an etching stopper 11 of a silicon nitride film. The etching stopper 11 is provided in this manner, and a PSG film or a B
If the PSG film is selectively etched, the contact hole can be opened without short-circuiting with the electrode wiring even if the contact hole pattern is misaligned.

【0005】従来、エッチングストッパとしては、例え
ば1993年、ドライプロセスシンポジウム予稿集、p
193に述べられているように、シリコン窒化膜が考え
られている。しかしながら、シリコン窒化膜は、膜応力
や誘電率等の膜特性がシリコン酸化膜と異なることか
ら、エッチングストッパにシリコン窒化膜を用いた場
合、トランジスタ特性等に与える影響が大きいことが懸
念される。このためエッチングストッパには、現在LD
Dサイドウォール等に通常使用されているシリコン酸化
膜を用いることが望ましいと考えられている。
[0005] Conventionally, as an etching stopper, for example, in 1993, Proceedings of Dry Process Symposium, p.
As described in 193, silicon nitride films have been considered. However, since the silicon nitride film has different film characteristics such as film stress and dielectric constant from the silicon oxide film, there is a concern that the use of the silicon nitride film as an etching stopper greatly affects the transistor characteristics and the like. For this reason, the etching stopper is currently LD
It is considered that it is desirable to use a silicon oxide film commonly used for the D side wall and the like.

【0006】シリコン酸化膜をエッチングストッパとし
て用いた場合、シリコン酸化膜に対してPSG膜もしく
はBPPSG膜を選択的にエッチングする必要がある。
コンタクトホールエッチングには従来CHF3 とCF4
の混合ガスが用いられているが、この混合ガスを用いた
場合、シリコン酸化膜に対するBPSG膜のエッチング
速度は1.5〜2倍(選択比1.5〜2)程度である。
これに対し、1993年、春季第40回応用物理学関連
連合講演会予稿集、第2分冊、P612、31a−ZE
−4には、CHF3 ,CF4 及びCOの混合ガスを用い
ることにより、シリコン酸化膜に対するBPSG膜の選
択比が15程度得られることが報告されている。
When a silicon oxide film is used as an etching stopper, it is necessary to selectively etch a PSG film or a BPPSG film with respect to the silicon oxide film.
Conventional contact hole etching for CHF 3 and CF 4
When the mixed gas is used, the etching rate of the BPSG film with respect to the silicon oxide film is about 1.5 to 2 times (selectivity 1.5 to 2).
On the other hand, in 1993, the 40th Spring Meeting of the Applied Physics-related Lectures, 2nd volume, P612, 31a-ZE
No. -4, it is reported that the selectivity of the BPSG film to the silicon oxide film is about 15 by using a mixed gas of CHF 3 , CF 4 and CO.

【0007】[0007]

【発明が解決しようとする課題】従来技術であるCF4
とCHF3 等の混合ガス系でエッチングを行った場合、
シリコン酸化膜に対するBPSG膜の選択比は1.5〜
2程度の低い値である。このため、シリコン酸化膜に対
するBPSG膜の選択的なエッチングは不可能であっ
た。従来技術において選択比が低い理由は、シリコン酸
化膜上に選択的に保護膜を形成する能力が低いためであ
る。
The prior art CF 4
And etching with a mixed gas system such as CHF 3
The selectivity of the BPSG film to the silicon oxide film is 1.5 to
It is a low value of about 2. For this reason, it has been impossible to selectively etch the BPSG film with respect to the silicon oxide film. The reason why the selectivity is low in the prior art is that the ability to selectively form a protective film on a silicon oxide film is low.

【0008】フロロカーボン系のガスによりドライエッ
チングを行なう場合、エッチングと同時に炭素及びフッ
素を成分とするポリマー形成が起っている。シリコン酸
化膜,BPSG膜等の膜中に酸素を含む膜をエッチング
する場合、エッチング中に膜から放出される酸素原子
が、このポリマーと結びつき揮発性のCO,COF等を
生成して排出されるため、ポリマーが堆積せず保護膜を
形成しづらい。
When dry etching is performed using a fluorocarbon-based gas, a polymer containing carbon and fluorine is formed simultaneously with the etching. When a film containing oxygen in a film such as a silicon oxide film or a BPSG film is etched, oxygen atoms released from the film during the etching are combined with the polymer to generate volatile CO, COF, etc., and are discharged. Therefore, the polymer is not deposited, and it is difficult to form the protective film.

【0009】又、従来技術ではCF4 とCHF3 の混合
ガス系を用いた場合、生成されるポリマー中のフッ素含
有量が多い。ポリマー中の炭素成分の割合が大きい程、
イオ衝撃に対する耐性は強くなりエッチングされにくく
なるため、ポリマーが堆積し保護膜の形成が促進され
る。フッ素含有量の多い膜では、イオン衝撃で保護膜自
体がスパッタ除去されてしまうため、保護効果が減少す
る。
In the prior art, when a mixed gas system of CF 4 and CHF 3 is used, the produced polymer has a large fluorine content. As the ratio of the carbon component in the polymer is larger,
Since resistance to ion bombardment is increased and etching is difficult, the polymer is deposited and the formation of a protective film is promoted. In a film containing a large amount of fluorine, the protective film itself is sputtered off by ion bombardment, so that the protective effect is reduced.

【0010】BPSG膜に比較してシリコン酸化膜の酸
素放出量は少ないため、保護膜は形成されやすいものの
その堆積速度は小さい。又、従来技術であるCHF3
CF4 の混合ガスを用いた場合、フッ素含有量が高いた
め堆積され難い。これらによりシリコン酸化膜に対する
BPSG膜の選択比は1.5〜2程度となり、BPSG
膜の選択的なエッチングは困難であった。
Since the amount of oxygen released from the silicon oxide film is smaller than that of the BPSG film, a protective film is easily formed but the deposition rate is low. Further, when a mixed gas of CHF 3 and CF 4 , which is a conventional technique, is used, deposition is difficult due to a high fluorine content. As a result, the selectivity of the BPSG film to the silicon oxide film becomes about 1.5 to 2,
It was difficult to selectively etch the film.

【0011】又、CF4 ,CHF3 にCOガスを添加す
ることにより、シリコン酸化膜に対するBPSG膜の選
択比が15程度に向上されることが報告されている(1
993年、春季第40回応用物理学関連連合講演会予稿
集第2分冊,P612,31a−ZE−4)。しかしな
がら、COガスは毒性が強く、取扱う上で危険であり、
又、COをCO2 などに変換して除外するための除外設
備等が必要である等の問題点があった。
It has been reported that the addition of CO gas to CF 4 and CHF 3 improves the selectivity of the BPSG film to the silicon oxide film to about 15 (1).
993, Proceedings of the 40th Joint Lecture Meeting on Applied Physics, 2nd volume, P612, 31a-ZE-4). However, CO gas is highly toxic and dangerous to handle.
In addition, there is a problem that an exclusion facility for converting CO into CO 2 or the like and excluding it is required.

【0012】さらに、自己整合的に電極配線とショート
させることなくコンタクトホールを開口する方法とし
て、シリコン窒化膜で電極配線を覆い、これをエッチン
グストッパとする方法が提案されているが、膜特性がシ
リコン酸化膜と異なることから、トランジスタ特性等の
製品に与える影響が大きいことが懸念される。
Further, as a method of opening a contact hole in a self-aligned manner without short-circuiting with an electrode wiring, a method of covering an electrode wiring with a silicon nitride film and using this as an etching stopper has been proposed. Since it is different from the silicon oxide film, there is a concern that the influence on the product such as transistor characteristics is large.

【0013】[0013]

【課題を解決するための手段】本発明のエッチング方法
は、シリコン酸化膜に対してPSGもしくはBPSG膜
を選択的かつ異方的にエッチングするエッチング方法に
おいて、フッ素,炭素もしくはこれに水素を含む化合物
ガスと、CH2 2 ガスとの混合ガスを反応ガスとして
用いることを特徴としている。フッ素,炭素もしくはこ
れに水素を含む化合物ガスとしては、CF4 ,C
2 6 ,C3 8 ,CHF3 を用いることができる。
The etching method of the present invention is an etching method for selectively and anisotropically etching a PSG or BPSG film with respect to a silicon oxide film, and is a compound containing fluorine, carbon or hydrogen in it. It is characterized in that a mixed gas of a gas and CH 2 F 2 gas is used as a reaction gas. As the compound gas containing fluorine, carbon or hydrogen, CF 4 , C
2 F 6 , C 3 F 8 and CHF 3 can be used.

【0014】[0014]

【発明の実施の形態】本発明について図面を参照して説
明する。図1はC2 6 とCH2 2 の混合ガスにおい
て、総ガス流量に対するCH2 2 ガスの混合比を変え
た場合に得られたシリコン酸化膜とBPSG膜のエッチ
ング速度を示している。CH2 2 ガスを添加すること
により、ガス中のフッ素をHFの形で排気させることが
できる。これによりポリマー中の炭素濃度を増加させ、
保護膜形成を促進させることができる。BPSG膜に比
較してシリコン酸化膜は酸素の放出量が少ないため、揮
発性物質であるCO,COF等の生成量が少ない。この
ためCH2 2 の混合比を調整することによりシリコン
酸化膜上へ選択的にポリマーを堆積させることができ
る。CH2 2 混合比60%〜90%において、BPS
G膜をシリコン酸化膜に対し選択的にエッチングさせる
ことができた。CH2 2 を90%より大きくするとB
PSG膜上へのポリマー堆積速度が大きくなり、エッチ
ング速度が低下する。
BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described with reference to the drawings. FIG. 1 shows the etching rates of the silicon oxide film and the BPSG film obtained when the mixing ratio of the CH 2 F 2 gas to the total gas flow rate was changed in the mixed gas of C 2 F 6 and CH 2 F 2 . . By adding the CH 2 F 2 gas, fluorine in the gas can be exhausted in the form of HF. This increases the carbon concentration in the polymer,
The formation of a protective film can be promoted. Since the silicon oxide film emits less oxygen than the BPSG film, the amount of volatile substances such as CO and COF generated is small. Therefore, the polymer can be selectively deposited on the silicon oxide film by adjusting the mixing ratio of CH 2 F 2 . At a CH 2 F 2 mixing ratio of 60% to 90%, BPS
The G film could be selectively etched with respect to the silicon oxide film. CH 2 F 2 greater than 90% B
The polymer deposition rate on the PSG film increases, and the etching rate decreases.

【0015】又、CH2 2 混合比を60%より減少さ
せると、ポリマーの堆積速度が小さくなり、シリコン酸
化膜上への保護膜形成量の減少が顕著になるために選択
的なエッチングは困難となる。これらよりCH2 2
合比60〜90%の範囲でエッチングすることが望まし
い。
If the mixing ratio of CH 2 F 2 is reduced to less than 60%, the deposition rate of the polymer decreases and the amount of the protective film formed on the silicon oxide film is significantly reduced. It will be difficult. From these, it is desirable to perform etching in the range of a CH 2 F 2 mixture ratio of 60 to 90%.

【0016】次に本発明を用いて、コンタクト形成に適
用した第1の実施の形態を図2に示す。まず図2(a)
に示すように、シリコン基板1上にシリコン酸化膜2,
ポリシリコン膜3,シリコン酸化膜4を順次堆積する。
次に図2(b)に示すように、レジストを塗布,現像
し、ゲート配線パターンを形成する。これをマスクとし
てシリコン酸化膜4,ポリシリコン膜3をドライエッチ
ングして電極配線6を形成する。レジスト除去後、図2
(c)のようにシリコン酸化膜7を全面に形成し、図2
(d)に示すようにこれを異方性エッチングでエッチバ
ックすることによりポリシリコン膜である電極配線6の
上面及び側面のみにシリコン酸化膜を形成される。その
後、図2(e)に示すように層間絶縁膜となるBPSG
膜8を堆積し、レジストを塗布、現像することによりコ
ンタクトホールレジストパターン9を形成する。
FIG. 2 shows a first embodiment of the present invention applied to contact formation using the present invention. First, FIG.
As shown in FIG. 1, a silicon oxide film 2,
A polysilicon film 3 and a silicon oxide film 4 are sequentially deposited.
Next, as shown in FIG. 2B, a resist is applied and developed to form a gate wiring pattern. Using this as a mask, the silicon oxide film 4 and the polysilicon film 3 are dry-etched to form the electrode wiring 6. After removing the resist,
A silicon oxide film 7 is formed on the entire surface as shown in FIG.
This is etched back by anisotropic etching to form a silicon oxide film only on the upper and side surfaces of the electrode wiring 6 which is a polysilicon film as shown in FIG. After that, as shown in FIG.
A contact hole resist pattern 9 is formed by depositing a film 8 and applying and developing a resist.

【0017】ここで本発明を用いてシリコン酸化膜4,
7をエッチングストッパとしてBPSG膜を異方性ドラ
イエッチングし、コンタクトホール10を開口する。例
えば圧力0.04Torr,C2 6 30sccm,C
2 2 70sccm,高周波電力800Wでエッチン
グを行なうことにより、シリコン酸化膜4,7に対して
20程度の選択比でBPSG膜8をエッチングすること
ができる。このため図2(f)に示すように、コンタク
トホール10が電極配線に対して目ずれしていた場合で
も、これらのショートを防ぐことができる。
Here, using the present invention, the silicon oxide film 4,
The contact hole 10 is opened by performing anisotropic dry etching of the BPSG film using the etching stopper 7 as an etching stopper. For example, a pressure of 0.04 Torr, C 2 F 6 30 sccm, C
The BPSG film 8 can be etched at a selectivity of about 20 with respect to the silicon oxide films 4 and 7 by performing etching with H 2 F 2 70 sccm and high frequency power 800 W. For this reason, as shown in FIG. 2F, even when the contact hole 10 is misaligned with respect to the electrode wiring, it is possible to prevent these short circuits.

【0018】次に本発明の第2の実施の形態を図3を参
照して説明する。ここでは、電極配線間隔よりも大きい
径のコンタクトホールを電極間に形成する場合を示す。
まず第1の実施の形態の図2(a)〜(d)と同様に電
極配線となるポリシリコン膜の上面及び側面にシリコン
酸化膜を形成させる。その後図3(a)に示すように層
間絶縁膜となるBPSG膜8を堆積し、レジストを塗
布,現像することによりコンタクトホールレジストパタ
ーン9を形成する。この時、コンタクトホール径は電極
配線間隔よりも大きくなっている。
Next, a second embodiment of the present invention will be described with reference to FIG. Here, a case is shown in which a contact hole having a diameter larger than the electrode wiring interval is formed between the electrodes.
First, similarly to FIGS. 2A to 2D of the first embodiment, a silicon oxide film is formed on the upper surface and the side surface of the polysilicon film which will be the electrode wiring. Thereafter, as shown in FIG. 3A, a BPSG film 8 serving as an interlayer insulating film is deposited, and a resist is applied and developed to form a contact hole resist pattern 9. At this time, the contact hole diameter is larger than the electrode wiring interval.

【0019】ここで本発明を用いてBPSG膜8を異方
性ドライエッチングし、コンタクトホール10を開口す
る。例えば、圧力0.04Torr,C2 6 20sc
cm、CH2 2 80sccm、高周波電力800Wで
エッチングを行なうことにより、シリコン酸化膜4,7
に対して25程度の選択比でBPSG膜をエッチングす
ることができた。このため、図3(b)に示すように電
極配線間隔よりもコンタクトホールが大きい場合でも、
電極配線とショートさせることなくコンタクトホールを
開口させることが可能となる。したがって、半導体装置
の高集積化により電極配線間隔が微細化された場合で
も、リソグラフィによるコンタクトホールパターン形成
に余裕をもたせることができた。
Here, using the present invention, the BPSG film 8 is anisotropically dry-etched to open a contact hole 10. For example, a pressure of 0.04 Torr, C 2 F 6 20 sc
cm, CH 2 F 2 80 sccm and high-frequency power 800 W to perform etching so that silicon oxide films 4 and 7
The BPSG film could be etched at a selectivity of about 25 with respect to the BPSG film. Therefore, as shown in FIG. 3B, even when the contact hole is larger than the electrode wiring interval,
The contact hole can be opened without short-circuiting with the electrode wiring. Therefore, even when the electrode wiring interval is reduced due to the high integration of the semiconductor device, it is possible to allow a margin for forming a contact hole pattern by lithography.

【0020】なお、上記実施の形態では、エッチングガ
スとしてC2 6 について記したが、炭素,フッ素及び
水素を含む化合物気体としては、CF4 ,C3 8 ,C
HF3 を用いてもよい。又、層間絶縁膜としてBPSG
膜の代わりにPSG膜を用いても同様な効果が得られ
る。
In the above embodiment, C 2 F 6 is described as an etching gas, but CF 4 , C 3 F 8 , C 3 is used as a compound gas containing carbon, fluorine and hydrogen.
HF 3 may be used. BPSG is used as an interlayer insulating film.
Similar effects can be obtained by using a PSG film instead of a film.

【0021】[0021]

【発明の効果】以上説明したように、本発明は炭素,フ
ッ素,もしくはこれに水素を含む化合物気体とCH2
2 ガスの混合ガスを用いてドライエッチングを行なうこ
とにより、シリコン酸化膜に対しBPSG膜,PSG膜
を異方的かつ選択的にエッチングすることができる。こ
れにより、シリコン酸化膜をエッチングストッパとした
自己整合的なコンタクトホールの開口手段を提供するこ
とが可能となり、半導体装置の歩留りを向上できるとい
う効果を有する。
As described above, according to the present invention, carbon, fluorine or a compound gas containing hydrogen is mixed with CH 2 F.
By performing dry etching using a mixed gas of two gases, the BPSG film and the PSG film can be anisotropically and selectively etched with respect to the silicon oxide film. This makes it possible to provide a self-aligned contact hole opening means using the silicon oxide film as an etching stopper, and has the effect of improving the yield of the semiconductor device.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明を説明するためのグラフである。FIG. 1 is a graph for explaining the present invention.

【図2】(a)〜(f)は本発明を用いコンタクトホー
ルを形成した第1の実施の形態を示す工程図である。
FIGS. 2A to 2F are process diagrams showing a first embodiment in which a contact hole is formed using the present invention.

【図3】(a),(b)は本発明を用いコンタクトホー
ルを形成した第2の実施の形態を示す工程図である。
3 (a) and 3 (b) are process diagrams showing a second embodiment in which a contact hole is formed using the present invention.

【図4】(a),(b)は従来技術によりコンタクトホ
ールを形成した例を示す断面図である。
FIGS. 4A and 4B are cross-sectional views showing an example in which a contact hole is formed by a conventional technique.

【符号の説明】[Explanation of symbols]

1 シリコン基板 2,4,7 シリコン酸化膜 3 ポリシリコン膜 5,9 レジストパターン 6 電極配線 8 BPSG膜 10 コンタクトホール Reference Signs List 1 silicon substrate 2, 4, 7 silicon oxide film 3 polysilicon film 5, 9 resist pattern 6 electrode wiring 8 BPSG film 10 contact hole

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 シリコン酸化膜に対してBPSG膜もし
くはPSG膜を選択的かつ異方的にドライエッチングす
る方法であって、エッチングガスとして炭素,フッ素も
しくはこれに水素を含む化合物ガスを用い、添加ガスと
してCH2 2 を用いることを特徴とするドライエッチ
ング方法。
1. A method of selectively and anisotropically dry-etching a BPSG film or a PSG film with respect to a silicon oxide film, wherein carbon, fluorine or a compound gas containing hydrogen is added as an etching gas, and the addition is performed. A dry etching method using CH 2 F 2 as a gas.
【請求項2】 前記エッチングガスとしてCF4 ,C2
6 ,C3 8 又はCHF3 を用いることを特徴とする
請求項1記載のドライエッチング方法。
2. An etching gas comprising CF 4 , C 2
The dry etching method according to claim 1, wherein the use of F 6, C 3 F 8 or CHF 3.
【請求項3】 前記エッチングガスと添加ガスの混合ガ
ス中の添加ガスの混合比は60〜90%であることを特
徴とする請求項1または請求項2記載のドライエッチン
グ方法。
3. The dry etching method according to claim 1, wherein a mixing ratio of the additive gas in the mixed gas of the etching gas and the additive gas is 60 to 90%.
JP8074103A 1996-03-28 1996-03-28 Dry etching method Expired - Fee Related JP2836569B2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP8074103A JP2836569B2 (en) 1996-03-28 1996-03-28 Dry etching method
KR1019970011209A KR970067691A (en) 1996-03-28 1997-03-28 Dry etching process

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8074103A JP2836569B2 (en) 1996-03-28 1996-03-28 Dry etching method

Publications (2)

Publication Number Publication Date
JPH09266198A true JPH09266198A (en) 1997-10-07
JP2836569B2 JP2836569B2 (en) 1998-12-14

Family

ID=13537527

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8074103A Expired - Fee Related JP2836569B2 (en) 1996-03-28 1996-03-28 Dry etching method

Country Status (2)

Country Link
JP (1) JP2836569B2 (en)
KR (1) KR970067691A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004502295A (en) * 2000-03-23 2004-01-22 マイクロン テクノロジー インコーポレイテッド Method of forming silicide gate stack for use in etching for forming self-aligned contacts
US7074724B2 (en) * 2000-04-27 2006-07-11 Micron Technology, Inc. Etchant and method of use

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010028673A (en) * 1999-09-22 2001-04-06 윤종용 Method for forming contact hole in semiconductor device using reactive ion etching
TW486733B (en) * 1999-12-28 2002-05-11 Toshiba Corp Dry etching method and manufacturing method of semiconductor device for realizing high selective etching

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004502295A (en) * 2000-03-23 2004-01-22 マイクロン テクノロジー インコーポレイテッド Method of forming silicide gate stack for use in etching for forming self-aligned contacts
US7074724B2 (en) * 2000-04-27 2006-07-11 Micron Technology, Inc. Etchant and method of use

Also Published As

Publication number Publication date
KR970067691A (en) 1997-10-13
JP2836569B2 (en) 1998-12-14

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