US20070148965A1 - Method and composition for plasma etching of a self-aligned contact opening - Google Patents
Method and composition for plasma etching of a self-aligned contact opening Download PDFInfo
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- US20070148965A1 US20070148965A1 US11/698,158 US69815807A US2007148965A1 US 20070148965 A1 US20070148965 A1 US 20070148965A1 US 69815807 A US69815807 A US 69815807A US 2007148965 A1 US2007148965 A1 US 2007148965A1
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- fluorocarbon
- flow rate
- sccm
- etching
- ammonia
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- 238000000034 method Methods 0.000 title claims abstract description 52
- 239000000203 mixture Substances 0.000 title claims description 15
- 238000001020 plasma etching Methods 0.000 title claims description 8
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims abstract description 65
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 claims abstract description 33
- 229910021529 ammonia Inorganic materials 0.000 claims abstract description 30
- 239000004065 semiconductor Substances 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 238000005530 etching Methods 0.000 claims abstract description 19
- 238000006243 chemical reaction Methods 0.000 claims description 22
- 125000006850 spacer group Chemical group 0.000 claims description 21
- 230000015572 biosynthetic process Effects 0.000 claims description 11
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 claims description 10
- RWRIWBAIICGTTQ-UHFFFAOYSA-N difluoromethane Chemical compound FCF RWRIWBAIICGTTQ-UHFFFAOYSA-N 0.000 claims description 10
- 229920002120 photoresistant polymer Polymers 0.000 claims description 7
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 claims description 6
- 150000005827 chlorofluoro hydrocarbons Chemical class 0.000 claims description 2
- WMIYKQLTONQJES-UHFFFAOYSA-N hexafluoroethane Chemical compound FC(F)(F)C(F)(F)F WMIYKQLTONQJES-UHFFFAOYSA-N 0.000 claims description 2
- QYSGYZVSCZSLHT-UHFFFAOYSA-N octafluoropropane Chemical compound FC(F)(F)C(F)(F)C(F)(F)F QYSGYZVSCZSLHT-UHFFFAOYSA-N 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 42
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- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 5
- 229910000069 nitrogen hydride Inorganic materials 0.000 description 5
- 239000001301 oxygen Substances 0.000 description 5
- 229910052760 oxygen Inorganic materials 0.000 description 5
- 239000000376 reactant Substances 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
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- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 3
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 3
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 3
- 239000005380 borophosphosilicate glass Substances 0.000 description 3
- 150000001875 compounds Chemical class 0.000 description 3
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- 229910052731 fluorine Inorganic materials 0.000 description 3
- 239000011737 fluorine Substances 0.000 description 3
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- 238000004519 manufacturing process Methods 0.000 description 3
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- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 230000000052 comparative effect Effects 0.000 description 2
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- 230000000873 masking effect Effects 0.000 description 2
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 description 2
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- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- NXHILIPIEUBEPD-UHFFFAOYSA-H tungsten hexafluoride Chemical compound F[W](F)(F)(F)(F)F NXHILIPIEUBEPD-UHFFFAOYSA-H 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
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- 125000001153 fluoro group Chemical group F* 0.000 description 1
- 239000008246 gaseous mixture Substances 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000000116 mitigating effect Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
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- 230000007935 neutral effect Effects 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
Definitions
- the present invention relates to a process for etching a self-aligned contact opening in a semiconductor device, and more particularly, to a method of plasma etching to prevent build up of undesirable polymers during contact formation.
- the invention also relates to a composition useful in the method of plasma etching described herein, as well as to the semiconductor structures formed thereby.
- FIG. 1 shows a cross section of a portion of a semiconductor device 10 in an intermediate stage of fabrication.
- the integrated circuit wafer section 10 has a substrate 12 .
- the substrate is formed of a semiconductor material, for example silicon, or a semiconductor material over an insulator, for example silicon-on-insulator (SOI).
- Field oxide regions 13 , transistor gate stacks 15 , side wall spacers 17 protecting the gate stacks, and doped regions 19 are formed over the substrate.
- a layer of insulating material 21 which is usually a type of glass oxide available in the art, for example, Boro-Phospho-Silicate Glass (BPSG), or silicon oxide material such as silicon dioxide or Tetraethylorthosilicate (TEOS) is formed over the substrate 12 .
- the layer of insulating material 21 may, in actuality, be formed as one or more layers of insulating material of, for example, BPSG, TEOS or silicon dioxide.
- the insulating layer 21 may be anywhere from a few hundred Angstroms to several thousand Angstroms in thickness.
- Formed over the insulative layer is a photoresist masking layer 23 using available photoresist materials.
- the photoresist layer 23 has a patterned opening 25 corresponding to the outline represented by the dotted lines shown in FIG. 1 .
- the patterned opening forms the outline of a self-aligned contact (SAC) opening which is thereafter created.
- SAC self-aligned contact
- a plasma etch is then conducted to form the SAC opening 27 , using the patterned opening 25 of the photoresist masking layer 23 as a guide.
- the patterned opening 25 generally follows the outline of the sides of the spacers 17 to align the etch for the contact opening.
- one or one fluorocarbons are introduced into a chamber containing the semiconductor device 10 .
- ionic and neutral etchants are then formed to etch the insulative layer 21 so as to form the opening 27 .
- the reaction of these etchants and other species with the insulative material of layer 21 produces a polymer layer 29 on the bottom and side wall spacers of opening 27 as a reaction product.
- a thin accumulation of polymer layer 29 along the sides of the side wall spacers 17 may be desirable to prevent subsequent erosion of the spacers.
- a build up of polymer layer 29 at the bottom of the SAC opening 27 can cause an undesirable phenomenon known as “etch stop”, in which further etching through the insulative layer 21 to the surface of the substrate 12 is prevented by this polymer layer build up 29 .
- the etch stop polymer layer 29 formed from the insulative layer can significantly inhibit suitable formation of the contact opening 27 .
- Oxygen may also be utilized to clean polymer debris from the bottom of the contact opening after exposure to the fluorine-based etchant plasma. Nitrogen (N 2 ) has also been utilized for cleaning residual debris after the etching process.
- a method for forming an opening in an insulative layer formed over a substrate in a semiconductor device in which the insulative layer is etched with ammonia and at least one fluorocarbon.
- the process parameters hereinafter described will substantially reduce or eliminate the formation of an “etch stop”.
- the invention provides a composition suitable for use in etching an insulative layer formed over a substrate in a semiconductor device.
- the composition comprises a gaseous mixture of at least one fluorocarbon and ammonia.
- the invention provides a process of forming an opening in an insulative layer formed over a substrate in a semiconductor device.
- a patterned photoresist mask layer is first formed over the insulative layer.
- a self-aligned contact opening is then etched in the insulative layer through an opening in the patterned resist layer.
- the opening is etched through to the substrate using a combination of ammonia and at least one fluorocarbon.
- the invention provides a method of preventing etch stop during etching of a semiconductor device which comprises adding ammonia to at least one fluorocarbon which is utilized for the etching.
- the invention provides a method of preserving a side wall spacer surrounding a gate stack during a self-aligned contact etch.
- the side wall spacer is contacted with a combination of at least one fluorocarbon and ammonia so as to form a protective layer thereover.
- the protective layer prevents erosion of the spacer as the contact opening is formed through to the substrate upon which the gate stack has been formed.
- the invention provides a method of forming a conductive plug inside a contact opening in an insulative layer between adjacent gate stacks formed over a substrate in a semiconductor device.
- the insulative layer is contacted with a plasma etchant mixture containing ammonia and at least one fluorocarbon at a pedestal temperature within the range of about ⁇ 50 to about 80 degrees Celsius so as to form a self-aligned contact opening in the insulative layer between the gate stacks without an etch stop.
- the contacting further forms a protective or passivating (nitrogen containing) layer over opposed side wall spacers which have been formed at the gate stacks.
- a conductive plug is then deposited inside the opening such that the plug is separated from the side wall spacers by the protective layer.
- FIG. 1 is a cross sectional view of a semiconductor device in an intermediate stage of fabrication.
- FIG. 2 is a cross sectional view of the device shown in FIG. 1 in a further stage of fabrication.
- FIG. 3 is a cross sectional view of a semiconductor device which utilizes the method and composition of the invention.
- FIG. 4 is a cross sectional view of a semiconductor device according to a further embodiment of the invention.
- substrate which is to be understood as including silicon, a silicon-on-insulator (SOI) or silicon-on-sapphire (SOS) structures, doped and undoped semiconductors, epitaxial layers of silicon supported by a base semiconductor foundation, and other semiconductor structures.
- SOI silicon-on-insulator
- SOS silicon-on-sapphire
- doped and undoped semiconductors epitaxial layers of silicon supported by a base semiconductor foundation
- the semiconductor need not be silicon-based, but could be based on silicon-germanium, germanium, indium phosphide, or gallium arsenide.
- substrate as used herein may also refer to any type of generic base or foundation structure.
- FIG. 3 illustrates the method of the invention which mitigates etch stop problems.
- a method of forming a contact opening using at least one fluorocarbon is desirable that the contact opening be a self-aligned contact (SAC) opening, that is, an opening which is self-aligned between two successive gate stack structures.
- SAC self-aligned contact
- at least two or more fluorocarbons are utilized, and in some embodiments at least three or more may be used as part of the invention.
- the fluorocarbon(s) may be chosen from those available in the art for plasma etching.
- Suitable fluorocarbons therefore include at least one member selected from the group consisting of fluorinated carbons, fluorohydrocarbons, chlorofluorocarbons and chlorofluorohydrocarbons.
- Non-limiting examples include such compounds as C 4 F 8 , C 4 F 6 , C 5 F 8 , CF 4 , C 2 F 6 , C 3 F 8 , CHF 3 , and CH 2 F 2 , and the like.
- one or more of the compounds CF 4 , CHF 3 , and CH 2 F 2 are utilized.
- the fluorocarbon(s) and ammonia are introduced into a suitable reaction chamber along with the semiconductor device.
- the reaction chamber pedestal may be set at an operating temperature within the range of about ⁇ 50 to about 80 degrees Celsius, with about 0 to about 80 degrees Celsius being preferred.
- Operating pressure is typically within the range of about 30 to about 60 milliTorrs, with about 40 to about 50 milliTorrs being more preferred, and about 45 milliTorrs being particularly desirable.
- About 600 watts of power is typically applied to the reaction chamber, but the wattage can vary within a range of about 500 to about 1500 watts.
- the fluorocarbon(s) and ammonia are introduced into the reaction chamber at a flow rate which will both allow formation of the self-aligned contact (SAC) opening 27 and prevent or reduce etch stop problems. In some embodiments, elimination or reduction of the etch stop problem may be quantifiable by the reduction in time it takes to complete formation of the opening, for example.
- the flow rates may vary slightly, but a ratio of the flow rate for each fluorocarbon to the flow rate of ammonia should typically be within the range of about 2:1 to about 40:1 (with flow rate being measured as scc/minute or sccm). It is preferred that the flow rate ratio not be less than about 3:1. More preferably, the flow rate ratio should be within the range of about 3:1 to about 20:1, and even more preferably about 4:1 to about 10:1.
- Actual flow rates for each of the individual fluorocarbon(s) utilized to form the SAC opening 27 will usually be within the range of about 10 to about 50 sccm, with about 10 to about 40 sccm being preferred.
- the flow rate will vary according to the particular fluorocarbon being utilized, and different fluorocarbons may have different flow rates. For example, when CF 4 is utilized, a flow rate of about 15 to about 20 sccm is preferred, with about 16 to about 18 sccm being more preferred. When CHF 3 is utilized, a flow rate of about 35 to about 45 sccm may be preferred, with about 37 to 42 sccm being even more preferred.
- a flow rate of about 10 to about 15 sccm is preferred, with about 11 to about 14 sccm being more preferred.
- the flow rate for the ammonia will usually be at least about 2 sccm, and should normally not exceed about 6 sccm. An upper limit flow rate of about 5 sccm is generally preferred. A flow rate range for the ammonia of about 2 sccm to about 4 sccm is especially desirable.
- the flow rates of both ammonia and the fluorocarbon(s) may be adjusted so as to yield the flow rate ratios previously described.
- An ammonia flow rate above about 8 sccm is generally not preferred because at this rate the resultant reactant mixture can sometimes cause loss of selectivity to the gate stack and/or spacer, and may also result in the etched opening not being self-aligned to the gate stacks and/or the side wall spacers.
- etchant gases which may be introduced into the reaction chamber together with the foregoing ammonia and fluorocarbon(s) can include oxygen, nitrogen and other compounds which are generally available in plasma etching.
- the photoresist mask layer may be removed using available methods.
- the device shown in FIG. 3 has a self-aligned contact opening 27 that is formed without etch stop problems.
- the reactant mixture of fluorocarbon(s) and ammonia produces a thin protective layer 35 along the sides of the contact opening 27 defined by the sides of the insulative layer and the side wall spacers 17 .
- the protective layer 35 is a polymeric material formed as a result of the reaction between the reactant mixture and the insulative layer and the side wall spacers, respectively. Formation of this protective layer 35 helps to prevent erosion and destruction of the side wall spacers during the etching process and thereafter, and is therefore desirable.
- the protective layer 35 is typically on the order of just a few Angstroms in thickness, e.g. about 5- 50 Angstroms.
- substantially no layer is formed at the bottom of the opening 27 .
- any de minimis layer of residue that may be formed is rather quickly eliminated as a result of continuous contact with the reactant mixture of the invention. Perhaps this is due at least in part to the differing chemical components which make up the insulative layer, in contrast to the side wall spacers upon the protective layer 35 is formed.
- a conductive plug 37 may be formed in the contact opening 27 after completion of the etching process.
- the conductive plug may be formed using a conductive metal such as tungsten, for example, using tungsten hexafluoride (WF 6 ) and silane (SiH 4 ) using available deposition techniques. Formation of the conductive plug may be proceeded by titanium deposition and annealing to coat the inside of the contact opening 27 in which the plug is formed. Titanium deposition will form a thin contact layer 39 , e.g. about 5-50 Angstroms, over the active region 19 of the substrate 12 . This contact layer will in turn act as a protective barrier to prevent free fluorine and tungsten atoms from penetrating into the substrate 12 at the active region site 19 during formation of the conductive plug 37 .
- the top of the plug may be co-planarized with the top of the insulative layer 21 using chemical mechanical planarization (CMP) techniques, if desired.
- CMP chemical mechanical planarization
- An optional conductive metal runner can also be provided over the plug 37 using available materials, e.g. aluminum, and methods (not shown in FIG. 4 ).
- the conductive plug 37 adheres more effectively inside the contact opening 27 .
- the protective layer 35 prevents erosion of the side wall spacers 17 which could materially detract from the performance of the plug 37 and the gate stacks 15 .
- a self-aligned contact opening was formed in the device illustrated in FIG. 3 .
- Plasma etching was conducted in a reaction chamber set at 600 watts, 45 milliTorr operating pressure, and 40 Gauss. Operating temperature was in the range of 0 to 50 degrees C.
- the following fluorocarbons were introduced into the reaction chamber together with ammonia, at the following flow rates: CF 4 18 sccm CHF 3 40 sccm CH 2 F 2 13 scccm NH 3 4 sccm
- Example 2 the same operating parameters and reaction conditions were utilized as set forth in Example 1, except that the flow rate of ammonia (NH 3 ) was 2 sccm. Under these conditions, a suitable self-aligned contact opening was also formed without etch stop.
- NH 3 ammonia
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Abstract
A method of forming a self-aligned contact opening in an insulative layer formed over a substrate in a semiconductor device involves etching the insulative layer with at least one fluorocarbon and ammonia.
Description
- This application is a divisional of application Ser. No. 09/752,685, filed Jan. 3, 2001, which is incorporated herein by reference.
- The present invention relates to a process for etching a self-aligned contact opening in a semiconductor device, and more particularly, to a method of plasma etching to prevent build up of undesirable polymers during contact formation. The invention also relates to a composition useful in the method of plasma etching described herein, as well as to the semiconductor structures formed thereby.
- In the formation of contact openings or vias in semiconductor devices used to provide metal-to-metal or conductive layer-to-conductive layer contacts, it is often necessary to etch through one or more layers of insulative material formed over a substrate.
FIG. 1 shows a cross section of a portion of asemiconductor device 10 in an intermediate stage of fabrication. The integratedcircuit wafer section 10 has asubstrate 12. The substrate is formed of a semiconductor material, for example silicon, or a semiconductor material over an insulator, for example silicon-on-insulator (SOI).Field oxide regions 13, transistor gate stacks 15,side wall spacers 17 protecting the gate stacks, and dopedregions 19 are formed over the substrate. A layer ofinsulating material 21, which is usually a type of glass oxide available in the art, for example, Boro-Phospho-Silicate Glass (BPSG), or silicon oxide material such as silicon dioxide or Tetraethylorthosilicate (TEOS) is formed over thesubstrate 12. The layer ofinsulating material 21 may, in actuality, be formed as one or more layers of insulating material of, for example, BPSG, TEOS or silicon dioxide. Theinsulating layer 21 may be anywhere from a few hundred Angstroms to several thousand Angstroms in thickness. Formed over the insulative layer is aphotoresist masking layer 23 using available photoresist materials. Thephotoresist layer 23 has apatterned opening 25 corresponding to the outline represented by the dotted lines shown inFIG. 1 . The patterned opening forms the outline of a self-aligned contact (SAC) opening which is thereafter created. The SAC opening will provide access to thesubstrate 12 through theinsulative layer 21. - Referring to
FIG. 2 , a plasma etch is then conducted to form the SAC opening 27, using thepatterned opening 25 of thephotoresist masking layer 23 as a guide. The patternedopening 25 generally follows the outline of the sides of thespacers 17 to align the etch for the contact opening. During the etching process, one or one fluorocarbons are introduced into a chamber containing thesemiconductor device 10. Under suitable conditions ionic and neutral etchants are then formed to etch theinsulative layer 21 so as to form theopening 27. Unfortunately, under prevailing conditions the reaction of these etchants and other species with the insulative material oflayer 21 produces apolymer layer 29 on the bottom and side wall spacers of opening 27 as a reaction product. A thin accumulation ofpolymer layer 29 along the sides of theside wall spacers 17 may be desirable to prevent subsequent erosion of the spacers. However, a build up ofpolymer layer 29 at the bottom of theSAC opening 27 can cause an undesirable phenomenon known as “etch stop”, in which further etching through theinsulative layer 21 to the surface of thesubstrate 12 is prevented by this polymer layer build up 29. In effect, the etchstop polymer layer 29 formed from the insulative layer can significantly inhibit suitable formation of thecontact opening 27. - Attempts have been made to prevent etch stop during contact opening formation. For example, it is known to add oxygen (O2) to the mixture of fluorocarbon gases which are introduced into the reaction chamber. As a result, the etch rate of insulative material, e.g. oxide, has been shown to increase. The addition of oxygen appears to be accompanied by an increase in the density of the fluorine atoms in the etchant discharge. However, the use of too much oxygen may undesirably dilute the fluorine concentration, and thereby decrease the etch rate. Oxygen may also be utilized to clean polymer debris from the bottom of the contact opening after exposure to the fluorine-based etchant plasma. Nitrogen (N2) has also been utilized for cleaning residual debris after the etching process.
- What is now needed in the art is a new method of forming a self-aligned contact opening in a semiconductor structure which can substantially eliminate etch stop problems. Also needed is a new composition which can be utilized in conjunction therewith.
- In accordance with one aspect of the invention a method is provided for forming an opening in an insulative layer formed over a substrate in a semiconductor device in which the insulative layer is etched with ammonia and at least one fluorocarbon. The process parameters hereinafter described will substantially reduce or eliminate the formation of an “etch stop”.
- Also in another aspect the invention provides a composition suitable for use in etching an insulative layer formed over a substrate in a semiconductor device. The composition comprises a gaseous mixture of at least one fluorocarbon and ammonia.
- In another aspect the invention provides a process of forming an opening in an insulative layer formed over a substrate in a semiconductor device. A patterned photoresist mask layer is first formed over the insulative layer. A self-aligned contact opening is then etched in the insulative layer through an opening in the patterned resist layer. The opening is etched through to the substrate using a combination of ammonia and at least one fluorocarbon.
- In another aspect the invention provides a method of preventing etch stop during etching of a semiconductor device which comprises adding ammonia to at least one fluorocarbon which is utilized for the etching.
- In another aspect the invention provides a method of preserving a side wall spacer surrounding a gate stack during a self-aligned contact etch. The side wall spacer is contacted with a combination of at least one fluorocarbon and ammonia so as to form a protective layer thereover. The protective layer prevents erosion of the spacer as the contact opening is formed through to the substrate upon which the gate stack has been formed.
- In another aspect the invention provides a method of forming a conductive plug inside a contact opening in an insulative layer between adjacent gate stacks formed over a substrate in a semiconductor device. The insulative layer is contacted with a plasma etchant mixture containing ammonia and at least one fluorocarbon at a pedestal temperature within the range of about −50 to about 80 degrees Celsius so as to form a self-aligned contact opening in the insulative layer between the gate stacks without an etch stop. The contacting further forms a protective or passivating (nitrogen containing) layer over opposed side wall spacers which have been formed at the gate stacks. A conductive plug is then deposited inside the opening such that the plug is separated from the side wall spacers by the protective layer.
- These and other advantages and features of the present invention will become more readily apparent from the following detailed description and drawings which illustrate various exemplary embodiments.
-
FIG. 1 is a cross sectional view of a semiconductor device in an intermediate stage of fabrication. -
FIG. 2 is a cross sectional view of the device shown inFIG. 1 in a further stage of fabrication. -
FIG. 3 is a cross sectional view of a semiconductor device which utilizes the method and composition of the invention. -
FIG. 4 is a cross sectional view of a semiconductor device according to a further embodiment of the invention. - Reference herein shall be made to the term “substrate,” which is to be understood as including silicon, a silicon-on-insulator (SOI) or silicon-on-sapphire (SOS) structures, doped and undoped semiconductors, epitaxial layers of silicon supported by a base semiconductor foundation, and other semiconductor structures. In addition, when reference is made to a “substrate” in the following description, previous process steps may have been utilized to form arrays, regions or junctions in or over the base semiconductor structure or foundation. In addition, the semiconductor need not be silicon-based, but could be based on silicon-germanium, germanium, indium phosphide, or gallium arsenide. The term “substrate” as used herein may also refer to any type of generic base or foundation structure.
- Referring again to the drawings,
FIG. 3 illustrates the method of the invention which mitigates etch stop problems. According to one embodiment, there is provided a method of forming a contact opening using at least one fluorocarbon. It is desirable that the contact opening be a self-aligned contact (SAC) opening, that is, an opening which is self-aligned between two successive gate stack structures. Preferably, at least two or more fluorocarbons are utilized, and in some embodiments at least three or more may be used as part of the invention. The fluorocarbon(s) may be chosen from those available in the art for plasma etching. Suitable fluorocarbons therefore include at least one member selected from the group consisting of fluorinated carbons, fluorohydrocarbons, chlorofluorocarbons and chlorofluorohydrocarbons. Non-limiting examples include such compounds as C4F8, C4F6, C5F8, CF4, C2F6, C3F8, CHF3, and CH2F2, and the like. Preferably, one or more of the compounds CF4, CHF3, and CH2F2 are utilized. - The fluorocarbon(s) are introduced with ammonia (NH3) in a
reaction chamber 30 together with the portion of the semiconductor device shown inFIG. 3 . The chamber may be any suitable reaction vessel available for plasma etching. The ammonia may be obtained from any suitable source. It has now been shown that the combination of at least one fluorocarbon, together with ammonia, is not only effective in forming thecontact opening 27 shown inFIG. 3 , but is also effective in mitigating against etch stop, i.e. the problem illustrated inFIG. 2 . - The fluorocarbon(s) and ammonia are introduced into a suitable reaction chamber along with the semiconductor device. The reaction chamber pedestal may be set at an operating temperature within the range of about −50 to about 80 degrees Celsius, with about 0 to about 80 degrees Celsius being preferred. Operating pressure is typically within the range of about 30 to about 60 milliTorrs, with about 40 to about 50 milliTorrs being more preferred, and about 45 milliTorrs being particularly desirable. About 600 watts of power is typically applied to the reaction chamber, but the wattage can vary within a range of about 500 to about 1500 watts.
- The fluorocarbon(s) and ammonia are introduced into the reaction chamber at a flow rate which will both allow formation of the self-aligned contact (SAC)
opening 27 and prevent or reduce etch stop problems. In some embodiments, elimination or reduction of the etch stop problem may be quantifiable by the reduction in time it takes to complete formation of the opening, for example. The flow rates may vary slightly, but a ratio of the flow rate for each fluorocarbon to the flow rate of ammonia should typically be within the range of about 2:1 to about 40:1 (with flow rate being measured as scc/minute or sccm). It is preferred that the flow rate ratio not be less than about 3:1. More preferably, the flow rate ratio should be within the range of about 3:1 to about 20:1, and even more preferably about 4:1 to about 10:1. - Actual flow rates for each of the individual fluorocarbon(s) utilized to form the
SAC opening 27 will usually be within the range of about 10 to about 50 sccm, with about 10 to about 40 sccm being preferred. The flow rate will vary according to the particular fluorocarbon being utilized, and different fluorocarbons may have different flow rates. For example, when CF4 is utilized, a flow rate of about 15 to about 20 sccm is preferred, with about 16 to about 18 sccm being more preferred. When CHF3 is utilized, a flow rate of about 35 to about 45 sccm may be preferred, with about 37 to 42 sccm being even more preferred. When CH2F2 forms part of the etchant plasma, a flow rate of about 10 to about 15 sccm is preferred, with about 11 to about 14 sccm being more preferred. In some embodiments of the invention, it may be desirable to utilize at least two of the foregoing fluorocarbons, and preferably all three at the flow rates already set forth. - The flow rate for the ammonia will usually be at least about 2 sccm, and should normally not exceed about 6 sccm. An upper limit flow rate of about 5 sccm is generally preferred. A flow rate range for the ammonia of about 2 sccm to about 4 sccm is especially desirable. The flow rates of both ammonia and the fluorocarbon(s) may be adjusted so as to yield the flow rate ratios previously described. An ammonia flow rate above about 8 sccm is generally not preferred because at this rate the resultant reactant mixture can sometimes cause loss of selectivity to the gate stack and/or spacer, and may also result in the etched opening not being self-aligned to the gate stacks and/or the side wall spacers.
- One or more of the fluorocarbons and the ammonia may be introduced into the reaction chamber substantially simultaneously, or successively. The order of introduction should be consistent with the invention's goals of eliminating etch stop, while providing a
SAC opening 27 to thesubstrate 12 in thedevice 10. - Other etchant gases which may be introduced into the reaction chamber together with the foregoing ammonia and fluorocarbon(s) can include oxygen, nitrogen and other compounds which are generally available in plasma etching.
- After the etching process is complete such that the self-aligned
contact opening 27 is formed, then the photoresist mask layer may be removed using available methods. - As a result of the invention, the device shown in
FIG. 3 has a self-aligned contact opening 27 that is formed without etch stop problems. Moreover, the reactant mixture of fluorocarbon(s) and ammonia produces a thinprotective layer 35 along the sides of thecontact opening 27 defined by the sides of the insulative layer and theside wall spacers 17. Theprotective layer 35 is a polymeric material formed as a result of the reaction between the reactant mixture and the insulative layer and the side wall spacers, respectively. Formation of thisprotective layer 35 helps to prevent erosion and destruction of the side wall spacers during the etching process and thereafter, and is therefore desirable. Theprotective layer 35 is typically on the order of just a few Angstroms in thickness, e.g. about 5- 50 Angstroms. - In contrast to the side wall spacers, substantially no layer is formed at the bottom of the
opening 27. Without being bound by any particular theory, it appears that any de minimis layer of residue that may be formed is rather quickly eliminated as a result of continuous contact with the reactant mixture of the invention. Perhaps this is due at least in part to the differing chemical components which make up the insulative layer, in contrast to the side wall spacers upon theprotective layer 35 is formed. - A further embodiment of the invention is shown now with reference to
FIG. 4 . Aconductive plug 37 may be formed in thecontact opening 27 after completion of the etching process. The conductive plug may be formed using a conductive metal such as tungsten, for example, using tungsten hexafluoride (WF6) and silane (SiH4) using available deposition techniques. Formation of the conductive plug may be proceeded by titanium deposition and annealing to coat the inside of thecontact opening 27 in which the plug is formed. Titanium deposition will form athin contact layer 39, e.g. about 5-50 Angstroms, over theactive region 19 of thesubstrate 12. This contact layer will in turn act as a protective barrier to prevent free fluorine and tungsten atoms from penetrating into thesubstrate 12 at theactive region site 19 during formation of theconductive plug 37. - After deposition of the
conductive plug 37, the top of the plug may be co-planarized with the top of theinsulative layer 21 using chemical mechanical planarization (CMP) techniques, if desired. An optional conductive metal runner can also be provided over theplug 37 using available materials, e.g. aluminum, and methods (not shown inFIG. 4 ). As a result of the method and composition of the invention using the reactant mixture to etch thecontact opening 27, theconductive plug 37 adheres more effectively inside thecontact opening 27. In particular, theprotective layer 35 prevents erosion of theside wall spacers 17 which could materially detract from the performance of theplug 37 and the gate stacks 15. - The following examples illustrate certain preferred embodiments of the invention, but should not be construed as limiting the scope thereof.
- In this example, a self-aligned contact opening was formed in the device illustrated in
FIG. 3 . Plasma etching was conducted in a reaction chamber set at 600 watts, 45 milliTorr operating pressure, and 40 Gauss. Operating temperature was in the range of 0 to 50 degrees C. The following fluorocarbons were introduced into the reaction chamber together with ammonia, at the following flow rates:CF4 18 sccm CHF3 40 sccm CH2F2 13 scccm NH3 4 sccm - Under the foregoing conditions, a self-aligned contact opening was formed in the device shown in
FIG. 3 without etch stop. - In this example, the same operating parameters and reaction conditions were utilized as set forth in Example 1, except that the flow rate of ammonia (NH3) was 2 sccm. Under these conditions, a suitable self-aligned contact opening was also formed without etch stop.
- In this example, the same operating parameters and reaction conditions were utilized as set forth in Example 1, except that the flow rate of ammonia (NH3) was 8 sccm. Under these conditions, loss of etch selectivity to gate stack and sidewall spacer was observed.
- In this example, the same operating parameters and reaction conditions were utilized as set forth in Example 1, except that the flow rate of ammonia (NH3) was 0 sccm. Under these conditions, etch stop was observed.
- The foregoing description is illustrative of exemplary embodiments which achieve the objects, features and advantages of the present invention. It should be apparent that many changes, modifications, substitutions may be made to the described embodiments without departing from the spirit or scope of the invention. The invention is not to be considered as limited by the foregoing description or embodiments, but is only limited by the construed scope of the appended claims.
Claims (24)
1. A method of forming a contact opening in an insulative layer formed over a substrate in a semiconductor device, said method comprising:
etching said insulative layer with an etching composition consisting of ammonia and at least one fluorocarbon so as to form said contact opening, wherein the flow rate ratio of said at least one fluorocarbon to said ammonia is from about 2:1 to about 40:1, and said flow rate of said ammonia is in the range from about 2 sccm to about 6 sccm.
2. The method of claim 1 , wherein said method is performed to produce a self-aligned contact opening, said opening is self-aligned between two adjacent gate stack structures with side wall spacers.
3. The method of claim 1 , wherein said etching includes plasma etching.
4. The method of claim 3 , wherein said etching is performed within a temperature range of about −50 to about 80 degrees Celsius.
5. The method of claim 4 , wherein said etching is performed within a temperature range of about 0 to about 50 degrees Celsius.
6. The method of claim 4 , wherein said etching is performed at an operating pressure of about 25 to about 60 milliTorrs.
7. The method of claim 4 , wherein said etching is performed at an operating pressure of about 40 to about 50 milliTorrs.
8. The method of claim 1 , wherein said etching is performed through a patterned photoresist mask.
9. The method of claim 1 , wherein said fluorocarbon is at least one member selected from the group consisting of fluorinated carbons, fluorohydrocarbons, chlorofluorocarbons and chlorofluorohydrocarbons.
10. The method of claim 9 , wherein said at least one fluorocarbon is at least one member selected from the group consisting of C4F8, C4F6, C5F8, CF4, C2F6, C3F8, CHF3, and CH2F2.
11. The method of claim 10 , wherein said at least one fluorocarbon is at least one member selected from the group consisting of CF4, CHF3, and CH2F2.
12. The method of claim 1 , wherein said method is performed without forming an etch stop.
13. The method of claim 2 , wherein said side wall spacers remain unetched during formation of said self-aligned contact opening.
14. The method of claim 9 , wherein said at least one fluorocarbon and said ammonia are flowed into a reaction chamber containing said semiconductor device such that the flow rate ratio of said at least one fluorocarbon to said ammonia is not less than about 3:1.
15. The method of claim 15 , wherein the flow rate ratio of said at least one fluorocarbon to said ammonia is within the range of about 3:1 to about 20:1.
16. The method of claim 16 , wherein said flow rate ratio is within the range of about 4:1 to about 10:1.
17. The method of claim 11 , wherein said at least one fluorocarbon is at least two members selected from the group of CF4, CHF3, and CH2F2.
18. The method of claim 17 , wherein said at least one fluorocarbon comprises CF4, CHF3, and CH2F2.
19. The method of claim 11 , wherein said at least one fluorocarbon is CF4 which is flowed into a reaction chamber at a flow rate of about 15 to about 20 sccm.
20. The method of claim 17 , wherein said CF4 is flowed into a reaction chamber at a flow rate of about 18 sccm.
21. The method of claim 11 , wherein said at least one fluorocarbon is CHF3 which is flowed into a reaction chamber at a flow rate of about 35 to about 45 sccm.
22. The method of claim 21 , wherein said CHF3 is flowed into a reaction chamber at a flow rate of about 40 sccm.
23. The method of claim 11 , wherein said at least one fluorocarbon is CH2F2 which is flowed into a reaction chamber at a flow rate of about 10 to about 15 sccm.
24. The method of claim 23 , wherein said CH2F2 is introduced at a flow rate of about 13 sccm.
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US7202171B2 (en) * | 2001-01-03 | 2007-04-10 | Micron Technology, Inc. | Method for forming a contact opening in a semiconductor device |
US6846749B1 (en) * | 2001-06-25 | 2005-01-25 | Advanced Micro Devices, Inc. | N-containing plasma etch process with reduced resist poisoning |
US7566929B2 (en) * | 2002-07-05 | 2009-07-28 | Samsung Electronics Co., Ltd. | Nonvolatile memory devices having floating gate electrodes with nitrogen-doped layers on portions thereof |
KR100467019B1 (en) | 2002-07-05 | 2005-01-24 | 삼성전자주식회사 | Flash memory device with self aligned shallow trench isolation structure and method of fabricating the same |
US20070023864A1 (en) * | 2005-07-28 | 2007-02-01 | International Business Machines Corporation | Methods of fabricating bipolar transistor for improved isolation, passivation and critical dimension control |
US8129282B2 (en) | 2006-07-19 | 2012-03-06 | Tokyo Electron Limited | Plasma etching method and computer-readable storage medium |
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Cited By (2)
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US20060017118A1 (en) * | 2004-07-21 | 2006-01-26 | Park Je-Min | Semiconductor device having spacer pattern and method of forming the same |
US10304692B1 (en) | 2017-11-28 | 2019-05-28 | International Business Machines Corporation | Method of forming field effect transistor (FET) circuits, and forming integrated circuit (IC) chips with the FET circuits |
Also Published As
Publication number | Publication date |
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US20020123226A1 (en) | 2002-09-05 |
US7202171B2 (en) | 2007-04-10 |
US20070212885A1 (en) | 2007-09-13 |
US20020123234A1 (en) | 2002-09-05 |
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