JPH09261628A - Image compressor, image expander, and image compander - Google Patents

Abstract

PROBLEM TO BE SOLVED: To relieve the load on an external equipment with respect to a transfer speed. SOLUTION: A compressed data buffer 4 storing tentatively a compressed image signal 13 is interposed between a compression section 2 and an external equipment 9. The compressed data buffer 4 is controlled by a data transfer control section 3 so as to write data in response to a write request from the compression section 2 and to read data in response to a read request from the external equipment 9. Thus, write of a compressed image signal 13 is conducted at a transfer speed specific to the compression section 2 and the read is executed at transfer speed specific to the external equipment 9. Since it is not required to make transfer by the external equipment 9 in synchronism with the operation of the compression section 2, the load of the external equipment 9 with respect to the transfer speed is relieved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image compression device,
The present invention relates to an image decompression device and an image compression / decompression device having both functions, and more particularly, to an improvement for reducing the load on an external device regarding the transfer of compressed data.

[0002]

2. Description of the Related Art FIG. 12 is a block diagram showing the configuration of a conventional image compression apparatus which is the background of the present invention. The conventional device 96 includes a video signal decoder 81, an image data buffer 82, a compression section 83, and a timing generation section 84.
It has. The video signal 11 such as an NTSC signal input from the outside is digitized by the video signal decoder 81. The digitized image signal is temporarily held in the image data buffer 82, and then the compression unit 83.
Read by.

The compression unit 83 compresses the image signal to generate the compressed image signal 13 and outputs it to the external device 80 connected to the outside. The external device 80 is, for example, an image storage device that stores an image signal, a transmission path that transmits an image signal, or the like.

The video signal decoder 81 further extracts horizontal and vertical sync signals from the video signal 11. The timing generation section 84 outputs a control signal for controlling the operation of the image data buffer 82 based on these synchronization signals.

In the conventional device 96, the video signal 11 is compressed in this way and output to the external device 80.

FIG. 13 is a block diagram showing the configuration of an image decompression device which is another conventional device which is the background of the present invention. This conventional device 97 includes a video signal encoder 7
1, a picture data buffer 72, a decompression unit 73, and a timing generation unit 74. The decompression unit 73 decompresses the compressed image signal 13 input from the external device 80. The expanded image signal is stored in the image data buffer 7
2 is temporarily held, and then the video signal encoder 71
Read by.

The video signal encoder 71 reconstructs the video signal 11 from the decompressed digital image signal. The timing generation section 74 outputs a control signal for controlling the operation of the image data buffer 72, and also generates horizontal and vertical synchronization signals and supplies them to the video signal encoder 71.

In the conventional device 97, the compressed image signal 13 is decompressed in this way and output to the outside.

[0009]

Prior art devices 96, 97
Is configured as described above, the external device 80
Need to read the compressed image signal 13 in synchronization with the operation of the compression unit 83 that generates the compressed image signal 13. Further, it is necessary to output the compressed image signal 13 in synchronization with the operation of the decompression unit 73 that decompresses the compressed image signal 13.

The transfer rate of the compressed image signal 13 in the compression section 83 and the decompression section 73 generally changes from time to time depending on the partial compression rate in the screen. Therefore, in order to cope with any change in the compression ratio, the external device 80 was required to have the ability to transfer the compressed image signal 13 at the highest speed required at the moment. For example, when the external device 80 has a transmission path, it is necessary to use a transmission path having a high transmission capacity.

Furthermore, in the conventional device 97, even when the video signal 11 corresponding to a still image is output, the external device 80 has to repeatedly output the compressed image signal 13 of the same screen. As described above, the conventional image compressing device and image decompressing device have a problem in that the external device 80 is required to have high-speed transfer capability and redundant transfer.

The present invention has been made in order to solve the above-mentioned problems in the conventional apparatus, and an image compression apparatus, an image decompression apparatus, and an image decompression apparatus which can reduce the load on an external apparatus when transferring compressed data. An object is to provide an image compression / decompression device having both functions.

[0013]

The apparatus of the first invention is an image compression apparatus for compressing an input image signal and outputting the compressed image signal to an external device. The image signal is compressed to obtain a compressed image signal. Section, a compression data buffer that temporarily holds the compressed image signal interposed between the compression section and the external device, and a write operation and a read operation of the compressed image signal in the compressed data buffer. And a data transfer control unit, wherein the compressed data buffer writes the compressed image signal in response to a write request from the compression unit and in response to a read request from the external device. The compressed data buffer is controlled so as to read the compressed image signal.

The apparatus of the second invention is the image compression apparatus of the first invention, characterized in that the compression section performs compression based on an intra-frame coding algorithm.

According to a third aspect of the present invention, in the image compression apparatus according to the second aspect, the data transfer control unit sets a plurality of banks in the memory space of the compressed data buffer,
The compressed image signal obtained by the compression unit is distributed to and written in each of the plurality of banks for each screen, and the compressed image stored in a bank that is not being written among the plurality of banks. The compressed data buffer is controlled so as to read a signal to the external device.

According to a fourth aspect of the present invention, in the image compression apparatus according to the third aspect, the data transfer control section individually generates addresses for writing and reading for each one of the plurality of banks. A plurality of address generators, a plurality of registers that individually hold information about the addresses generated when each one of the address generators writes, and one of the plurality of address parts is selected, An address selection unit that supplies the address generated by the selected one to the compressed data buffer, and the plurality of address generation units refer to the information held in the plurality of registers. The address is generated at the time of reading.

According to a fifth aspect of the invention, in an image decompression device for decompressing and outputting a compressed image signal input from an external device, a decompression unit for decompressing the compressed image signal to obtain an image signal, and the decompression unit. A compressed data buffer that temporarily holds the compressed image signal, and a data transfer control unit that controls a write operation and a read operation of the compressed image signal in the compressed data buffer. In the data transfer control unit, the compressed data buffer writes the compressed image signal in response to a write request from the external device, and reads the compressed image signal in response to a read request from the decompression unit. Thus, the compressed data buffer is controlled.

A sixth aspect of the invention is the image decompression apparatus of the fifth aspect, wherein the decompression is performed based on an intra-frame coding algorithm.

According to a seventh aspect of the invention, in the image decompression apparatus of the sixth aspect, the data transfer control unit sets a plurality of banks in the memory space of the compressed data buffer,
A bank not being read out is selected from the plurality of banks, and the compressed image signal sent from the external device is set to 1
It is characterized in that the compressed data buffer is controlled so that data is written to each one of the plurality of banks for each screen.

According to an eighth aspect of the present invention, in the image expanding apparatus according to the seventh aspect, the data transfer control section individually generates addresses for writing and reading for each one of the plurality of banks. A plurality of address generators, a plurality of registers that individually hold information about the addresses generated when each one of the address generators writes, and one of the plurality of address parts is selected, An address selection unit that supplies the address generated by the selected one to the compressed data buffer, and the plurality of address generation units refer to the information held in the plurality of registers. The address is generated at the time of reading.

According to a ninth aspect of the invention, in the image decompressing apparatus of the seventh aspect, the data transfer control unit holds the data in one of the plurality of banks in response to an instruction from the external device. The compressed data buffer is controlled so as to repeatedly read the compressed image signal for one screen.

The apparatus of the tenth invention is an image compression / expansion apparatus which compresses an input image signal and outputs the compressed image signal to an external apparatus, and also expands and outputs a compressed image signal input from the external apparatus, A compression / expansion unit including a compression unit that compresses the image signal to obtain the compressed image signal and an expansion unit that decompresses the compressed image signal to obtain the image signal;
A compressed data buffer, which is interposed between the compression / expansion unit and the external device, temporarily holds the compressed image signal, and data for controlling a write operation and a read operation of the compressed image signal in the compressed data buffer. A transfer control unit, wherein the compression unit and the decompression unit perform compression and decompression, respectively, by performing operations that are opposite to each other, and the data transfer control unit includes the compression data decompression unit and the compression decompression unit. Write or read the compressed image signal to or from the compression / expansion unit in response to a request from the external device, and read or write the compressed image signal to or from the external device in response to a request from the external device. The compressed data buffer is controlled so that

An apparatus according to an eleventh invention is the image decompression apparatus according to any one of the fifth to ninth inventions, wherein the compressed image signal is data of variable length code, and the decompression unit is a compressed single signal. To a small-scale decoder for decoding the above data, a large-scale decoder for decoding two or more compressed data having a processing speed characteristic almost half that of the small-scale decoder, and the small-scale decoder and the large-scale decoder. At the same time, input data control means for giving the compressed single or two or more data, and first switching means for switching and outputting the output data from the small-scale decoder and the output data from the large-scale decoder, A delay unit that delays and outputs the output data from the first switching unit by a unit time, and a delay unit from the first switching unit based on a predetermined timing signal. A second switching means for switching and outputting the output data from the force data the delay means,
Timing control means for generating the predetermined timing signal for switching the second switching means from the output data from the delay means to the output data from the first switching means, and the small-scale decoder, The timing control means has a judgment means for judging whether the received data is a single data or two or more data, and the timing control means, based on the judgment signal from the judgment means of the small-scale decoder,
An indefinite timing detection means for detecting indefinite data generated when the first switching means switches from the output data from the small-scale decoder to the output data from the large-scale decoder, and a signal from the indefinite timing detection means. Timing signal output means for outputting the predetermined timing signal to the second switching means on the basis of the predetermined timing signal.

An apparatus according to the twelfth invention is the image compression apparatus according to any one of the first to fourth inventions, wherein the compression section performs a predetermined process on the image signal by a pipeline. The unit detects an effective timing of each pipeline based on the given horizontal synchronizing signal and vertical synchronizing signal and outputs a predetermined enable signal, and the predetermined enable from the enabling unit. And a processing control unit that permits signal processing in the pipeline only when a signal is received and stops signal processing in the pipeline when the predetermined enable signal is not received.

An apparatus according to a thirteenth invention is the image compression apparatus according to any one of the first to fourth inventions, wherein the compression section performs a predetermined process on the image signal by a pipeline. The unit detects the timing at which each pipeline effectively operates based on the given horizontal synchronizing signal and vertical synchronizing signal and outputs a predetermined enable signal; and a signal processing the predetermined enable signal. Enable signal delay means for delaying by the number of stages of the pipeline, and signal processing in the pipeline is permitted only when the enable means or the predetermined enable signal corresponding to each stage from the enable signal delay means is received. Processing control means for stopping signal processing in the pipeline when the predetermined enable signal is not received, Characterized in that it comprises.

An apparatus according to a fourteenth invention is the image decompression apparatus according to any one of the fifth to ninth inventions, wherein the decompression unit performs a predetermined process on the compressed image signal by a pipeline. The decompression unit detects the timing at which each pipeline operates effectively based on the given horizontal synchronizing signal and vertical synchronizing signal and outputs a predetermined enable signal, and the predetermined enabling signal from the enabling unit. And a processing control means for permitting the signal processing in the pipeline only when receiving the enable signal and stopping the signal processing in the pipeline when not receiving the predetermined enable signal.

An apparatus according to the fifteenth invention is the image decompression apparatus according to any one of the fifth to ninth inventions, wherein the decompression unit pipelines a predetermined process for the compressed image signal. An expansion unit detects the timing at which each pipeline operates effectively based on the given horizontal synchronization signal and vertical synchronization signal and outputs a predetermined enable signal, and a signal processing of the predetermined enable signal. Enable signal delay means for delaying by the number of stages of the pipeline, and the signal processing in the pipeline is permitted only when the enable signal or the predetermined enable signal corresponding to each stage from the enable signal delay means is received. However, the processing control hand that stops the signal processing in the pipeline when the predetermined enable signal is not received. Characterized in that it comprises and.

[0028]

BEST MODE FOR CARRYING OUT THE INVENTION

<1. Image Compressing Device> FIG. 1 is a block diagram showing the configuration of the image compressing device according to the embodiment of the present invention. FIG.
As shown in, the device 91 includes a video signal decoder 1, a compression unit 2, a data transfer control unit 3, a compressed data buffer 4, and a timing generation unit 5. When using the device 91, a video signal 11 such as an NTSC signal is input from an external device (not shown) such as a television camera, and another external device 9 is connected. The external device 9 is, for example, an image storage device that stores a compressed image signal, a transmission path that transmits an image signal, or the like.

The video signal decoder 1 receives a video signal 11, which is typically a dynamic image, and the video signal 11
A digital image signal 12 is obtained by demodulating the
Extract 5. The compression unit 2 also obtains a compressed image signal 13 by compressing the digital image signal 12 obtained by the video signal decoder 1. The compression unit 2 compresses an image based on an intra-frame encoding algorithm such as a method based on JPEG.

The timing generator 5 sends a control signal 16 to the compressor 2 based on the synchronization signal 15. The compression unit 2 compresses the digital image signal 12 in synchronization with the control signal 16. The compressed data buffer 4 is a storage medium that temporarily stores the compressed image signal 13, and preferably includes a RAM. The operation of the compressed data buffer 4 is controlled by the data transfer control unit 3.

The data transfer control unit 3 writes the compressed image signal 13 sent from the compression unit 2, and at the same time, the operation compressed image signal 13 temporarily stored is read out to the external device 9. Control the compressed data buffer 4. That is, the compressed data buffer 4 operates from the compression unit 2 to the external device 9 by the function of the data transfer control unit 3.
It functions as a buffer that mediates the transfer of the compressed image signal 13 to and from.

The data transfer control unit 3 receives the screen final data signal 17 and the compressed data generation signal 1 sent from the compression unit 2.
8 and the compressed data read request signal 21 and the bank switching request signal 22 sent from the external device 9, the memory control signal 19 and the memory address signal 20 are output to the compressed data buffer 4. This allows
The compressed data buffer 4 is controlled. The functions of these signals and the internal configuration of the data transfer control unit 3 will be described later.

FIG. 2 is a schematic diagram showing a configuration example of the memory space of the compressed data buffer 4. As shown in FIG. 2, the compressed image signal 13 is stored in the compressed data buffer 4 for each screen. This one-screen compressed image signal 13
The memory area in which is stored is referred to as a bank in this specification. In the example of FIG. 2, the memory space of the compressed data buffer 4 is provided with two banks. The configuration of such a memory space is also determined by the control of the data transfer control unit 3.

FIG. 3 is an explanatory diagram showing the operation of the compressed data buffer 4 illustrated in FIG. As shown in FIG.
One of the banks (bank 1) functions for writing the compressed image signal 13, and the other (bank 2) functions for reading. Moreover, these functions alternate with the passage of time.

That is, while the compressed image signal 13 for one screen sent from the compression unit 2 is written in one bank, the other bank is in a readable state.
At this time, the previously stored compressed image signal 13 for one screen is read out to the external device 9 from the other bank.
By alternately switching the functions of the two banks, writing and reading of the compressed image signal 13 can be performed simultaneously in parallel.

Moreover, the compression unit 2 can write the compressed image signal 13 to the compressed data buffer 4 in accordance with the compression operation, while the external device 9 can read one bank. It suffices to complete the reading of one screen during the period, and it is not necessary to perform the reading operation in synchronization with the operation of the compression unit 2. Therefore, the read operation speed can be averaged, and the external device 9 does not need to read at high speed. That is, the load of the external device 9 on the transfer capability of the compressed image signal 13 is reduced. This also enables the use of a simple transmission path with low transmission capability when the external device 9 has a transmission path, for example.

Although FIG. 2 and FIG. 3 show an example in which the memory space of the compressed data buffer 4 has two banks, in general, a plurality of banks can be configured. For example, when the memory space has three or more banks and writing is performed to one bank, the external device 9
One of the remaining banks was selected according to the request from
The compressed data buffer 4 and the data transfer control unit 3 may be configured so that reading is performed.

A plurality of compressed data buffers 4 may be provided in parallel according to the number of external devices 9. At this time, the compressed image signal 13 is simultaneously written from the compression unit 2 to the plurality of compressed data buffers 4. And
Reading is performed individually from the plurality of compressed data buffers 4 to the plurality of external devices 9. The read operation speed is also set individually according to the required speed of each external device 9.

<2. Image Decompression Device> FIG. 4 is a block diagram showing the structure of the image decompression device according to the embodiment of the present invention. As shown in FIG. 4, this device 92 is provided with the data transfer control unit 3, the compressed data buffer 4, and the timing generation unit 5, similarly to the above-mentioned device 91. Further, the compression unit 2 and the video signal decoder 1 in the device 91 are replaced by a decompression unit 6 and a video signal encoder 7, respectively. further,
The video signal encoder 7 and the timing generator 5 are provided with a sync signal generator 8 for supplying signals.

In the device 92, the compressed data buffer 4 is
It functions to mediate transfer of the compressed image signal 13 from the external device 9 to the decompression unit 6. That is, the data transfer control unit 3
Controls the compressed data buffer 4 such that the compressed image signal 13 sent from the external device 9 is written and the temporarily stored compressed image signal 13 is read out to the decompression unit 6.

The data transfer control unit 3 sends the screen final data signal 17 and the decompression data request signal 2 sent from the decompression unit 6.
3, and the memory control signal 19 and the memory address signal 20 are output to the compressed data buffer 4 based on the expansion data write request signal 24 and the bank switching request signal 22 sent from the external device 9. This allows
The compressed data buffer 4 is controlled.

The sync signal generator 8 generates horizontal and vertical sync signals 15. Further, the timing generation section 5 sends the control signal 16 to the decompression section 6 based on the synchronization signal 15 generated by the synchronization signal generation section 8.

The decompression section 6 reconstructs the digital image signal 12 by decompressing the compressed image signal 13 read from the compressed data buffer 4. The decompression unit 6 executes the decompression operation based on the intra-frame coding algorithm. Further, the decompression operation by the decompression unit 6 is controlled by the control signal
It is performed in synchronization with 6.

The video signal encoder 7 reconstructs the video signal 11 in the form of, for example, an NTSC signal from the reconstructed digital image signal 12 and the synchronizing signal 15 and outputs it to the outside.

When the device 92 and the device 91 are in a pair-usable relationship with each other, that is, by decompressing the compressed image signal 13 obtained by the device 91 by the device 92,
When the video signal 11 has a reconfigurable relationship, the decompressing unit 6 and the compressing unit 2 perform processing opposite to each other. For example, when the compression unit 2 compresses an image based on an algorithm based on JPEG, the corresponding decompression unit 6 executes decompression based on an algorithm based on JPEG. Similarly, the video signal encoder 7 and
The corresponding video signal decoder 1 performs the opposite processing.

The memory space of the compressed data buffer 4 in the device 92 is constructed similarly to the device 91. For example,
The memory space of the compressed data buffer 4 is shown in FIG. The operation is shown in the explanatory diagram of FIG. That is, while the compressed image signal 13 for one screen from one of the two banks (bank 1) is being read by the decompression unit 6, the other bank (bank 2) is in the writable state. At this time, the compressed image signal 13 for one screen is written from the external device 9 to the other bank. By alternately switching the functions of these two banks, writing and reading of the compressed image signal 13 are performed simultaneously in parallel.

The decompression unit 6 can read the compressed image signal 13 from the compressed data buffer 4 in accordance with the decompression operation, while the external device 9 is in the period during which one bank is writable. It is only necessary to complete the writing for one screen, and it is not necessary to perform the writing operation in synchronization with the operation of the decompression unit 6. Therefore, the speed of the write operation can be averaged, and the external device 9 does not need to write at a high speed. That is, the load of the external device 9 on the transfer capability of the compressed image signal 13 is reduced. This also enables the use of a simple transmission path with low transmission capability when the external device 9 has a transmission path, for example.

In addition, the data transfer control unit 3 from the external device 9
It is also possible to repeatedly read the compressed image signal 13 for one screen held in one bank to the decompression unit 6 in response to the instruction. At this time, the external device 9 has the same 1
Even if the compressed image signal 13 for the screen is not repeatedly written to the compressed data buffer 4, the video signal 11 corresponding to the still image is reconstructed. That is, when decompressing a still image, the external device 9 does not need to repeatedly supply the same compressed image signal 13.

Thus, the device 92 also eliminates the redundancy in the write operation of the external device 9. This also contributes to reducing the load on the external device 9 regarding the transfer of the compressed image signal 13.

Although FIG. 5 shows an example in which the memory space of the compressed data buffer 4 has two banks, generally, like the device 91, a plurality of banks can be formed. Further, like the device 91, it is possible to provide a plurality of compressed data buffers 4 in parallel according to the number of external devices 9.

<3. Data Transfer Control Unit> Next, the device 9
An example of the configuration of the data transfer control unit 3 that is commonly provided for the No. 1 and 92 and its operation will be described in detail. 6 is shown in FIG.
6 is a block diagram showing a configuration of a data transfer control unit 3 that realizes the operation of FIG. As shown in FIG. 6, the data transfer control unit 3 includes an access arbitration unit 30, a memory address generation unit 31, and a memory control timing generation unit 39.

The access arbitration unit 30 accesses the compressed data buffer 4 between the compression unit 2 (or decompression unit 6) and the external device 9 (that is, write or read operation).
Mediation of This arbitration is performed by the compressed data generation signal 18 (or the expanded data request signal 23) sent from the compression unit 2 (or the expanded unit 6) and the compressed data read request signal 21 (or the expanded data write signal) sent from the external device 9. It is performed based on the request signal 24).

The compressed data generation signal 18 (or decompressed data request signal 23) is a signal for instructing the compressed data buffer 4 to perform a write (or read) operation, and is written by the compression unit 2 (or decompression unit 6). Or it is sent every time a read operation is performed. In addition, the compressed data read request signal 21 (or the expanded data write request signal 24)
Is a signal instructing the compressed data buffer 4 to perform a read (or write) operation, and is sent from the external device 9 every time the external device 9 performs a read (or write) operation.

Further, the memory control timing generator 39
Responds to the result of access arbitration by the access arbitration unit 30 to generate a memory control signal 19 given to the compressed data buffer 4, that is, a signal for controlling a write operation and a read operation. Furthermore, the memory address generation unit 31
Is a device portion that generates the memory address signal 20 to be given to the compressed data buffer 4. The memory address generation unit 31 includes registers 32, 33, 35, 36, address generation units 34, 37, and an address selection unit 38.

The registers 32 and 35 have a storage medium for temporarily holding the value of the data length of the compressed image signal 13 for one screen. This data length is calculated by the address generators 34 and 37 as described later. However, in the image decompressing device 92, the data length value is directly transmitted from the external device 9 to the data transfer control unit 3, and the data transfer control unit 3 is controlled so that this value is held in the registers 32 and 35. You may comprise.

The registers 33 and 36 are storage media for temporarily storing the value of the head address of the compressed image signal 13 for one screen. The value of this start address is set by the external device 9.

The address generators 34 and 37 use the register 3
The memory address signal 20 designating the address of the compressed data buffer 4 is generated based on the data lengths held in 2, 35, the start address held in the registers 33, 36, and the screen end data signal 17. The screen final data signal 17 is a signal for notifying the end of one screen, and is sent from the compression unit 2 (or the expansion unit 6) every time the compression (or expansion) of one screen is completed.

The address selecting section 38 uses the screen final data signal 17, the bank switching request signal 22, and the arbitration result of the access arbitration section 30 to generate two memory address signals generated by the address generating sections 34 and 37. Two
One of 0 is selected and output. As shown in FIG. 6, two address generators 34 and 37 are provided to generate an address for every two banks in the memory space of the compressed data buffer 4. That is, the address generators 34 and 37 individually manage the two banks.

The address is calculated so as to be incremented with respect to the head address each time the compressed data buffer 4 is accessed. In the device 91,
When the screen final data signal 17 is input, it is initialized to the start address. In device 92, register 3
When the increment is performed until the data length is held in 2, 35, the initial address is initialized.

Depending on the role of the bank managed by the two address generators 34, 37, these address generators 3
When one of 4, 37 generates an address for writing by the compression unit 2 (or reading by the decompression unit 6), the other generates an address for reading (or writing) from the external device 9. Then, the address generation unit 3
These functions of 4, 37 are also switched as the roles of the banks they manage are switched alternately.

This switching is instructed by the bank switching request signal 22. Further, since this switching is performed in synchronization with the writing of the final data of the compressed image signal 13 for one screen, the external device 9 does not need to accurately measure the timing of sending the bank switching request signal 22.

Since the functions of the address generators 34 and 37 are switched in accordance with the switching of the role of the bank, each 1 of the address generators 34 and 37 manages both writing and reading of one bank. Will be done. Therefore, the information regarding the storage location of the compressed image signal 13 for one screen written in the banks managed by each is held by the address generation units 34 and 37, and is utilized at the time of reading.

This switching is similarly performed in the device 92. Further, in the device 92, the bank switching request signal 2
Addresses are generated so that the compressed image signal 13 of the same screen is read repeatedly until 2 is transmitted. Therefore, the external device 9 uses the compressed image signal 13 corresponding to the still image.
Is transmitted, the transmission of the bank switching request signal 22 may be stopped during that period. By doing so, the external device 9 does not repeatedly send the same compressed image signal 13 and the compressed image signal 1 for the same one screen.
A decompression of 3 is performed iteratively. As a result, the video signal 11 as a still image is obtained from the video signal encoder 7.

As in the case of normal memory access, by directly designating an address from the external device 9,
The data transfer control unit 3 may be configured such that the compressed image signal 13 is read and written by the external device 9.

FIG. 7 is a block diagram showing a configuration example of the address generation unit 34 on behalf of the address generation units 34 and 37. First, an example in which the address generator 34 is incorporated in the device 91 will be described.

The address generator 34 includes an offset register 41, an adder 42, and a switch 43. To the bank managed by the address generation unit 34, the compression unit 2
When the writing is performed by, the offset register 41 initializes the held value to zero in response to the screen final data signal 17 corresponding to the break of the compressed image signal 13 for each screen. Then, in response to the compressed data generation signal 18, the held value is incremented by one. This operation is continued until the next screen final data signal 17 is input.

The offset register 41 holds a value corresponding to the data length of the compressed image signal 13 for one screen when the screen final data signal 17 is transmitted. Therefore, the switch unit 43 transfers the value held by the offset register 41 to the register 32 in response to the screen final data signal 17.

The adder unit 42 generates the memory address signal 20 by adding the value of the head address supplied from the register 33 and the value held by the offset register 41. As a result, one screen of compressed image signal 1
3 is written in the memory space in the range corresponding to the data length from the head address held in the register 33.

When reading from the bank managed by the address generator 34 to the external device 9, first, the bank managed by the address generator 34 is switched to the read side by the bank switching request signal 22. At this time, the value held in the registers 32 and 33 indicates the storage location of the compressed image signal 13 for one screen to be read.

The offset register 41 increments the value held each time the compressed data read request signal 21 is transmitted from the external device 9, and when the bank switching request signal 22 is transmitted, it responds to this. Initialize to zero. Further, the reading is performed the number of times corresponding to the data length held by the register 32. The adding unit 42
The point that the memory address signal 20 is generated by adding the value of the start address held by the register 33 and the value held by the offset register 41 is the same as in writing.

By generating the read address in this manner, the compressed image signal 13 for one screen written in the memory space in the range corresponding to the data length from the start address held in the register 33 is read. Is done.

Next, an example in which the address generator 34 is incorporated in the device 92 will be described. When the compressed image signal 13 is written from the external device 9 to the bank managed by the address generation unit 34, the value of the data length of the compressed image signal 13 for one screen is input to the register 32. The offset register 41 increments the held value in response to the decompression data write request signal 24 that is sent each time the compressed image signal 13 is written from the external device 9 to the compressed data buffer 4. After that, when the bank switching request signal 22 is transmitted, the bank managed by the address generation unit 34 switches from the write operation to the read operation.

The value held by the offset register 41 is
It is initialized after the value becomes equal to the data length held in the register 32. As a result, until the bank switching request signal 22 is transmitted, the same compressed image signal 13 for one screen is output from the bank managed by the address generator 34.
It is continuously supplied to the extension section 6.

In FIG. 7, the address generator 34
An example has been shown in which not only the access of the compression unit 2 (or the decompression unit 6) but also the address for the access of the external device 9 is generated. However, when the external device 9 itself has a function of designating an address, an address for accessing the external device 9 is not generated,
It is also possible to configure the devices 91 and 92.

Although FIG. 6 shows an example in which there are two banks to be managed, the management of three or more banks can be similarly performed by expanding the configuration of FIG.

<4. Image compression / decompression device> Image compression device 91
The image expansion device 92 is usually used in combination. Here, a device 9 suitable for such use
An example of an image compression / decompression device in which 1 and the device 92 are incorporated will be described.

FIG. 8 is a block diagram showing a configuration example of the image compression / decompression device. The device 93 includes a compression / expansion unit 10. The compression / expansion unit 10 includes a compression unit 2 and an expansion unit 6. Moreover, the compression unit 2 and the expansion unit 6 are
It is configured to execute operations based on mutually opposite algorithms. Further, the device 93 further includes compressed data buffers 4A and 4B each having the same configuration as the compressed data buffer 4.

In the device 93, the video signal 11 inputted to the video signal decoder 1 from the outside can be compressed and output to the external device 9 in the form of the compressed image signal 13 and the external device 9 can also It is also possible to decompress the sent compressed image signal 13 and output it as the video signal 11 from the video signal encoder 7. That is, the device 93 has both functions of the devices 91 and 92. In addition, since the common device part is shared by both devices, the cost is lower than when both devices are manufactured individually.

Although FIG. 8 shows an example in which the two compressed data buffers 4A and 4B are provided, the compressed data buffer can be shared by the compressing unit 2 and the decompressing unit 6, so that it is generally a single unit. Only the compressed data buffer 4 of 4 may be provided. In the example of FIG. 8, since two compressed data buffers 4A and 4B are provided, a plurality of external devices 9 can be connected.

The compressed image signals 13 for a large number (generally a plurality) of screens obtained by compression by the compression unit 2 are stored in the compressed data buffers 4A and 4B, and a specific screen is externally stored. It is also possible to arbitrarily select it in accordance with the instruction from, to expand the video signal 11 by the expansion unit 6 to reconstruct it, and output it as a still image. That is, the external device 9
It is also possible to use the device 93 as if it were an independent image storage device, without connecting the.

As described above, the compressed data buffers 4A, 4
B can be used not only for the purpose of buffering between the compression unit 2 (or decompression unit 6) and the external device 9, but also as a medium for storing the compressed image signal 13. This is the same even when a single compressed data buffer 4 is provided instead of the compressed data buffers 4A and 4B.

<5. General Structure of Compressing Unit 2 and Expanding Unit 6> In the above description, in the compressing unit 2 and the expanding unit 6,
Although an example in which an image is compressed and decompressed based on an intraframe coding algorithm has been shown, the present invention performs compression and decompression based on an interframe coding algorithm that also considers correlation between frames. It can also be applied to a device.

However, in the case of intra-frame coding, it is not necessary to consider the correlation between frames, so that it is not necessary to provide a frame buffer, and there is an advantage that the compression and decompression operations are performed at high speed. to be born.
This also enables bidirectional communication using the external device 9 as a transmission path.

In the case of the intra-frame encoding, the compressed image signal 13 is further held in the compressed data buffer 4 on a screen-by-screen basis, so that FIG. 2, FIG. 3, and FIG. 5 to FIG.
As illustrated in, the control by the data transfer control unit 3 becomes simple. In particular, since it is possible to cut out one screen of the compressed image signal 13, it is possible to eliminate the redundancy of transfer of the external device 9 when outputting a still image, as described above.

<6. Preferable Example of Decompression Unit 6> Next, a desirable configuration of the decompression unit 6 when the compressed image signal 13 handled by the decompression unit 6 is a variable length code will be described. A Huffman code obtained based on Huffman coding will be taken as an example of the variable-length code to be processed by the decompression unit 6, but the same configuration is applicable to general variable-length codes.

<6-1. Principle> In general, the same data is often continuous in image data, and therefore the difference between mutually continuous data is often “0”. Especially,
In the case of the discrete cosine transform (DCT) processing, since the data are often concentrated in a specific area (for example, a low frequency area), the above-mentioned difference is extremely high in percentage. For example, when the difference is “0005” (1), the run length of “0” (hereinafter referred to as “0 run length”) is “3”, and then “5” (that is, other than “0”). Data) will be assigned, and Huffman codes will be assigned two-dimensionally. in this case,
In order to decode the data of "3" which is 0 run length and the data of "5" which comes next,
In the case of the sequence shown in (1) above, four data can be processed by one decoding.

"2134" (2) On the other hand, like the sequence shown in (2) above, when data other than "0" is continuous as the difference data, that is, when the 0 run length is "0", it should be decoded. The data is “2”,
Only one piece of data can be processed for one decoding such as "1", "3", "4".

Considering these facts, it can be seen that the processing speeds are at least doubled depending on whether the 0 run length is "0" or not. That is, when the 0 run length is “1” or more, two or more data are decoded at one time, so even if two cycles are taken for memory lookup, the final data output timing is once for each data. This means that there is no time difference in decoding timing. Then, as described above, the data other than "0" is continuous only in a specific area such as a low frequency area, so that the processing is biased depending on whether or not the 0 run length is "0". It can be said that it is desirable to improve the processing speed.

In consideration of this, the decompression unit 6 of this embodiment first determines whether the 0 run length is "0" or "1".
It is detected whether it is the above or not, and only the specific area in which the 0 run length is "0" is processed by the high-speed hardware decoder, and the processing of the path different from the case where the 0 run length is "1" or more is performed. Thus, the processing speed is improved by increasing the speed of the decoder as compared with a conventionally known device that relies on the processing speed of the memory lookup.

<6-2. Configuration> FIG. 9 shows the configuration of a decoding processing unit using 0 run length data, which is provided in the decompression unit 6 of this embodiment. In FIG. 9, reference numeral 51 is an input data control block (input data control means) that determines the data to be decoded next in the variable length data.

Reference numeral 52 is a hardware decoder (small-scale decoder: hereinafter referred to as HW decoder) capable of high-speed processing for decoding only Huffman code corresponding to 0 run length data "0". The H / U signal (determination signal) which is an output signal from the HW decoder 52 is a signal for indicating whether or not the internal data of the HW decoder 52 is hit.

Specifically, as shown in FIG. 10B, a High signal is output when the internal data is hit, and a Low signal is output when the internal data is not hit. In order to perform such processing, inside the HW decoder 52, an internal data storage means (memory) 52a for storing internal data as a reference, and the internal data storage means 52a.
Of the Huffman data from the input data control block 51 and a collating means (comparator: determining means) 52b.

Further, 53 is a memory (table: large-scale decoder) for decoding a Huffman code in which 0 run length is assigned to 1 or more, and 54 is a HW decoder 52 based on the H / U signal from the HW decoder 52.
A first multiplexer (first switching means: hereinafter referred to as a first MUX) for selecting the composite data from the memory 53 and the composite data from the memory 53, and 55 is based on the 0 run length data decoded in the memory 53. A run length counter that counts 0 run lengths in order to delay the data output timing by the number of 0 run lengths,
Reference numeral 56 is a data enable generation circuit that generates a flag indicating whether or not to perform the decoding process of the next data based on the H / U signal of the decoder and the output of the 0 run length counter.

Furthermore, in 57, when the Huffman data from the input data control block 51 does not hit the internal data of the HW decoder 52, the access speed of the memory 53 is slow, so that the output data becomes indefinite. 10 (see (F) in FIG. 10), an undefined timing detection circuit (undefined timing detection means) that detects this and generates a flag (see (E) in FIG. 10) for controlling the data output timing. is there.

Decoded data 58 calculates auxiliary data for calculating the amount of data decoded so far from the decoded data output from the first MUX 54 and outputting compressed data to be decoded next. Quantity calculation circuit, 59, 6
Reference numerals 0, 61 and 62 denote delay devices (delays) for delaying the data string by one cycle of the clock signal CK, and 63 denotes delay device 61 (delay means) based on the timing signal from the delay device 60 (timing signal output means). ) From the output data from the first MUX 54 to the output data from the first MUX 54 (second switching means:
Hereinafter referred to as the second MUX).

The indefinite timing detection circuit 57 and the delay device 60 constitute a timing control means for generating a predetermined timing signal for switching the second MUX 63.

<6-3. Operation> The processing procedure of the decompression unit 6 having the above configuration will be described. FIG. 10 is a timing chart showing the operation of the image compression / decompression device of this embodiment. The data shown in FIG. 10A is the input data control block 51.
Data 0, the 0 run length of data a is “0”, the 0 run length of data b is “1”, and the data c is
It is assumed that the 0 run length of is 0 and the 0 run length of the data d is 2.

First, when the data a in FIG. 10A is output from the input data control block 51, it is simultaneously input to the HW decoder 52 and the memory 53 as shown in FIG. Here, the comparison means (comparator) in the HW decoder 52 detects whether the received Huffman data a hits the internal data of the decoder.

When the data a hits the internal data of the HW decoder 52, it is set as a H / U signal ((B) in FIG. 10) as a flag indicating that the data is hit.
The signal is output, and the decoded data that has been decoded (data A in (C) of FIG. 10) is output. On the other hand, when the 0 run length of the data a is “1” or more, the data a does not hit the internal data of the HW decoder 52, and therefore H
The Low signal is output as the / U signal ((B) in FIG. 10). The memory 53 always decodes the data a and outputs the decoded data.

When the first MUX 54 is notified by the HW decoder 52 that a hit has occurred, the first MUX 54 outputs Hi as an H / U signal.
The gh signal is input, and accordingly the HW decoder 5
Select the composite data from 2. On the other hand, if there is no hit, the Low signal is input as the H / U signal, and the decoded data from the memory 53 is selected accordingly. Further, the 0 run length data output from the memory 53 is input to the 0 run length counter 55, and a process of delaying the timing of decoding the next data through the data enable generation circuit 56 by the number of 0 run lengths is performed.

On the other hand, the decoded data amount calculation circuit 58 is
The amount of data decoded so far is calculated from the decoded data output from the MUX 54, and auxiliary data for outputting compressed data to be decoded next is created. Second M
The UX 63 embeds correct data in accordance with the timing (High signal of (E) in FIG. 10) detected by the indefinite timing detection circuit 57 to create final decoded data (data of (H) in FIG. 10). A).

The above is the process for the data a in (A) of FIG. 10. However, since the lookup of the memory 53 has two cycles, the data a is output, and the subsequent cycle is the same as in FIG. In (B), it becomes indefinite as shown between data A and data B. That is, the timing at which the data b of (A) is decoded (the data B of (B) in FIG. 10) becomes the second cycle after the data A. In other words, if the 0 run length is "1" or more,
One cycle will occur for an indefinite period.

Therefore, the entire data string is delayed by one cycle by the delay device (delay) 61, and the portion of the indefinite period subjected to the delay processing (output from the delay device 61: (F) in FIG. 10). By embedding the data B (output from the first MUX 54: (C) in FIG. 10) at a timing that does not apply delay processing to the
It is possible to output at the same speed as the cycle of the decoder 52.

When the 0 run length is "2" or more as in the data d of (A) in FIG. 10, the undefined timing detection circuit 57 in (E) of FIG. The output from the delay device 61 becomes indefinite as shown in (F) of FIG. 10 for the data one cycle after the detection of (when there is no hit at 52). The data following the indefinite data of (F) in FIG. 10 is data D and data D. Therefore, in the indefinite data part,
By embedding the data D by performing the same processing as that for the data B, the data string relating to the data D can be output at the same speed as the cycle of the HW decoder 52.

As described above, in the decompression unit 6 of this embodiment, the HW decoder 52 which decodes the code when the 0 run length is "0" must output the decoded data within 1 clock. The memory 53 that decodes 0 run lengths of 1 or more may output data within 2 clocks. Since the HW decoder 52 used here is for high-speed processing corresponding to the Huffman code only when the 0 run length is "0", the circuit scale can be small and the processing can be made extremely fast.

The expansion section 6 of this embodiment is provided with the devices 92,
Since the compressed data buffer 4 and the data transfer control unit 3 are present when incorporated into the external device 93, the external device 9 can be used despite the high processing speed of the expansion unit 6, especially the peak speed.
Similarly, the same high transfer rate is not required, and there is an advantage that the load on the external device 9 is light. That is,
In the devices 92 and 93, the compressed data buffer 4 and the data transfer control unit 3 are particularly effective when the decompression unit 6 of this embodiment is provided.

<6-4. Modified Example> In this embodiment, the decoder and the memory are disassembled depending on the run length of “0” and “1” or more. It goes without saying that other division methods can be applied.

<7. Other Preferred Examples of Compressing Unit 2 and Expanding Unit 6> Next, preferred examples of the configurations of the compressing unit 2 and the expanding unit 6 when they execute pipeline processing will be described. For example, processing based on a JPEG-based algorithm is a typical example of pipeline processing.

<7-1. Configuration> FIG. 11 is a block diagram showing the configuration of the compression / expansion unit 10 of this embodiment. FIG.
, 103-1, 103-2, 103-3 are various signal processing devices inside the compression / expansion unit 10, and 104 is data processed by the signal processing devices 103-1, 103-2, 103-3 in the preceding stage. The data enable generation circuit 106 determines whether to reflect the output of each subsequent pipeline.
The internal decision device (processing control means) of the compression / expansion unit 10 for making a decision based on the data enable signal from the internal expansion device 105, 105a is an internal delay device (register of the compression / expansion unit 10 for delaying the internal signal from the internal decision device 104 by one clock ) 1
Reference numeral 05b denotes a data enable signal from the data enable generation circuit 106, which is provided to the signal processing device 1 at each stage of the pipeline.
An internal delay device (enable signal delay means: register) of the compression / expansion unit 10 that delays by one clock corresponding to the number of stages of 03-1, 103-2, 103-3, and 106 is an external HSYNC signal (horizontal synchronization). Signal) and VSY
A data enable generation circuit (enable means) that generates a data enable signal for enabling only a period of valid data based on an NC signal (vertical synchronization signal).

Here, internal decision device 104 permits signal processing in the pipeline only when it receives the data enable signal from data enable generation circuit 106, and signals in the pipeline when it does not receive the data enable signal. A general multiplexer is used to stop the processing. One of the pair of input terminals is connected to the output terminal of the signal processing device 103-1, 103-2, 103-3 at the preceding stage, and the other is connected to the subsequent terminal. Feedback connection to the output terminal of the internal delay device 105a.

<7-2. Operation> A processing method of the compression / expansion unit 10 having the above configuration will be described. First, at the time of compression, the data enable generation circuit 106 causes the HSYNC signal and the VSYNC signal.
A data enable signal is generated based on the NC signal only during a period when the input video signal is valid. The signal processing devices 103-1, 103-2, 103-3 in the compression device sequentially process the input image data by pipeline processing.
The internal determination device 104 of each stage determines whether to output to the next stage or retain the previous data.

In other words, the data is processed only when the data of each stage is valid, and when not, the internal delay device 105a of each stage holds the data until the next valid signal. By performing such processing, it is possible to compress only an effective input video signal.
Next, I will describe the processing during decompression.

On the other hand, during the decompression process, the timing at which the video signal is output is delayed by the number of pipeline stages after the decompression process is started. That is, HSYNC
When it is attempted to output the expanded data in accordance with the signal and the VSYNC signal, the data enable generation circuit 106 may output the data enable signal so as to start the processing by the number of pipeline stages before the timing of outputting the valid data. Normally, the video signal contains a considerable amount of invalid data, so even if there are a few pipeline stages,
Such processing is possible without any problems.

In the compression / expansion unit 10 of this embodiment, or in the compression unit 2 and the expansion unit 6 which are its constituents, the peak speed becomes particularly high. Since the buffer 4 and the data transfer control unit 3 are present, there is an advantage that the external device 9 is not required to have a similar high transfer rate and the load on the external device 9 is light. That is, the device 9
In Nos. 2 and 93, the compressed data buffer 4 and the data transfer control unit 3 are particularly effective when the compression unit 2 or the decompression unit 6 of this embodiment is provided.

[0115]

In the device of the first aspect of the present invention, the compressed data buffer is interposed between the compression unit and the external device, and the compressed data signal is written by the compression unit by the function of the data transfer control unit. And reading by an external device
It is done according to each request. Therefore, the writing of the compressed image signal is performed at the transfer rate unique to the compression unit, and the reading is performed at the transfer rate unique to the external device. That is, the external device does not need to transfer the compressed image signal in synchronization with the operation of the compression unit. Therefore, the external device does not need to have a high-speed transfer capacity corresponding to the maximum transfer speed at the moment of the compression unit, and the load of the external device on the transfer capacity is reduced.

In the apparatus of the second invention, since the compression section performs compression based on the intra-frame coding algorithm,
The compression operation is performed at high speed. Therefore, it may be suitable for bidirectional communication. Further, since the compressed data buffer can hold the compressed image signal on a screen-by-screen basis, the control by the data transfer control unit becomes simple.

In the device of the third aspect of the invention, the compressed image signal is distributed to each one of the plurality of banks in the memory space of the compressed data buffer for each screen, and the bank in which writing is performed and the bank in which reading is performed are performed. The banks are adjusted so that they do not overlap. That is, with simple control, writing and reading can be performed at individual speeds without interfering with each other.

In the device of the fourth aspect of the invention, an address generator for generating an address is provided for each bank, and the information on the address of the compressed image signal written in each bank is:
Since it is used for reading, an address can be easily generated when reading the written compressed image signal.

In the device of the fifth invention, the compressed data buffer is interposed between the decompression unit and the external device, and
By the function of the data transfer control unit, writing of the compressed image signal by the external device and reading by the decompression unit are performed according to the respective requests. Therefore, the writing of the compressed image signal is performed at the transfer rate unique to the external device, and the reading is performed at the transfer rate unique to the decompression unit. That is, the external device does not need to transfer the compressed image signal in synchronization with the operation of the decompression unit. Therefore, the external device does not need to have a high-speed transfer capacity corresponding to the maximum transfer speed at the moment of the expansion section, and the load of the external device on the transfer capacity is reduced.

In the apparatus of the sixth invention, the decompression unit decompresses based on the intra-frame coding algorithm.
The expansion operation is performed at high speed. Therefore, it may be suitable for bidirectional communication. Further, since the compressed data buffer can hold the compressed image signal on a screen-by-screen basis, the control by the data transfer control unit becomes simple.

In the device of the seventh invention, the compressed image signal is distributed to each one of the plurality of banks in the memory space of the compressed data buffer for each screen, and the bank to which writing is performed and the bank to which reading is performed are performed. The banks are adjusted so that they do not overlap. That is, with simple control, writing and reading can be performed at individual speeds without interfering with each other.

In the device of the eighth invention, an address generator for generating an address is provided for each bank, and information on the address of the compressed image signal written in each bank is:
Since it is used for reading, an address can be easily generated when reading the written compressed image signal.

In the device of the ninth invention, 1 stored in one of the plurality of banks in response to an instruction from an external device.
Since the compressed image signal for the screen is repeatedly read, the external device does not need to repeatedly send the same compressed image signal for one screen when outputting a still image. That is, redundancy in data transfer of an external device when outputting a still image is eliminated. This contributes to further reducing the data transfer capability of the external device.

The apparatus of the tenth invention incorporates the image compressing apparatus and the image decompressing apparatus of the present invention, so that the functions of both can be obtained simultaneously. The image compression device and the image decompression device are often used in a pair, and this device is suitable for such a normal use form.

In the apparatus of the eleventh aspect of the invention, the decompression unit has a small-scale decoder and a large-scale decoder, detects an indeterminate timing of indeterminate data generated during processing by a large-scale decoder having a slow processing speed, and at that time, detects a predetermined timing. Is output to the second switching means, and the undelayed output data from the first switching means is embedded in the indefinite timing delayed by the delay means. When it is 1, the data is decoded by a small-scale decoder having a high processing speed, and the data is output at high speed. On the other hand, when there are two or more data to be decoded, the large-scale decoder decodes the data and the delay means is used. By embedding the undelayed output data from the first switching means in the delayed indefinite timing, the finally output data string is And amortization, to prevent damage to the data resulting from slow processing speed of large-scale decoder. As a result, the processing speed of the entire expansion unit can be relatively increased. Therefore, it is possible to increase the processing speed at the time of decoding / decompressing the variable-length code nearly twice as much as that of a conventionally known device, and it is possible to deal with a video signal which has been difficult to perform in real time until now. There is an effect that it becomes possible.

In addition, since this apparatus further includes the compressed data buffer and the data transfer control section, even if the processing speed of the decompression section, especially the peak speed, is high, a similar high transfer rate to the external apparatus is not achieved. It is not required and the burden on the external device is light. That is, in this device,
The compressed data buffer and the data transfer control unit exert its effect particularly remarkably.

In the twelfth aspect of the invention, the enable means provided in the compression section detects the timing at which each pipeline effectively operates based on the horizontal synchronizing signal and the vertical synchronizing signal, and outputs a predetermined enable signal. Then
The processing control means permits the signal processing in the pipeline only when receiving the predetermined enable signal from the enabling means, and stops the signal processing in the pipeline when not receiving the predetermined enable signal.

Therefore, the compression section can input and output only the effective portion of the video signal in synchronization with the horizontal and vertical synchronizing signals, and therefore can handle the video signal without the frame buffer and FIFO. That is, an inexpensive image compression device can be realized. In addition, since the valid period and invalid period can be clarified in the signal input / output, the data control can be made very simple, and the compressed data can be easily switched during the expansion. is there.

In addition, the peak speed of the processing is particularly high in the compression section, but since this apparatus is further provided with the compressed data buffer and the data transfer control section, a similar high transfer rate is required for the external apparatus. In addition, the burden on the external device is light. That is, in this device, the compressed data buffer and the data transfer control unit particularly exhibit their effects.

In the apparatus of the thirteenth invention, the compression section delays the predetermined enable signal by the number of stages of the signal processing pipeline in the enabling means and adjusts the timing, while the processing control means performs the predetermined enable signal. The signal processing in the pipeline is permitted only when the signal is received, and the signal processing in the pipeline is stopped when the predetermined enable signal is not received. In this way, since the processing of each pipeline is operated only during the period when valid data should be processed, it is very easy to input / output only the data of the valid part at an appropriate timing according to each stage. As a result, the timing control becomes extremely easy.

Further, although the peak speed of the processing is particularly high in the compression section, since this apparatus is further provided with the compressed data buffer and the data transfer control section, a similar high transfer rate is required for the external apparatus. In addition, the burden on the external device is light. That is, in this device, the compressed data buffer and the data transfer control unit particularly exhibit their effects.

In the apparatus of the fourteenth invention, the enable means provided in the decompression unit detects the timing at which each pipeline effectively operates based on the horizontal synchronizing signal and the vertical synchronizing signal, and outputs a predetermined enable signal. Then
The processing control means permits the signal processing in the pipeline only when receiving the predetermined enable signal from the enabling means, and stops the signal processing in the pipeline when not receiving the predetermined enable signal.

Therefore, since the decompression unit can input / output only the effective portion of the video signal in synchronization with the horizontal and vertical synchronizing signals, it is possible to handle the video signal without the frame buffer and FIFO. That is, an inexpensive image expansion device can be realized. In addition, since the valid period and invalid period can be clarified in the signal input / output, the data control can be made very simple, and the compressed data can be easily switched during the expansion. is there.

Moreover, the peak speed of the processing is particularly high in the decompression unit, but since this device is further provided with the compressed data buffer and the data transfer control unit, the same high transfer speed is required for the external device. In addition, the burden on the external device is light. That is, in this device, the compressed data buffer and the data transfer control unit particularly exhibit their effects.

In the apparatus of the fifteenth invention, the decompression unit delays the predetermined enable signal by the number of stages of the signal processing pipeline in the enabling means and adjusts the timing, while the processing control means performs the predetermined enable signal. The signal processing in the pipeline is permitted only when the signal is received, and the signal processing in the pipeline is stopped when the predetermined enable signal is not received. In this way, since the processing of each pipeline is operated only during the period when valid data should be processed, it is very easy to input / output only the data of the valid part at an appropriate timing according to each stage. As a result, the timing control becomes extremely easy.

Further, although the decompression section has a particularly high peak processing speed, this apparatus is further provided with a compressed data buffer and a data transfer control section, so that a similar high transfer rate is required for the external apparatus. In addition, the burden on the external device is light. That is, in this device, the compressed data buffer and the data transfer control unit particularly exhibit their effects.

[Brief description of drawings]

FIG. 1 is a block diagram of an image compression apparatus according to an embodiment.

2 is a schematic diagram of a memory space of a compressed data buffer of the apparatus of FIG.

FIG. 3 is an explanatory diagram showing an operation of a compressed data buffer of the apparatus shown in FIG.

FIG. 4 is a block diagram of an image expansion device according to an embodiment.

5 is an explanatory diagram showing an operation of a compressed data buffer of the apparatus shown in FIG.

6 is a block diagram of a data transfer control unit of the apparatus of FIGS. 1 and 4. FIG.

FIG. 7 is a block diagram showing an internal configuration of an address generator of FIG.

FIG. 8 is a block diagram of an image compression / decompression device according to an embodiment.

FIG. 9 is a block diagram showing a preferable configuration of an extension unit.

10 is a timing chart explaining the operation of the decompression unit in FIG.

FIG. 11 is a block diagram showing a preferable configuration of a compression / expansion unit.

FIG. 12 is a block diagram of a conventional image compression device.

FIG. 13 is a block diagram of a conventional image expansion device.

[Explanation of symbols]

 2 compression unit 3 data transfer control unit 4 compressed data buffer 6 decompression unit 9 external device 11 video signal (image signal) 13 compressed image signal 34, 37 address generation unit 32, 33, 35, 36 register 38 address selection unit 51 input data Control block 52 HW decoder 52a Internal data storage means 52b Collating means 53 Memory 54 First multiplexer 55 Run length counter 56 Data enable generation circuit 57 Undefined timing detection circuit 58 Decoded data amount calculation circuit 59, 60, 61, 62 Delay device 63 Second multiplexer 103-1, 103-2, 103-3 Signal processing device 104 Internal determination device 105a, 105b Internal delay device 106 Data enable generation circuit

Claims (15)

[Claims] 1. An image compression apparatus for compressing an input image signal and outputting the compressed image signal to an external device, comprising: a compression unit that compresses the image signal to obtain a compressed image signal; and the compression unit and the external device. A data transfer control unit that controls the writing operation and the reading operation of the compressed image signal in the compressed data buffer by interposing therebetween a compressed data buffer that temporarily holds the compressed image signal; In the transfer control unit, the compressed data buffer is
The compression data buffer is controlled so that the compressed image signal is written in response to a write request from the compression unit and the compressed image signal is read in response to a read request from the external device. apparatus. 2. The image compression apparatus according to claim 1, wherein the compression unit performs compression based on an intra-frame coding algorithm. 3. The image compression apparatus according to claim 2, wherein the data transfer control unit sets a plurality of banks in a memory space of the compressed data buffer, and the compressed image signal obtained by the compression unit. Is written to each one of the plurality of banks for each screen, and the compressed image signal held in a bank not being written among the plurality of banks is read to the external device. An image compression apparatus, characterized in that the compressed data buffer is controlled. 4. The image compression apparatus according to claim 3, wherein the data transfer control unit individually generates addresses for writing and reading for each one of the plurality of banks. And a plurality of registers that individually hold information regarding the address generated by each one of the address generation units when writing, and one of the plurality of address units is selected, and the selected one is selected. An address selection unit that supplies the address generated by one to the compressed data buffer, the plurality of address generation units refer to the information held in the plurality of registers, and An image compression apparatus, wherein the address is generated. 5. An image decompression device for decompressing and outputting a compressed image signal input from an external device, comprising: a decompression unit for decompressing the compressed image signal to obtain an image signal, the decompression unit and the external device. A data transfer control unit that controls the writing operation and the reading operation of the compressed image signal in the compressed data buffer by interposing therebetween a compressed data buffer that temporarily holds the compressed image signal; In the transfer control unit, the compressed data buffer is
The compressed image data buffer is controlled so that the compressed image signal is written in response to a write request from the external device and the compressed image signal is read out in response to a read request from the decompression unit. apparatus. 6. The image decompression device according to claim 5, wherein the decompression is performed on the basis of an intra-frame coding algorithm. 7. The image decompression device according to claim 6, wherein the data transfer control unit sets a plurality of banks in a memory space of the compressed data buffer, and a bank that is not being read out of the plurality of banks. The image data is controlled by controlling the compressed data buffer so that the compressed image signal sent from the external device is written to each one of the plurality of banks for each screen. Stretching device. 8. The image decompression device according to claim 7, wherein the data transfer control unit individually generates addresses for writing and reading for each one of the plurality of banks. And a plurality of registers that individually hold information regarding the address generated by each one of the address generation units when writing, and one of the plurality of address units is selected, and the selected one is selected. An address selection unit that supplies the address generated by one to the compressed data buffer, the plurality of address generation units refer to the information held in the plurality of registers, and An image decompression device characterized by generating the address. 9. The image decompression device according to claim 7, wherein the data transfer control unit is responsive to an instruction from the external device for one screen held in one of the plurality of banks. To read the compressed image signal of
An image decompression device characterized by controlling the compressed data buffer. 10. An image compression / expansion device that compresses an input image signal and outputs the compressed image signal to an external device, and also expands and outputs a compressed image signal input from the external device. A compression / decompression unit including a compression unit for obtaining the compressed image signal and a decompression unit for decompressing the compressed image signal to obtain the image signal; and interposed between the compression / decompression unit and the external device, A compressed data buffer that temporarily holds a compressed image signal; and a data transfer control unit that controls a write operation and a read operation of the compressed image signal in the compressed data buffer, wherein the compression unit and the decompression unit are mutually Compressing and decompressing are performed by performing inverse operations, and the data transfer control unit is configured such that the compressed data buffer is
The compressed image signal is written to or read from the compression / expansion unit in response to a request from the compression / expansion unit, and the compressed image signal is exchanged with the external device in response to a request from the external device. To read or write,
An image compression / decompression device characterized by controlling the compressed data buffer. 11. The image decompression device according to claim 5, wherein the compressed image signal is variable-length code data, and the decompression unit decodes a single compressed data. A small-scale decoder, a large-scale decoder for decoding two or more pieces of compressed data having a processing speed characteristic almost half that of the small-scale decoder, and the small-scale decoder and the large-scale decoder being simultaneously compressed. Input data control means for giving single or two or more data, first switching means for switching and outputting output data from the small scale decoder and output data from the large scale decoder, and the first switching means. Delaying means for delaying and outputting the output data from the switching means by a unit time; and output data from the first switching means based on a predetermined timing signal. A second switching means for switching between the output data from the delay means and the output data from the delay means; and for switching the second switching means from the output data from the delay means to the output data from the first switching means. Timing control means for generating the predetermined timing signal, and the small-scale decoder has determination means for determining whether the received data is single data or two or more data, and the timing control means Is undefined data generated when the first switching unit switches from the output data from the small-scale decoder to the output data from the large-scale decoder based on the determination signal of the determination unit of the small-scale decoder. And an indefinite timing detection means for detecting the predetermined timing signal based on the signal from the indefinite timing detection means And a timing signal output means for outputting to the second switching means. 12. The image compression apparatus according to claim 1, wherein the compression unit performs a predetermined process on the image signal in a pipeline, and the compression unit provides: An enable means for detecting a timing at which each pipeline operates effectively based on the horizontal and vertical sync signals and outputting a predetermined enable signal; and a predetermined enable signal from the enable means. An image compression apparatus, comprising: a processing control unit that permits signal processing in the pipeline only when the predetermined enable signal is not received, and stops signal processing in the pipeline when the predetermined enable signal is not received. 13. The image compression apparatus according to claim 1, wherein the compression unit performs a predetermined process on the image signal in a pipeline, and the compression unit Enable means for detecting a timing at which each pipeline effectively operates based on the received horizontal synchronization signal and vertical synchronization signal, and outputting a predetermined enable signal; and the number of pipeline stages for signal processing the predetermined enable signal. The enable signal delaying means for delaying only by the amount, and the signal processing in the pipeline is permitted only when the predetermined enable signal corresponding to each stage from the enable means or the enable signal delay means is received, and the predetermined signal is enabled. Processing control means for stopping signal processing in the pipeline when the enable signal is not received Image compression apparatus according to claim and. 14. The image decompression device according to claim 5, wherein the decompression unit performs predetermined processing on the compressed image signal in a pipeline, and the decompression unit includes: An enable means for detecting a timing at which each pipeline operates effectively on the basis of the given horizontal synchronizing signal and vertical synchronizing signal and outputting a predetermined enable signal, and a predetermined enable signal from the enable means. An image decompression device, comprising: a processing control unit that permits signal processing in the pipeline only when the predetermined enable signal is received and stops signal processing in the pipeline when the predetermined enable signal is not received. 15. The image decompression device according to claim 5, wherein the decompression unit performs predetermined processing on the compressed image signal in a pipeline, and the decompression unit includes: Enable means for detecting the timing at which each pipeline operates effectively based on the given horizontal synchronizing signal and vertical synchronizing signal and outputting a predetermined enable signal, and the predetermined enable signal for the pipeline of signal processing. The enable signal delay means for delaying by the number of stages, and the signal processing in the pipeline is permitted only when the enable means or the predetermined enable signal corresponding to each stage from the enable signal delay means is received, and the predetermined signal is permitted. Processing control means for stopping the signal processing in the pipeline when not receiving the enable signal of Image expansion apparatus according to claim Rukoto.