JPH118853A - Image compressing and expanding device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To process a video signal without using a frame buffer not an FIFO. SOLUTION: A data enable generation circuit 106 generates a data enable signal only while an input video signal is effective based on horizontal synchronizing (HSYNC) signal and a vertical synchronizing (NSYNE) signal at the time of compression, and each signal processor 103-1 to 103-3 in a compressing device processes inputted image data through pipeline processing. Each internal deciding device 104 processes data only when data is valid, and an internal delaying device 105a on each stage holds data until the next valid signal comes when data is not valid. Each pipeline delivers only valid data and asures an ineffective period for a fixed period in input-output of data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image compression / expansion apparatus for compressing a video signal and expanding compressed data.

[0002]

[Prior art]

<< Example of Conventional Huffman Decoder >> Generally, a variable-length code is a technique in which the encoded data length is variable and data can always be decoded only sequentially. That is, since parallel processing is difficult to decode, realization of high-speed decoding of a variable-length code decoder is a major problem. A typical example of the variable length code method is a Huffman code. The Huffman code assigns a variable length code according to the frequency of appearance of data. In particular, when used for image data, since the same data is highly likely to be continuous, a plurality of data are often encoded at a time with the continuous length (run length) as an encoding target.

FIG. 7 shows a configuration example of a conventional high-speed Huffman decoder using run lengths. In FIG. 7, 1 is an input data control block for outputting data to be processed next in variable length data, 2 is a decoded data table (lookup table) in which data necessary for decoding Huffman codes is written, Reference numeral 3 denotes a decoded data amount calculation block for calculating the amount of decoded data based on the contents of the decoded data table 2 and generating a decoding timing signal, and 4 detects a continuous length (run length) when the same data continues. The run length counters 5 and 6 are delay circuits (delays).

Here, the decoded data table 2 has the following data configuration in a configuration using an associative memory or a normal memory configuration in order to speed up the decoding of Huffman data. That is, the variable length data is provided with redundant data, and the same data is written to the corresponding addresses. For example, in the case of a Huffman code having a maximum length of 8 bits, the same decoded data is written in all remaining 6-bit addresses for a 2-bit Huffman code.

[0005] With these table configurations, decoding can be performed by a single table lookup.

{Example of Conventional ADCT} Generally, irreversible coding is a compression technique that obtains a high compression rate by efficiently quantizing data using human senses. An orthogonal transformation is a technique often used in this compression method. The orthogonal transform transforms the spatial axis so that the power of the signal is concentrated. For image data, two-dimensional transform, which is one method of spatial-frequency spatial transform, in terms of the conversion efficiency and the amount of hardware. Discrete cosine transform (hereinafter 2D-DCT) is often used.

A typical image compression method using 2D-DCT is an adaptive discrete cosine transform (ADCT). This is a compression method adopted as a global standard for image compression called JPEG or MPEG. However, in this method, as the compression rate is increased, block-shaped distortion (hereinafter, referred to as block distortion) unique to orthogonal transform occurs. This block distortion is conspicuous in an image portion that changes relatively slowly, such as the sky or a wall, and a large image quality deterioration is visually perceived.

[0008] FIG. 8 shows a conventional block distortion countermeasure A.
4 shows a flow of compression and decompression of DCT. Reference numerals 11 to 15 in FIG. 8 denote devices in the encoding operation. Reference numeral 11 denotes a raster / block conversion device for converting raster data into 8 × 8 block data to be input to the 2D-DCT. A two-dimensional discrete cosine transform device (2D-DCT device) 13 for performing frequency space transform; A quantizer 15 for performing quantization is an entropy encoder such as a Huffman code or an arithmetic code. Also, 1 in FIG.
6 to 21 perform inverse transform corresponding to each device related to the encoding operation, and 16 denotes an entropy decoding device, 1
7 is an inverse quantization device, 18 is a zigzag inverse transform device for rearranging one-dimensional data in a zigzag manner and two-dimensionally arranging it, and 19 is a two-dimensional discrete inverse cosine transform device (2D-IDCT device) for performing frequency space-space conversion. , 20 is a block / raster conversion device for converting 8 × 8 block data into raster data, and 21 is a spatial filter device for blurring an image injected to reduce block distortion of a decoded image.

Next, the operation of the conventional image compression / decompression device will be described. In the encoding process, first, the image data is converted from the raster data into 8
It is converted into × 8 block data. The data converted into blocks is converted into a space-frequency space by the 2D-DCT device 12. The data converted to the frequency space is rearranged by the zigzag converter 13 in the order of lower frequencies and output. The quantizer 14 utilizes the visual characteristics of human beings to quantize low-frequency data to a small value, and quantize higher-frequency data to a larger value. By this processing, power concentration of data can be increased while suppressing deterioration of image quality, and the compression ratio can be increased. The entropy encoding device 15 compresses data using an entropy code such as a Huffman code.

[0010] On the other hand, the decoding process is realized by performing the above-described reverse process. In order to reduce block distortion, decoded data converted into a raster is output through a spatial filter device 21. .

In such a conventional image compression / expansion apparatus,
As a measure against block distortion, 2D-DC in FIG.
In T and 2D-IDCT processing, there is a method of reducing discontinuity of a spatial filter frequency in a superimposed portion by superimposing and processing data of continuous blocks little by little.

{Example of Conventional Compression / Expansion Apparatus and Peripheral Apparatus} Generally, a video signal for generating an image is composed of a vertical synchronizing signal (hereinafter, referred to as VSYNC) and a horizontal synchronizing signal (hereinafter, referred to as HSYNC). It is configured based on two types of synchronization signals, and usually has invalid data in both the vertical and horizontal directions. For example, in the NTSC signal, valid data is about 480 out of 525 lines.
It is a book. In the horizontal direction, about 80% is the effective area. In the case of compressing an image signal, it is common to perform compression processing only on the effective data in order to reduce the amount of data to be processed as much as possible and to increase the processing speed.
FIG. 9 (first conventional example) shows a configuration example of a conventional compression / expansion apparatus. Reference numeral 31 in FIG. 9 denotes HSYNC and VSYNC.
A timing generating device for generating a timing signal for inputting / outputting valid image data to / from a frame buffer based on C;
Reference numeral 2 denotes a frame buffer of about 6 megabits for temporarily buffering effective image data, 33 a compression / expansion device for compressing / expanding image data, and 34 a compressed data storage device for storing compressed data. Also, 35, 36 in FIG.
Reference numerals a, 36b, and 36c denote elements constituting the inside of the compression / decompression device 33, 35 denotes a delay device (delay) for pipeline processing, and 36a, 36b, and 36c denote signal processing devices of each pipeline.

Next, the processing procedure will be described. First, in the compression mode, only the data of the effective portion of the image is taken in by the timing generator 31 and the frame buffer 32 from the digital video signal input to the present apparatus. Only the data of the effective portion of the data taken into the frame buffer 32 is sequentially compressed by the compression / expansion device 33. The compressed data is accumulated by the compressed data storage device 34. On the other hand, in the expansion mode, the compressed data is sequentially taken from the device 34 to the compression / expansion device 33 and expanded. The decompressed data is temporarily stored in the frame buffer 32, and is output in accordance with the timing of the valid data generated by the timing generator 31 based on HSYNC and VSYNC.

FIG. 10 shows a configuration example (second conventional example) of a conventional compression / expansion apparatus according to another method. 41, 4 in FIG.
2 is the same as the compression / decompression device 33 and the compressed data storage device 34 shown in FIG. 9, respectively. 43 is a FIFO memory for temporarily buffering data, and 44 is a HSY timing for inputting and outputting data from the FIFO memory 43.
This is an input / output control device created corresponding to NC and VSYNC. 45 is a FIFO that controls the FIFO memory 43
O control device.

Next, the operation will be described. At the time of compression, the FI signal is
Input data to FO. FIFO controller 45 is FI
The data is compressed while performing control such as stopping the clock of the compression / expansion device 41 so that the FO memory 43 does not become FULL or NULL. When expanding, first, FIF
The data is decoded until the O memory 43 becomes full to some extent, and the processing of the compression / expansion device 41 is interrupted by, for example, stopping the clock of the compression / expansion device 41. Based on the signal from the input / output control device 44, the data is output from the FIFO memory 43, or the compression / expansion device 41 is operated again when the data in the FIFO memory 43 is reduced to some extent. As described above, the FIFO memory 43 is also used at the time of expansion.
Is controlled by the FIFO control device 45 so that does not become FULL or NULL.

[0016]

[Problems to be solved by the invention]

<< Problems of Conventional Huffman Decoder >> Usually, in the configuration of the conventional high-speed Huffman decoder as shown in FIG. 7, a memory such as a ROM, a RAM or an associative memory is used as a table. This is because if all the tables are created by the hardware decoder, the amount of hardware becomes too large and becomes unrealistic.

In the conventional configuration, the reading speed of the memory used for this table is lower than the processing speed of the other blocks, so that the reading speed of the decoded data table 2 is lower than the processing speed of the variable length code decoding device. It is a major factor in determining speed.

{Problems of Conventional ADCT} In the conventional ADCT shown in FIG. 8, as described above, the spatial filter device 2
1 is inserted into the decoded output, or the 2D-DCT device 12 and the 2D-IDCT device 19 process the data in adjacent blocks by slightly overlapping each other.
Block distortion is reduced.

However, in the method using the spatial filter device 21, since filtering is performed on all images, block distortion is blurred to a small image portion that is not so noticeable, and it is not possible to improve the overall image quality. Can not. Then, the data is superimposed and the DCT
In the method of performing the processing, it is very difficult to process the video signal in real time because the amount of data to be processed increases.

{Problems of the conventional compression / expansion apparatus}
The compression / expansion apparatus for handling the video signal of the prior art and the second conventional example) can handle only the effective data period of the video signal, so that the frame buffer 32 shown in FIG. 9 or the FIFO shown in FIG. The input / output timing of the video signal is buffered by controlling the input / output timing of the memory 43.

However, the frame buffer 32 shown in FIG. 9 (first conventional example) requires a large capacity (about 6 megabits) to store one image as a memory. In addition, since input and output must be performed asynchronously, input and output of digital video signals are normally performed through dual ports (for example, using a VRAM). For these reasons, it becomes relatively expensive, and occupies a considerable cost ratio in configuring the compression / expansion apparatus.

Further, the F shown in FIG. 10 (second conventional example)
When buffering data input / output timing by controlling the FIFO memory 43, the FIFO memory 43 is full (FUL
L) or not, and the processing of the compression / expansion device 41 is stopped when it becomes full. Also, it is detected whether the FIFO memory 43 has become empty (NULL),
When it became empty, the processing of the compression / expansion device 41 was hastened. As described above, it is necessary to control the FIFO memory 43 so that the FIFO memory 43 does not become FULL or NULL, and the control becomes considerably complicated. In addition, if you try to switch the data to expand in the middle,
The switching timing for storage in the compressed data storage device 34 must be synchronized with the control of the FIFO control device 45 depending on the state of the FIFO memory 43, so that the processing of the compression / decompression device 41 is very detailed. Complex controls are needed.

{Problems to be Solved by the Present Invention} The present invention is particularly directed to the above-mentioned subject, in particular, the frame buffer and the F
It is an object of the present invention to obtain an image compression / decompression device capable of inputting / outputting a video signal without using an IFO.

[0024]

Means for Solving the Problems According to a first aspect of the present invention, there is provided a compression unit for compressing a video signal, and a decompression unit for decoding and decompressing the data compressed by the compression unit. At least one of the compression section and the expansion section performs predetermined processing of a video signal in a pipeline, and each pipeline operates effectively based on a given horizontal synchronization signal and a vertical synchronization signal. Enable means for detecting a timing and outputting a predetermined enable signal; and enabling signal processing in the pipeline only when receiving the predetermined enable signal from the enable means, and not receiving the predetermined enable signal. And processing control means for stopping signal processing in the pipeline.

The problem solving means according to claim 2 of the present invention is as follows.
A compression unit that compresses the video signal; and a decompression unit that decodes and decompresses the data compressed by the compression unit. At least one of the compression unit and the decompression unit performs a predetermined process on the video signal in a pipeline. An enable means for detecting a timing at which each pipeline operates effectively based on a given horizontal synchronizing signal and a vertical synchronizing signal, and outputting a predetermined enable signal; Enable signal delay means for delaying by the number of stages of the processing pipeline; and signal processing in the pipeline only when receiving the predetermined enable signal corresponding to each stage from the enable means or the enable signal delay means. Permitting and stopping signal processing in the pipeline when the predetermined enable signal is not received. And a control unit.

[0026]

In the image compression / expansion apparatus according to claim 1 of the present invention,
The enable means detects the timing at which each pipeline operates effectively based on the horizontal synchronization signal and the vertical synchronization signal, and outputs a predetermined enable signal. The processing control means permits the signal processing in the pipeline only when receiving a predetermined enable signal from the enable means, and stops the signal processing in the pipeline when not receiving the predetermined enable signal. As described above, since the processing of each pipeline is operated only during a period in which valid data is to be processed, HSYNC and VSY can be used without using a frame buffer and FIFO as in the related art.
Only the effective portion of data can be input and output very easily in synchronization with the NC signal. Also, since the pipeline passes only valid data, the invalid period of data input / output can always be guaranteed for a certain period,
Even when the compressed data is changed during the decompression process, the data can be changed at any time during the invalid period, eliminating the need for a complicated timing processor.

In the image compression / expansion apparatus according to the second aspect of the present invention, the enable signal delay means delays the predetermined enable signal by the number of stages of the signal processing pipeline, adjusts the timing, and controls the processing control means. Then, the signal processing in the pipeline is permitted only when a predetermined enable signal is received, and the signal processing in the pipeline is stopped when the predetermined enable signal is not received. As described above, since the processing of each pipeline is operated only during a period in which valid data is to be processed, it is very easy to input / output only the data of the valid portion at an appropriate timing according to each stage. And the timing control becomes extremely easy.

[0028]

【Example】

<< First Embodiment >><Principle> Generally, the same data often continues in image data, and therefore, the difference between consecutive data is often “0”. In particular, in the case of the discrete cosine transform (DCT) processing, since the data is often concentrated in a specific area (for example, a low frequency area), the rate at which the above-mentioned difference becomes “0” is extremely high. For example, when the difference is “0005” (1), the run length of “0” (hereinafter, referred to as “0 run length”) is “3”, followed by “5” (that is, other than “0”). Huffman code is allocated two-dimensionally in such a manner that data) comes. in this case,
In order to decode the data of "3" which is 0 run length and the data of "5" that comes next,
In the case of the sequence shown in the above (1), four data can be processed by one decoding.

"2134" (2) On the other hand, when data other than "0" is continuous as the differential data, that is, when the 0 run length is "0" as in the sequence shown in (2) above, decoding should be performed. The data is “2”,
Only one piece of data can be processed for one decoding such as "1", "3", and "4".

Considering these facts, it can be seen that the processing speed differs at least twice or more depending on whether or not the 0 run length is "0". That is, when the 0 run length is "1" or more, two or more data are decoded at a time, so even if it takes two cycles for the memory lookup, the final data output timing is once per data. There is no time inferior to the decoding timing. As described above, since data other than “0” is limited to a specific area such as a low frequency area, the processing is deflected depending on whether or not the 0 run length is “0”. This is desirable for improving the processing speed. In consideration of this, first, it is detected whether the 0 run length is “0” or “1” or more, and only a specific area where the 0 run length is “0” is detected by a high-speed hardware decoder. By performing the process and performing a process of a path different from the case where the 0 run length is equal to or more than “1”, the processing speed is increased by increasing the speed of the decoder as compared with the conventional example which depends on the processing speed of the memory lookup. The image compression / expansion apparatus according to the present embodiment is intended to realize the improvement.

<Structure> FIG. 1 shows the structure of a decoding processing unit of an image compression / decompression apparatus for Huffman codes using 0 run-length data according to the first embodiment of the present invention.
The image compression / decompression device according to the present embodiment includes a compression unit that compresses a video signal, and a decompression unit that decodes and decompresses variable-length code data compressed by the compression unit. FIG. 1 illustrates the decompression unit. In FIG. 1, reference numeral 51 denotes an input data control block (input data control means) for determining data to be decoded next in variable length data. Reference numeral 52 denotes a hardware decoder (small-scale decoder: hereinafter, referred to as HW decoder) capable of high-speed processing for decoding only the Huffman code corresponding to 0 run-length data corresponding to "0". H / U which is the output signal from
The signal (judgment signal) is a signal indicating whether the internal data of the HW decoder 52 has been hit or not. Specifically, as shown in FIG. 2B, a High signal is output when the internal data is hit, and a Low signal is output when the internal data is not hit. In order to perform such processing, an internal data storage means (memory) 52a for storing internal data as a reference, an internal data of the internal data storage means 52a and an input data control block 51 are provided inside the HW decoder 52. Collating means (comparator: determining means) for collating with the Huffman data of (5)
2b.

Further, reference numeral 53 denotes a memory (table: large-scale decoder) for decoding a Huffman code to which 0 run length is assigned to 1 or more, and 54 denotes an HW decoder 52 based on an H / U signal from the HW decoder 52.
A first multiplexer (first switching means: hereinafter, referred to as a first MUX) for selecting decoded data from the memory 53 and decoded data from the memory 53, and 55 is based on 0 run-length data decoded by the memory 53. A run-length counter that counts 0 run-lengths in order to cause the data output timing to be delayed by the number of 0 run-lengths.
Reference numeral 56 denotes a data enable generation circuit for generating a flag as to whether or not the next data is to be decoded based on the H / U signal of the decoder and the output of the 0 run length counter.

Further, when the Huffman data from the input data control block 51 does not hit the internal data of the HW decoder 52, the timing at which the output data becomes indefinite due to the slow access speed of the memory 53 can be obtained (57). 2 (F) in FIG. 2), an undefined timing detection circuit (undefined timing detection means) which detects this and generates a flag (see FIG. 2 (E)) for controlling the data output timing. is there.

Reference numeral 58 denotes decoded data for calculating the amount of data decoded so far from the decoded data output from the first MUX 54 and creating auxiliary data for outputting compressed data to be decoded next. Quantity calculation circuit, 59, 6
Reference numerals 0, 61 and 62 denote delay devices (delays) for delaying the data train by one cycle of the clock signal CK, and 63 denotes a delay device 61 (delay means) based on a timing signal from the delay device 60 (timing signal output means). ) From the output data from the first MUX 54 to the output data from the first MUX 54 (second switching means:
Hereinafter, referred to as a second MUX).

The indefinite timing detection circuit 57 and the delay device 60 constitute timing control means for generating a predetermined timing signal for switching the second MUX 63.

<Operation> The processing procedure of the image compression / expansion apparatus having the above configuration will be described. FIG. 2 is a timing chart showing the operation of the image compression / decompression device of the present embodiment. The data shown in FIG. 2A is input data control block 51.
, The 0 run length of data a is “0”, the 0 run length of data b is “1”, and the data c
It is assumed that the 0 run length of the data d is “0” and the 0 run length of the data d is “2”.

First, when the data a of FIG. 2A is output from the input data control block 51, as shown in FIG.
It is simultaneously input to the HW decoder 52 and the memory 53.
Here, the comparing means (comparator) in the HW decoder 52 detects whether or not the received Huffman data a hits the internal data of the decoder. And data a
Outputs a high signal as an H / U signal ((B) in FIG. 2) as a flag indicating the hit, and decodes the decoded data (( The data A) of C) is output. On the other hand, when the 0 run length of the data a is “1” or more, since the data a does not hit the internal data of the HW decoder 52, the Low signal is output as the H / U signal ((B) in FIG. 2). . Further, the memory 53 always decodes the data a and outputs decoded data.

When the first MUX 54 is notified of the hit to the HW decoder 52, the first MUX 54 outputs Hi / H signal as Hi / U signal.
gh signal is input, and the HW decoder 5
2 is selected. On the other hand, if no hit has occurred, a Low signal is input as the H / U signal, and the decoded data from the memory 53 is selected accordingly. Further, the 0 run length data output from the memory 53 is input to the 0 run length counter 55, and the data enable generating circuit 56 performs a process of waiting the timing of decoding the next data by the number of 0 run lengths.

On the other hand, the decoded data amount calculation circuit 58
, The amount of data decoded so far is calculated from the decoded data output from the MUX 54, and auxiliary data for outputting compressed data to be decoded next is created. 2nd M
The UX 63 embeds correct data in accordance with the timing detected by the indefinite timing detection circuit 57 (High signal of (E) in FIG. 2) and creates final decoded data (data of (H) in FIG. 2). A).

The above is the processing for the data a in FIG. 2A. Since the look-up of the memory 53 takes two cycles, the data a is output, and the subsequent cycle is as shown in FIG. Data A and data B in (B)
It becomes indefinite as shown in between. That is, the timing at which the data b of (A) is decoded (the data B of (B) in FIG. 2) is the second cycle after the data A. That is, when the 0 run length is “1” or more, one cycle of an indefinite period occurs.

Therefore, the entire data string is delayed by one cycle by a delay unit (delay) 61, and the portion of the indefinite period subjected to the delay processing (output from the delay unit 61: (F) in FIG. 2) When the data B (output from the first MUX 54: (C) in FIG. 2) is embedded at a timing at which no delay processing is applied to the
Output can be performed at the same speed as the cycle of the decoder 52.

When the 0 run length is equal to or more than "2" like the data d in (A) of FIG. 2, the indefinite timing detection circuit 57 in (E) of FIG. The output from the delay device 61 becomes undefined as shown in (F) in FIG. 2 for the data one cycle after the detection (when no hit is made at 52). Also, (F) in FIG.
The data following the undefined data follows data D and data D. Therefore, if the data D is embedded by performing the same processing as in the case of the data B, the data D
Can be output at the same speed as the cycle of the HW decoder 52.

As described above, in the image compression / decompression device of this embodiment, the HW decoder 52 for decoding a code when the 0 run length is "0" must output decoded data within one clock. The memory 53 for decoding 0 or more run lengths may output data within two clocks. The HW decoder 52 used here is for high-speed processing corresponding to the Huffman code only when the 0 run length is "0", so that the circuit scale can be small and the processing can be performed at extremely high speed.

Second Embodiment <Configuration> FIG. 3 is a functional block diagram showing an image compression / decompression apparatus according to a second embodiment of the present invention. In FIG. 3, reference numerals 71 to 75 denote components of the compression unit, and reference numerals 76 to 84 denote components of the expansion unit. 71 is a raster / block converter for converting raster data into 8 × 8 block data for input to the 2D-DCT, 72 is a two-dimensional discrete cosine converter (2D-DCT device) for performing space-frequency space conversion, Reference numeral 73 denotes a zigzag transformer that scans the results of the DCT in a zigzag manner in order from the lowest frequency, rearranges them one-dimensionally, and outputs them. 74 denotes a quantizer that performs scalar quantization. An encoding device, 76 is an entropy decoding device, 77 is an inverse quantization device, 78 is a zigzag inverse transform device that rearranges one-dimensional data in a zigzag shape and two-dimensionally arranges it, and 79 is a two-dimensional device that performs frequency space-space conversion. A discrete inverse cosine transform device (2D-IDCT device) 80 is a block / rack for converting 8 × 8 block data into raster data. These are the star converters, which have the same functions as the conventional devices.

Reference numeral 81 denotes a block distortion prediction device (block distortion prediction means) for detecting a portion where block distortion is likely to occur from the data structure of the inversely quantized frequency space. Of the fourth and subsequent data among the above data (determination means). Here, FIG. 5 is a diagram showing the internal configuration of the block distortion prediction device 81. In FIG. 5, TS3 is a first timing signal which becomes High only from the first to third output data timings of the first to 64th output data of the inverse quantization device 77 and thereafter becomes Low, and TS1 is an inverse quantization device. During the first to 64th output data of 77, only the first one becomes High and then becomes Lo.
CK is a clock signal, which is a second timing signal that becomes w. As shown in FIG. 5, the block distortion prediction device 81 includes a first NOR circuit 91 that calculates the logical sum (inversion) of the 11-bit output signal from the inverse quantization device 77, and the first NOR circuit 91.
The output from the circuit 91 and the first timing signal TS3
And a JK-flip-flop whose input is divided into a J terminal and a K terminal and whose output is determined by a combination of the inputs of the J terminal and the K terminal. And the second timing signal TS1
Is the set input signal (CS), and the output signal from the JK flip-flop 93 is the input signal (D).
A flip-flop 94;

Reference numeral 82 denotes a timing adjustment device (timing signal generating means) for adjusting the timing of the flag output from the block distortion prediction device 81 and the final raster output from the block / raster conversion device 80, and reference numeral 83 denotes raster data. 5 × 5 spatial filter device (filter unit) for applying a smoothing filter to output image data, 84
Is an output switching device (multiplexer: output switching unit) that selects an output from the block / raster conversion device 80 and an output from the spatial filter device 83 based on a block distortion prediction flag.

The block distortion predicting device 81 and the timing adjusting device 82 constitute a switching control section for controlling the switching of the output switching device 84.

<Operation> In the image compression / expansion apparatus having the above configuration, at the time of data compression processing, first, the image data is converted into 8 × by the raster / block converter 71 from the raster data.
8 block data. The data converted into blocks is converted into a space-frequency space by the 2D-DCT device 72. The data converted to the frequency space is rearranged by the zigzag converter 73 in the order of lower frequencies and output. The quantizer 74 utilizes the visual characteristics of humans to quantize low-frequency data small and quantize high-frequency data larger. By this processing, power concentration of data can be increased while suppressing deterioration of image quality, and the compression ratio can be increased. Entropy encoder 75
Compresses data using an entropy code such as a Huffman code.

On the other hand, in the decoding process, the compressed data is decoded by an entropy decoding device 76 using an entropy code such as a Huffman code, and is inversely quantized by an inverse quantization device 77. The signal output from 77 is output in order from the component having the lower spatial frequency.

Here, as for the components in the block decomposed into 64 frequency components, as shown in FIG. 4, for example, when all the fourth and subsequent frequency components from the lower frequency are "0", a flag is set, and However, if there is data other than "0", no flag is set. An image in which block distortion is highly likely to be visually noticeable is a portion of a simple pattern such as the sky or a wall. This means that when decomposed into spatial frequencies, there is data only for reduction, and there is almost no data in the high frequency range. That is, as described above, it is possible to determine an image block having a high possibility of causing block distortion by determining whether all of the fourth and subsequent data are “0” or not “0”. In this case, as shown in FIG. 5, it is determined based on the first timing signal TS3 whether or not the fourth and subsequent data from the second NOR circuit 92 are all "0".

Next, based on the flag from the block distortion prediction device 81, the output signal from the spatial filter device 83 and the signal as it is from the block / raster conversion device 80 are switched and output by the output switching device 84. The switching is performed in accordance with the timing at which the decoded data is output from the block distortion prediction device 81. By the above processing, it is possible to output smoothed filtering only for a portion where block distortion is likely to occur, and to output unfiltered data for other portions. For this reason, it is possible to prevent image blur of a complicated pattern and reduce block distortion.

<< Third Embodiment >><Structure> FIG. 6 is a diagram showing an image compression / decompression apparatus and its peripheral devices according to a third embodiment of the present invention. 101 in FIG.
Is an image compression / decompression device including a compression unit and a decompression unit;
Reference numeral 2 denotes a data storage device that stores compressed data. Reference numerals 103-1, 103-2, and 103-3 denote various signal processing devices in the image compression / decompression device 101;
Is the signal processing device 103-1, 103-2, 1 in the preceding stage.
The internal determination device (processing control unit) of the image compression / decompression device 101 that determines whether to reflect the data processed in 03-3 on the output of each subsequent pipeline based on the data enable signal from the data enable generation circuit 106 Means 105a, an internal delay device (register) of the image compression / decompression device 101 for delaying the internal signal from the internal determination device 104 by one clock, and 105b a data enable signal from the data enable generation circuit 106 at each stage of the pipeline. Signal processing devices 103-1 and 103-2,
An internal delay device (enable signal delay means: register) of the image compression / decompression device 101 for delaying one clock at a time corresponding to the number of stages of 103-3, and 106 is an external HSY
A data enable generation circuit (enable means) for generating a data enable signal based on the NC signal and the VSYNC signal for enabling only during the period of valid data. Here, the internal determination device 104 permits the signal processing in the pipeline only when receiving the data enable signal from the data enable generation circuit 106, and the pipeline when not receiving the data enable signal. A common multiplexer is used, and one of a pair of input terminals is connected to one of the signal processing devices 103-1 and 103 in the preceding stage.
The output terminals of −2 and 103-3 are connected, and the other is feedback-connected to the output terminal of the succeeding internal delay device 105a.

<Operation> A processing method of the image compression / expansion apparatus having the above configuration will be described. First, at the time of compression, the data enable generation circuit 106 outputs the HSYNC signal and the VSYNC signal.
A data enable signal is generated based on the signal during a period in which the input video signal is valid. Each of the signal processing devices 103-1, 103-2, and 103-3 in the compression device sequentially processes the input image data by pipeline processing, and is output to the next stage by the internal determination device 104 of each stage. Or keep the previous data. That is,
The data is processed only when the data in each stage is valid. Otherwise, the internal delay device 105a in each stage holds the data until the next valid signal comes. By performing such processing, only valid input video signals can be compressed. Next, processing at the time of decompression will be described.

On the other hand, in the decompression process, the timing at which the video signal is output is delayed by the number of stages of the pipeline from the start of the decompression process. That is, HSYNC
To output the expanded data in accordance with the signal and the VSYNC signal, the data enable generation circuit 106 may output the data enable signal so as to start the processing by the number of stages of the pipeline before the timing of outputting the valid data. Usually, the video signal contains a lot of invalid data, so even with a small number of pipeline stages,
Such processing is possible without any problem.

Modification In the first embodiment, the decoder is divided into a decoder and a memory when the run length is "0" and when the run length is "1" or more. It goes without saying that other division methods can be applied.

[0056]

According to the first aspect of the present invention, in both the compression processing and the decompression processing, the enable means detects the timing at which each pipeline operates effectively based on the horizontal synchronizing signal and the vertical synchronizing signal, and determines the predetermined timing. And the processing control means permits signal processing in the pipeline only when a predetermined enable signal is received from the enable means, and outputs a signal in the pipeline when the predetermined enable signal is not received. Since the processing is stopped, only the valid part of the video signal is
Since input / output can be performed in synchronization with SYNC, a compression / expansion device that handles video signals without a frame buffer and FIFO can be used, and an inexpensive compression / expansion device can be realized. Also,
Since the valid period and the invalid period can be clarified in the input / output of the signal, the control of the data can be made very simple, and there is an effect that the compressed data can be easily switched during the decompression.

According to the second aspect of the present invention, while the timing is adjusted by delaying the predetermined enable signal by the number of stages of the signal processing pipeline by the enable signal delay means, the predetermined enable signal is processed by the processing control means. Signal processing in the pipeline is permitted only when a signal is received, and signal processing in the pipeline is stopped when a predetermined enable signal is not received. As described above, since the processing of each pipeline is operated only during a period in which valid data is to be processed, it is very easy to input / output only the data of the valid portion at an appropriate timing according to each stage. In addition to this, there is an effect that timing control becomes extremely easy.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a configuration of a Huffman decoder in an image compression / decompression apparatus according to a first embodiment of the present invention.

FIG. 2 is a timing chart showing an operation of the image compression / decompression device according to the first embodiment of the present invention.

FIG. 3 is a diagram showing a compression / expansion flow in an image compression / expansion apparatus of the ADCT method according to a second embodiment of the present invention.

FIG. 4 is a diagram illustrating a data configuration of block distortion appearance determination in the image compression / decompression device according to the second embodiment of the present invention.

FIG. 5 is a diagram illustrating an image compression / expansion device of a block distortion appearance determination circuit according to a second embodiment of the present invention.

FIG. 6 is a diagram showing an image compression / decompression device according to a third embodiment of the present invention.

FIG. 7 is a diagram illustrating a circuit configuration example of a conventional high-speed Huffman decoder.

FIG. 8 is a diagram showing a compression / expansion flow in a conventional ADCT type image compression / expansion apparatus.

FIG. 9 is a diagram showing a first conventional image compression / expansion apparatus.

FIG. 10 is a diagram showing a second conventional image compression / expansion apparatus.

[Explanation of symbols]

 Reference Signs List 51 input data control block 52 HW decoder 52a internal data storage means 52b verification means 53 memory 54 first multiplexer 55 run length counter 56 data enable generation circuit 57 undefined timing detection circuit 58 decoded data amount calculation circuit 59, 60, 61, 62 Delay device 63 Second multiplexer 71 Raster / block transform device 72 2D-DCT device 73 Zigzag transform device 74 Quantizer 75 Entropy encoder 76 Entropy decoder 77 Dequantizer 78 Zigzag inverse transformer 79 2D-IDCT Device 80 Block / raster conversion device 81 Block distortion prediction device 91 First NOR circuit 92 Second NOR circuit 93 JK-flip-flop 94 D-flip-flop 82 Timing adjustment device 83 spatial filter device 84 output switching device 101 image compression / decompression device 103-1, 103-2, 103-3 signal processing device 104 internal judgment device 105a, 105b internal delay device 106 data enable generation circuit

Claims (2)

[Claims] A compression unit that compresses a video signal; and a decompression unit that decodes and decompresses data compressed by the compression unit.
At least one of the compression section and the expansion section performs predetermined processing of a video signal in a pipeline, and each pipeline operates effectively based on a given horizontal synchronization signal and a vertical synchronization signal. Enable means for detecting timing and outputting a predetermined enable signal; and only when receiving the predetermined enable signal from the enable means, permitting signal processing in the pipeline and not receiving the predetermined enable signal. An image compression / expansion apparatus, further comprising: a processing control unit for stopping signal processing in the pipeline. 2. A compression unit for compressing a video signal, and a decompression unit for decoding and decompressing data compressed by the compression unit,
At least one of the compression section and the expansion section performs predetermined processing of a video signal in a pipeline, and each pipeline operates effectively based on a given horizontal synchronization signal and a vertical synchronization signal. Enable means for detecting timing and outputting a predetermined enable signal; enable signal delay means for delaying the predetermined enable signal by the number of stages of a signal processing pipeline; and each of the enable means or the enable signal delay means Processing control means for permitting signal processing in the pipeline only when receiving the predetermined enable signal corresponding to a stage, and stopping signal processing in the pipeline when not receiving the predetermined enable signal. Image compression / decompression device.