KR100987252B1 - Interface device and method for processing of bitstream data - Google Patents

Abstract

The present invention relates to an interface apparatus and a method for outputting desired bit data in byte data arranged in byte units including variable bit data, wherein the memory unit continuously receives the byte data from the transmission side, And the decoding unit sequentially receives and decodes the byte addresses for reading the continuous byte data, and the hardware logic unit sequentially reads the byte data stored in the data area of the memory unit corresponding to the decoded byte addresses and sequentially And the bearer shifter receives bit data and bit addresses arranged in the order, performs bit interfacing, and outputs desired bit data as byte-aligned data.

MPEG, bit stream, variable length bit data, byte data, address decoder section, hardware logic section, bearer shifter.

Description

TECHNICAL FIELD [0001] The present invention relates to an interface device and a method for processing bitstream data,             

1 shows a structure of byte-aligned data including variable-length bit data,

Figure 2 shows an interface device for processing general bitstream data;

FIG. 3 illustrates an operation for outputting bit data through an interface of general byte-aligned data; FIG.

4 illustrates an interface device for processing bitstream data having an 8-bit bus width according to a first embodiment of the present invention;

 5 is a diagram specifically illustrating a hardware logic unit according to the first embodiment of the present invention,

6 illustrates an interface device for processing bitstream data having a 16-bit bus width according to a second embodiment of the present invention;

FIG. 7 illustrates an interface device for processing bitstream data having a 32-bit bus width according to a third embodiment of the present invention; FIG.                 

8 is a diagram illustrating an operation for simultaneously performing a bit address input and a byte address input according to embodiments of the present invention;

9 is a flow diagram illustrating the operation of an interface for processing bitstream data in accordance with embodiments of the present invention.

The present invention relates to an interface apparatus and method for bit stream processing, and more particularly, to an interface apparatus and method for processing a bit stream such as a video signal compression format.

With the development of multimedia and network related technologies, communication systems focusing on voice and data services are developing into a multidimensional structure including a composite medium such as a video signal and the Internet.

In particular, video signal processing has been standardized by ISO's Joint Photographic Experts Group (JPEG), H.261 / H.263 of ITU, and MPEG Moving Pictures Expert Group (ISO) series. These protocols have different characteristics depending on the application, JPEG is mainly used for photo-CD, H.261 / H.263 is used for video phone and video conference, MPEG- 1 is mainly applied to CD-ROM and CD-I and computer applications, and MPEG-2 is mainly applied to digital broadcasting and video distribution. In addition, MPEG-4, established in 1999, not only compresses and encodes existing video and audio signals, but also produces still images, computer graphics, voice encoding of analytical synthesis, synthesized audio by MIDI (Musical Instrument Data Interface) Which is a general multimedia coding standard. The scope of this specification covers a wide range from simple profile of 64Kbps low-rate environment to main profile of 38.4Mbps, and its application field is applicable to all areas pursued by multimedia do. Furthermore, MPEG-4 has been used as the core of next-generation technology because it provides a multimedia service that integrates voice and video in IMT-2000, a mobile communication system technology.

On the other hand, since a video signal has a very large capacity, a compression technique is used to transmit the video signal. The general compression technique can be effectively performed by eliminating redundant information using the spatial and temporal correlation of the image information and variable-length encoding the redundant information. Among them, a typical compression technique is an entropy coding method using motion compensated DCT (Moving Compensated DCT), and MPEG has already adopted it. The bitstream encoded by the moving picture encoding method is applied to an image restoration device including a VLD, an inverse quantizer, an inverse discrete cosine transformer, a motion compensator, and the like to restore the original image. The compressed video signal, that is, the bit stream, has a variable-length bit-by-bit data structure. These variable length data are located between byte aligned data, as shown in FIG. Typical processors process byte aligned data by default. However, almost all of data such as MPEG is composed of variable length bit data, so that bit data is converted into byte aligned data throughout the decoder.

2 is a diagram showing a general interface device for processing a bitstream.

As shown in FIG. 2, the interface device includes a memory 20 for storing byte-aligned data that is compressed and encoded at the transmitting end, and an address decoder for receiving the byte address of A0 and A1, (20). The address decoder 20 outputs a decoded address so that the byte data corresponding to the decoded address can be read from the memory 20. [ In order to fetch the bit data into the general byte alignment data interface, a software process is performed as shown in FIG. 3, and the byte data including the desired bit data is fetched one by one and the unnecessary data is shifted (32 ). The processor then takes the last byte of data that contains the bit data and shifts (33) to obtain the desired final data via operation (34).

However, this software variable length method has to obtain 8-bit data unconditionally regardless of the width of the data bus, combine and compute them, and generate new data. For this operation, a software buffer must be provided and the number of bits read Unnecessary operations are increased. Since such an operation occurs throughout the decoder, there is a problem that the load of the processor increases.

Meanwhile, there is a method of implementing the variable length first address decoder hardware desired in addition to the software processing, which is a method of outputting desired decoded data immediately after inputting a bit stream. Alternatively, there is a hardware implementation method provided with a serial buffer so that an arbitrary number of bit data can be continuously fetched.

However, since the hardware implementation method is fast and the software is simple, only one decoding technique can be applied, resulting in a decrease in efficiency in systems requiring various application programs such as mobile. In addition, even if a serial buffer is used, an additional hardware control signal such as a clock must be used. Since the interface is complicated and a separate operation cycle must be used for storing in the serial buffer, a clock delay occurs in fetching data . Moreover, there is a problem in fetching data at an arbitrary position due to extraction of continuous bitstream data. Due to such a problem, it is difficult to apply the above methods in backward decoding.

Accordingly, an object of the present invention is to provide an interface apparatus and method for fetching variable length bit data used in a decoder such as image compression from byte-aligned data.

It is another object of the present invention to provide an interface device and method for fast processing without hardware delay in order to fetch continuous byte data including variable bit data without delay.                         

An apparatus for achieving the objects of the present invention includes variable bit data and an interface device for outputting desired bit data from byte data arranged in units of bytes, A decoder for sequentially receiving and decoding byte addresses for reading the continuous byte data, and a decoding unit for sequentially reading the byte data stored in the data area of the memory unit corresponding to the decoded byte addresses And a bearer shifter for receiving the byte data and the bit address listed in the order and performing bit interfacing and outputting the desired bit data as byte aligned data. It is gong.

A method for accomplishing the above objects of the present invention is an interface method for outputting desired bit data from byte data arranged in byte units including variable bit data, Storing the data in the data area, and receiving and decoding byte addresses for reading the consecutive byte data in order; and sequentially reading the byte data stored in the data area of the memory part corresponding to the decoded byte addresses and sequentially And performing bit interfacing by receiving the byte data and the bit address listed in the order, and outputting the desired bit data as byte aligned data.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description of the present invention, detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

An interface having 8-, 16-, and 32-bit bus widths will be described separately for each embodiment. First, an interface having an 8-bit bus width will be described in the first embodiment of the present invention . Here, an interface device having an 8-bit bus width requires one 8-bit memory, and since the finally outputted bit address data is one byte, a one-bit bearer shifter is required. It should be noted that the bit stream means having variable-length bit-by-bit data structure, and thus the bit stream means byte-aligned data including variable length.

FIG. 4 is a diagram illustrating an interface device for processing a bitstream in the case of an 8-bit bus width according to an embodiment of the present invention, and FIG. 5 is a diagram specifically illustrating a hardware logic unit according to an embodiment of the present invention to be. Here, the variable N in FIG. 4 represents the size of the bus width, and the variable X in FIG. 5 represents the input byte address.

Referring to FIG. 4, the interface apparatus 100 includes a memory unit 140 for storing byte-aligned data that is compressed and encoded from a transmitting end to be continuously input, and a memory unit 140 for storing the byte data stored in the memory unit 140 in a bit unit And a decoding unit 110 for decoding the input byte address so as to be addressable. The interface apparatus 100 includes a hardware logic unit 120 for reading continuous byte data without delay and a bearer shifter unit 130 for extracting only desired bit data from the read byte data.

The decoding unit 110 includes a first byte address decoder 111 decoding and outputting desired A0 and A1 byte addresses, and a second byte address decoder 112 decoding and outputting N + 1 bit addresses .

The memory unit 140 is composed of one memory having a size of 8 bits. In the memory unit 140, the row side represents a bit address address, and the column side represents a byte address address. When the first byte of data is received, the data is stored in the byte address 0 of the memory unit 140. When the next byte of data is received, the data is stored in the byte address 1 of the memory unit 140.

Referring to FIG. 5, the hardware logic unit 120 includes selection logic 121 connected to the first address decoder 111 and the second address decoder 112. The selection logic 121 reads the byte data corresponding to the input address from the memory 113 when a decoded byte address, that is, a byte data selection signal, is received from the first address decoder 111. [ Then, the second address decoder 112 continuously reads the byte data corresponding to the decoded and input addresses. The selection logic 121 then selects byte data to rearrange the byte data in order and connects to the bearer shifter 130 through a path such as 510 and 520 in order to output the selected byte data. Here, the logic 121 reorders the byte-aligned byte data in the case of data having a bus width of two bytes or more.

An interface operation for byte-aligned data processing in an 8-bit interface device having such a structure will be described with reference to the accompanying drawings.

4 and 5, when the first byte address (A0, A1) is input, the first address decoder 111 decodes the first byte address inputted and selects the hardware logic unit 120 Lt; / RTI > Then, the selection logic 121 confirms the decoded input address and reads the byte data corresponding to the address from the memory 113. If a byte address is consecutively input after the first byte address, the second address decoder 112 decodes the second byte address and outputs the decoded second byte address to the selection logic 121. Then, as in the case of the first byte address, the byte data corresponding to the second address is read from the memory 113.

Then, the hardware logic unit 120 connects with the bearer shifter 130 according to the read of the byte data, and sequentially sends the read first and second byte data to the bearer shifter 130 through the corresponding path. This operation is performed continuously without time delay. When the address input through the second address decoder 112 is two or more bytes, the selection logic 121 of the hardware logic unit 120 sequentially arranges the N + 1 pieces of byte data sequentially input to the bearer shifter 130 ).                     

The bearer shifter 130 receiving the (N + 1) byte data outputs the final bit-addressed N-byte data using the byte data and the bit address received from the hardware logic unit 120. The hardware logic unit 120 and the bearer shifter 130 for extracting the byte data including the bit data by using the second address decoder 112 connected to the first address decoder 111 and the bearer shifter 130, , The overall bit data output operates without clock delay.

In the first embodiment of the present invention as described above, an interface device having an 8-bit bus width has been described as an example, but a case where the interface device has a 16-bit bus width will be described in the second embodiment of the present invention . Here, an interface device having a 16-bit bus width requires two 8-bit memories, and the final output bit address data is 2 bytes, so a 3-bit bearer shifter is required. Such an interface device will be described with reference to the accompanying drawings.

FIG. 6 is a diagram showing an interface device for processing a bit stream in the case of a 16-bit bus width according to a second embodiment of the present invention.

Referring to FIG. 6, the interface device 200 includes a memory 240 for storing byte-aligned data that are compressed and encoded to be continuously input from the transmitting side, And a decoding unit 210 for decoding the input byte address so as to be addressable. The interface apparatus 200 includes a hardware logic unit 220 for reading continuous byte data without delay and a 3-bit bearer shifter 230 for extracting only desired bit data from the read byte data do.

The decoding unit 210 includes a first byte address decoder 211 decoding and outputting desired A0 and A1 byte addresses, a second byte address decoder 212 decoding and outputting N + 1 bit addresses, N And a third byte address decoder 213 for decoding and outputting +2 bit addresses.

The memory unit 240 includes two memories 241 and 242 each having an 8-bit size for storing consecutive byte data input with a 16-bit bus width. In the memory unit 240, the row side represents a bit address address, and the column side represents a byte address address. When the first byte data is received, the first row of the first memory 241, that is, the byte address 0 is stored. When the next byte data is received, the first row of the second memory 242, 1 < / RTI > The consecutively input byte data are sequentially stored in the first and second memories.

The interface operation for processing the byte-aligned data in the interface device having the thus configured 16-bit bus width is performed in the same manner as the first embodiment of the present invention as described above, It will be omitted.

In the first and second embodiments of the present invention described above, an interface device having 8-bit and 16-bit bus widths and an interface operation for processing byte data have been described. However, in the third embodiment of the present invention, An interface device having a width and an interface operation will be described. Here, a processor having a 32-bit bus width requires four 8-bit memories, and since the finally outputted bit address data is 4 bytes, a 5-bit bearer shifter 330 is required.

7, the interface device 300 includes a memory unit 340 for storing byte-aligned data that are compressed and encoded to be continuously input from the transmission side, and a memory unit 340 for storing the byte data stored in the memory unit 340 as bits And a decoding unit 310 for decoding the input byte address so as to be addressable in units of a unit. The interface apparatus 300 includes a hardware logic unit 320 for reading continuous byte data without delay and a 5-bit bearer shifter 330 for extracting only desired bit data from the read byte data.

The decoding unit 310 includes a first address decoder 131 for decoding and outputting desired N-byte advices, and a second address decoder 131 for decoding N + 1, N + 2, N + 3, Third, fourth, and fifth byte address decoders 312, 313, 314, and 315 for decoding and outputting addresses, respectively.

The memory unit 340 includes four memories 341, 342, 343, and 344 each having an 8-bit size for storing consecutive byte data input with a 32-bit bus width. In the memory unit 340, the row side represents a bit address address, and the column side represents a byte address address. When the first byte data is received, the first row of the first memory 341, that is, the byte address 0 is stored. When the next byte data is received, the first row of the second memory 342, 1 < / RTI > When the next byte data is received, it is stored in the first row of the third memory 343, that is, the byte address 2 address. The consecutively inputted byte data are sequentially stored in the first, second, third and fourth memories 341, 342, 343 and 344.

The interface operation for processing the byte aligned data in the interface apparatus having the 32-bit bus width configured as described above is performed in the same manner as the first embodiment of the present invention as described above, so that the third embodiment of the present invention will be described in detail. It will be omitted.

On the other hand, if the bit data addressing interface is used for all the physical memories, 3 bits are increased in the entire address, so that the address area may be limited. To this end, a processor (inputting byte data) (expressed as a straight line, but can the processor be the same as the above-described interface device) uses a method as shown in FIG. 8 so as to simultaneously input a bit address and a byte address do. That is, when accessing a byte address map with a logical address map 820 that distinguishes by a bit 810 of a higher address when accessing a specific address, the byte address is outputted to the physical address map 830. On the other hand, when accessing the bit address map of the logical address map 820, the bit address is output to the physical address map 830. [

The address interface operation of the embodiments of the present invention will now be briefly described with reference to the flow chart of FIG.                     

In step 901, the interface device receives an 8-bit byte address when the size of the byte address, for example, the bus width is 8 bits, and confirms whether the byte address input in step 902 is the first byte address. If the input data is the first inputted byte address, the interface device decodes the data through the first address decoder in step 903, and then proceeds to step 905. Otherwise, in step 904, And then proceeds to step 905. [

Thereafter, in step 905, the interface device sends the decoded address to the hardware logic unit and reads the byte data corresponding to the decoded address from the memory. At this time, in step 906, the interface device checks whether the next byte address is input. If the next byte address is input, the process proceeds to step 903. If the next byte address does not exist, the interface device sequentially arranges the byte data read in step 907. Then, in step 908, the byte data aligned in order is output to the 3-byte byte bearer shifter having a size larger than the bus width size by one byte, for example, when the bus width size is 8 bits. Accordingly, in step 909, the interface device performs bit addressing using the bit data and the input bit address that are received from the bearer shifter and outputs the byte data aligned in order through the bearer shifter to the bit address . In step 910, the interface device finally outputs the desired bit addressed data and then terminates the operation.

While the invention has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention. Therefore, the scope of the present invention should not be limited to the embodiments described, but should be determined by the scope of the claims and equivalents thereof.

As described above, according to the present invention, there is no delay in reading data by using hardware having no clock delay such as a hardware logic unit and a bearer shifter, and since a hardware interface structure can be simplified, a bit using a variable- There is an effect that the load of the processor at the time of decoding the stream can be reduced.

Claims (4)

1. An interface apparatus for outputting desired bit data in variable-bit data and byte data arranged in units of bytes, comprising: A memory unit for receiving the byte data continuously from the transmission side and storing the byte data in the corresponding data area, A decoding unit for sequentially receiving and decoding byte addresses for reading the continuous byte data, A hardware logic unit for sequentially reading the byte data stored in the data area of the memory unit corresponding to the decoded byte addresses and arranging them in order; And a bearer shifter for outputting the desired bit data as byte-aligned data from the byte data arranged in the order using a bit address for desired bit data. The method according to claim 1, Wherein the memory unit includes a memory having a predetermined size of 8 bits according to a bus width size. The apparatus of claim 1, wherein the bearer shifter comprises: Wherein the memory has a size that is one byte larger than the total number of bytes of the byte data stored in the memory unit. 1. An interface method for outputting desired bit data in variable-bit data and byte-aligned byte data, Receiving the byte data continuously from a transmitting side and storing the byte data in a corresponding data area; Sequentially receiving and decoding byte addresses for reading the continuously received byte data, Sequentially reading byte data stored in a data area corresponding to the decoded byte addresses and arranging them in order; And outputting the desired bit data as byte-aligned data from the byte data arranged in the order using a bit address for the desired bit data.

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