JPH09260672A - Thin film semiconductor device and liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a thin film semiconductor device which hardly deteriorates in throughput, is high in reliability and excellent in device characteristics. SOLUTION: This semiconductor device is equipped with a transparent insulating substrate 100, a thin film semiconductor layer formed on the substrate 100, and a thin transistor provided to the thin film semiconductor later. The above thin film transistor is equipped with a high-resistance semiconductor channel region, a drain region 104, and a source region 103 both formed of low-resistance semiconductor and produced adjacent to the channel region, a gate insulating film 106 formed on the channel region, and a gate electrode 108 provided onto the gate insulating film 106, wherein the gate electrode 108 has a tapered upper side wall and a nearly vertical lower side wall.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor manufacturing device and a liquid crystal display device, and more particularly to a gate electrode of a thin film transistor of an active matrix type liquid crystal display device.

[0002]

2. Description of the Related Art Display devices such as electroluminescence, light emitting diodes, plasma displays, fluorescent displays, and liquid crystal display devices can have a thin display section, and therefore display devices such as office equipment and computers or special displays. Demand is increasing for use in devices.

Among these display devices, an active matrix type liquid crystal display (AM-LC) using a thin film transistor (TFT) as a pixel switching element.
D) is expected as a display with high image quality, high quality, and low power consumption, and has been extensively researched and developed.

A pol using polycrystalline silicon (poly-Si) as a channel active layer of a TFT for AM-LCD.
The y-SiTFT has high mobility and can be made finer when applied to a pixel TFT, and can be used not only as a pixel switching element but also as a peripheral drive circuit for controlling the pixel TFT. Therefore, poly
In the -SiTFT, since the peripheral drive circuit section can be formed simultaneously with the pixel section (drive circuit integrated LCD),
It is possible to reduce the mounting cost of the drive circuit chip and narrow the frame.

At present, commercially available drive circuit integrated type LC
D is a small and medium-sized display used for a projection type display and a viewfinder. In the manufacturing process, a solid phase growth method (a process of about 600 ° C.) or a thermal oxide film (a process of 900 ° C. or higher) is required to form a poly-Si film, and thus a high temperature process is used. Therefore, it is required to use an expensive substrate such as a quartz substrate or a high heat resistant substrate.

Therefore, in a low temperature process of 450 ° C. or lower (a temperature that the glass substrate can withstand), a low cost large area glass substrate used in an a-Si (amorphous silicon) TFT LCD can be used, and a film quality of po equivalent to that of the high temperature process can be obtained.
If the ly-Si film and the gate oxide film can be formed and further the impurity activation process can be performed, the effects such as the cost reduction and the throughput improvement in the LCD panel multi-chambering can be achieved.

As a technique for forming a poly-Si film by a low temperature process and a technique for activating impurities, a crystallization technique for an a-Si film by excimer laser annealing (ELA) and an impurity activation technique have been studied. This technology is a-S
Since the i film is instantly melted and crystallized, the substrate is less damaged by heat, and a low cost glass substrate can be used.

Here, a part of the cross-sectional structure of a general poly-Si TFT will be described with reference to FIG. FIG.
In the poly-Si TFT shown in FIG.
A high resistance semiconductor layer 502 is formed on a transparent insulating substrate 500 coated with. This high resistance semiconductor layer 50
In No. 2, an a-Si: H film is formed on the insulating film 501 by, for example, a plasma CVD method to a thickness of 50 nm to 70 nm, and the film is subjected to thermal annealing to obtain a-Si: H.
Dehydrogenate the H film and then ELA the a-Si film.
Is formed by forming poly-Si.

The high resistance semiconductor layer 502 is in contact with a portion to be a channel, and the low resistance semiconductor layers 503 and 5 are provided on both sides thereof.
04 are provided. Low resistance semiconductor layers 503 and 504
Is formed by implanting impurities such as P into the high resistance semiconductor layer 502 and then activating the impurities by heat treatment or the like.

APCVD is performed on the high resistance semiconductor layer 502.
The gate insulating film 505 is formed with a thickness of 70 nm to 100 nm by a film forming method such as PECVD, ECR-PECVD, or the like. A gate electrode 506 is provided on the gate insulating film 505. Low resistance semiconductor layer 503,
A source electrode 509 and a drain electrode 510 are connected to 504, respectively. An interlayer insulating film 511 is provided to insulate the gate electrode 508, the source electrode 509, and the drain electrode 510.

The poly-Si shown in FIG. 11 described above is used.
In the TFT, the gate electrode 508 needs to have a certain thickness for the following reasons. 1. In order to reduce the parasitic capacitance of the device, impurity implantation into the source / drain regions is performed using the gate electrode as a mask. If the gate electrode does not have an appropriate film thickness,
Impurities are injected into the gate insulating film and the channel region, deteriorating the device characteristics. Specifically, the gate breakdown voltage deteriorates or Vth shifts.

2. If the same material is used, the thicker the film thickness, the lower the line resistance. Therefore, considering the delay of the gate pulse and the like, the film thickness is required to some extent. Above 2
For one reason, it is known from the study by the present inventors that, for example, assuming a gate electrode made of an alloy of Mo and Ta, 250 nm to 350 nm or more is required.

In the above examples, the side wall of the gate electrode rises almost vertically and the film thickness is 250 nm.
If the thickness is from 350 nm to 350 nm, the interlayer insulating film formed thereover is apt to have poor coverage (the circled portion in FIG. 11) and the yield is reduced. Therefore, in FIG.
As shown in FIG. 2, it is conceivable that the side wall of the gate electrode 608 has a tapered structure to reduce the coverage defect.

However, if the side wall of the gate electrode has a taper structure with a taper angle of about 30 degrees, for example, the following problems occur. That is, as described above, the impurity implantation into the source / drain regions is performed using the gate electrode as a mask. When such a method is used, if the side wall of the gate electrode is processed into a taper shape, the gate insulating film and the channel region below the end of the gate electrode are formed in a shape corresponding to the taper shape during impurity implantation. Impurities are implanted into (the portion indicated by reference numeral 610 in FIG. 13).

When an energy beam such as excimer laser annealing is used to activate the implanted impurities,
Impurity-implanted portion 61 under the tapered portion
The energy beam does not reach 0 and cannot be activated. In such a case, the Id-Vg characteristic of the TFT deteriorates.

In a low-temperature process using a glass substrate for forming a liquid crystal display, the glass cannot withstand activation by thermal annealing at 600 ° C. or higher.
Not used. Therefore, it is necessary to use an energy beam such as excimer laser annealing.

Therefore, the structure in which the side wall of the gate electrode is tapered is not suitable for a process using an energy beam such as excimer laser annealing. As described above, the structure of the conventional gate electrode has the following problems.

1. If the gate electrode having the required film thickness is processed perpendicularly to the gate insulating film, the coverage defect of the interlayer insulating film is caused and the yield is lowered.

2. If the side wall of the gate electrode is tapered so as to prevent coverage failure, a region with insufficient activation of impurities is formed at the gate end, and a device having good characteristics cannot be obtained. .

[0020]

SUMMARY OF THE INVENTION The present invention has been made under the above circumstances, and an object thereof is to provide a thin film semiconductor device having high reliability, high throughput, and no deterioration in throughput.

[0021]

In order to solve the above problems, the present invention (claim 1) provides a transparent insulating substrate, a thin film semiconductor layer formed on the transparent insulating substrate, and the thin film semiconductor layer. A thin film transistor formed on the channel region, the thin film transistor comprising: a channel region formed of a high resistance semiconductor region; a drain region and a source region formed of a low resistance semiconductor region arranged in contact with the channel region; A gate insulating film formed on
A gate electrode formed on the gate insulating film,
The thin film semiconductor device is characterized in that the gate electrode has a tapered upper side wall and a substantially vertical lower side wall.

According to the present invention (claim 2), in the thin film semiconductor device (claim 1), the gate electrode has a laminated structure of at least two kinds of films made of different materials.

According to the present invention (claim 3), in the thin film semiconductor device (claim 1), the taper angle of the lower side wall of the gate electrode is 80 to 90 degrees. The present invention (Claim 4) is characterized in that, in the thin film semiconductor device (Claim 1), the taper angle of the upper side wall of the gate electrode is 25 degrees to 45 degrees.

According to the present invention (claim 5), a pair of substrates, a liquid crystal layer enclosed between these substrates, pixel display portion electrodes arranged in a matrix on one of the pair of substrates, In a liquid crystal display device including a thin film transistor connected to the pixel display electrode, the thin film transistor includes a channel region including a high resistance semiconductor region and a drain region including a low resistance semiconductor region arranged in contact with the channel region. And a source region, a gate insulating film formed on the channel region, and a gate electrode formed on the gate insulating film, the gate electrode being substantially perpendicular to a taper-shaped upper side wall. And a lower side wall of the liquid crystal display device.

The thin film semiconductor device of the present invention will be described below.
This will be described more specifically. The thin film semiconductor device of the present invention is characterized in that the gate electrode has a tapered upper side wall and a substantially vertical lower side wall.

The bottom sidewall need only be substantially vertical and need not be perfectly vertical. In this case, almost vertical means
It means that the angle formed with the horizontal plane is 80 to 90 degrees. The angle is preferably 85 to 90 degrees. If the angle between the lower side wall and the horizontal plane is less than 80 degrees, the insufficiently activated portion is formed below the end portion of the gate electrode, and it is difficult to obtain a TFT having good characteristics.

The angle formed between the upper side wall and the horizontal plane is preferably 25 to 45 degrees, more preferably 30 to 40 degrees. If the angle between the upper side wall and the horizontal plane is less than 25 degrees, the angle between the lower side wall and the upper side wall will be large, and the upper cover will be covered.
Defects are likely to occur, and if the angle exceeds 45 degrees, the angle formed with the horizontal plane becomes large, and in this case also, coverage defects are likely to occur at the upper side.

If the angle between the upper side wall and the horizontal plane is too small, an intermediate side wall is provided between the upper side wall and the lower side wall so that the angle between the upper side wall and the lower side wall is intermediate between the two. Good. That is, the present invention is not limited to the case where the side wall having the taper angle is one step, and a side wall having a plurality of steps of the taper angle may be provided.

Materials for forming the gate electrode in the thin film semiconductor device of the present invention include Mo, Al, Ta, W and C.
Examples thereof include u and polysilicon doped with impurities.

The gate electrode is not limited to a single layer made of a single material, but may have a multi-layer structure made of a plurality of materials. In this case, it is possible to form a multi-layer structure of a layer having an upper side wall and a layer having a lower side wall. The layer having the upper side wall can be made of Mo, Mo / Ta, Mo / W and polysilicon doped with impurities, and the layer having the lower side wall can be made of Al, W or Cu.

As the combination, for example, (upper part, lower part) is (Mo / Ta, Al), (Mo / W, Al),
(Mo, Al), (Mo, n ⁺ polySi), (Mo / T
a, n ⁺ polySi) and the like.

As a method of forming the gate electrode, the upper side wall and the lower side wall can be formed separately by different etching methods. That is, the upper side wall having a predetermined taper angle is subjected to isotropic etching such as CDE (chemical dry etching) or wet etching, and the substantially vertical lower side wall is subjected to RIE (reactive ion etching).
Such anisotropic etching can be performed.

As described above, in the thin film semiconductor device according to the present invention, since the side wall of the upper part of the gate electrode is formed in a tapered shape, the yield reduction due to the coverage failure due to the gate electrode structure is prevented and the active state is reduced. It is possible to obtain a device structure that is free from defective formation. As a result, it is possible to efficiently obtain a thin film semiconductor device having high reliability and excellent device characteristics without lowering throughput.

[0034]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings. Example 1 FIG. 1 is a sectional view showing a semiconductor device according to a first example of the present invention.

In the semiconductor device shown in FIG. 1, a transparent insulating substrate 100 coated with a transparent insulating film 101 has a high resistance semiconductor layer 102 made of polysilicon and low resistance semiconductor layers 103 and 104 formed on both sides thereof. ing. These polysilicon layers 102, 103, 104 are formed by forming an a-Si: H film on the transparent insulating film 101, for example, plasma CV.
It is formed by the D method to a thickness of 50 to 80 nm, and then subjected to thermal annealing to dehydrogenate the a-Si: H film, and then to form poly-Si by ELA.

The high resistance semiconductor layer 102 acts as a channel, and the low resistance semiconductor layer 1 provided in contact with the channel.
03 and 104 are formed by implanting impurities such as P and then activating them by heat or the like. On top of the high resistance semiconductor layer 102, APCVD, PECVD, EC
The gate insulating film 10 is formed by a film forming method such as R-PECVD.
6 is formed to a thickness of 70 nm to 100 nm. A gate electrode 108 is provided on the gate insulating film 106. A source electrode 109 and a drain electrode 110 are connected to the low resistance semiconductor layers 103 and 104, respectively. An interlayer insulating film 111 is provided to insulate the gate electrode 108, the source electrode 109, and the drain electrode 110.

The gate electrode 108, as shown in FIG.
The upper part is processed into a taper shape. in this way,
By forming the gate electrode structure with a tapered side wall on the upper portion, a decrease in yield due to defective coverage due to a step difference in the gate electrode can be solved, and a device structure without defective activation can be provided. it can. As a result, it is possible to efficiently obtain a TFT having high reliability and excellent device characteristics without lowering throughput.

Embodiment 2 FIGS. 2 and 3 are cross-sectional views showing a manufacturing process of the semiconductor device shown in FIG. First, an a-Si: H film having a thickness of 50 to 80 nm is formed on the transparent insulating substrate 200 coated with the transparent insulating film 201 by, for example, plasma CVD method or LPCVD method, and the temperature is 450 ° C. for 1 hour. Dehydrogenation is performed from the a-Si: H film by performing thermal annealing to a certain degree. Next, the high resistance semiconductor layer 202 is formed by converting the a-Si film into poly-Si by ELA.

Next, on the high resistance semiconductor layer 202, AP
The gate insulating film 206 is formed to have a thickness of 70 nm to 100 nm by a film forming method such as CVD, PECVD, or ECR-PECVD method.
Formed to a thickness of After that, the metal film 2 to be the gate electrode
08a is formed. The material of the metal film 208a is M
Examples thereof include o, Al, Ta, W, Cu and alloys thereof, a laminated film or a doped silicon film. Metal film 208a
The film thickness of is preferably about 250 nm to 400 nm (see FIG. 2).
(A)).

Next, a resist is applied and patterned by a photolithography process to form a resist pattern 290. And this resist pattern 2
Using 90 as a mask, the film to be the gate electrode is tapered by CDE (chemical dry etching) or the like to obtain a structure 208b (FIG. 2B).

Next, after removing the resist pattern 290, a resist is applied again and patterned by a photolithography process to form a resist pattern 291. Then, using the resist pattern 291 as a mask, the structure 208b is processed almost vertically by RIE (reactive ion etching) or the like, and the gate electrode 20 is processed.
8 is obtained (FIG. 2 (c)).

Then, using the gate electrode 208 as a mask, impurities are implanted into a part of the high resistance semiconductor layer to form the low resistance semiconductor layers 203 and 204 (FIG. 3A).
Next, after forming the interlayer insulating film 211, the impurities are activated by ELA (FIG. 3B).

Further, a contact hole is opened and the source
A conductive film to be a drain electrode is formed and patterned to form a source electrode 209 and a drain electrode 210 (FIG. 3C).

By adopting the above manufacturing process,
As shown in the figure, the gate electrode 208 has a tapered upper portion. By using the semiconductor element having such a structure, that is, by forming the gate electrode structure with two-step angles, it is possible to prevent the yield from being reduced due to the coverage failure due to the shape of the gate electrode. In addition, a device structure without defective activation can be obtained. As a result, it is possible to efficiently manufacture a TFT with high reliability and excellent device characteristics without a decrease in throughput.

Example 3 FIG. 4 is a sectional view showing a semiconductor device according to a second example of the present invention. In the semiconductor element shown in FIG. 4, a transparent insulating substrate 300 coated with a transparent insulating film 301 has a high resistance semiconductor layer 302 made of polysilicon and low resistance semiconductor layers 303 and 304 formed on both sides thereof. These polysilicon layers 302, 303, 304 are formed by forming an a-Si: H film on the transparent insulating film 301, for example, plasma CV.
It is formed by the D method to a thickness of 50 to 80 nm, and then subjected to thermal annealing to dehydrogenate the a-Si: H film, and then to form poly-Si by ELA.

The high resistance semiconductor layer 302 acts as a channel, and the low resistance semiconductor layer 3 provided in contact with the channel.
03 and 304 are formed by implanting impurities such as P and then activating them by heat or the like. APCVD, PECVD, EC are formed on the high resistance semiconductor layer 302.
The gate insulating film 30 is formed by a film forming method such as R-PECVD.
6 is formed to a thickness of 70 nm to 100 nm. The gate electrode 3 having a two-layer structure is formed on the gate insulating film 306.
08a and 308b are provided. Low resistance semiconductor layer 3
A source electrode 309 and a drain electrode 310 are connected to 03 and 304, respectively. Gate electrodes 308a, 3
An interlayer insulating film 311 is provided to insulate the 08b, the source electrode 309, and the drain electrode 310.

As shown in FIG. 4, the side wall of the gate electrode 308b is tapered. On the other hand, the gate electrode 308a is processed so as to have a side wall that is nearly vertical. In this way, by forming the gate electrode structure with a tapered side wall on the upper portion, a decrease in yield due to defective coverage due to a step of the gate electrode is eliminated, and a device structure without defective activation is formed. Can be provided. As a result, it is possible to efficiently obtain a TFT having high reliability and excellent device characteristics without lowering throughput.

Embodiment 4 FIGS. 5 and 6 are cross-sectional views showing a manufacturing process of the semiconductor device shown in FIG. First, an a-Si: H film is formed on the transparent insulating substrate 400 coated with the transparent insulating film 401 to a thickness of 50 to 80 nm by, for example, the plasma CVD method or the LPCVD method, and the temperature is 450 ° C. for 1 hour. Dehydrogenation is performed from the a-Si: H film by performing thermal annealing to a certain degree. Next, the high resistance semiconductor layer 402 is formed by converting the a-Si film into poly-Si by ELA.

Next, on the high resistance semiconductor layer 402, AP
The gate insulating film 406 is formed to 70 nm to 100 nm by a film forming method such as CVD, PECVD, or ECR-PECVD method.
Formed to a thickness of After that, a lower metal film 408a and an upper metal film 408b which will serve as gate electrodes are stacked. The materials of the metal films 408a and 408b are Mo, Al and T.
Examples thereof include a, W, Cu and alloys thereof, a laminated film or a doped silicon film. The thickness of the lower metal film 408a is preferably 200 to 350 nm, and the thickness of the upper metal film 408b is preferably 50 to 200 nm. Metal film 408a,
The total film thickness of 408b is preferably about 250 nm to 400 nm (FIG. 5A).

Next, a resist is applied and patterned by photolithography to form a resist pattern 4.
Form 90. Then, this resist pattern 490
Using the as a mask, the metal film 408b is etched by CDE (chemical dry etching) or the like.
An upper layer gate electrode 408c having a par-shaped side wall is formed (FIG. 5B).

After that, after removing the resist pattern 490, a resist is applied again and patterned by a photolithography process to form a resist pattern (not shown). Then, using this resist pattern as a mask, the lower metal film 408a is processed by RIE (reactive ion etching) or the like so that the side walls are substantially vertical to obtain a lower gate electrode 408d (FIG. 5).
(C)). In this case, the lower metal film 408a may be processed by using the upper gate electrode 408c as a mask instead of the resist pattern 491.

After that, upper and lower gate electrodes 408
Impurities are implanted into a part of the high resistance semiconductor layer 402 by using c and d as masks to form the low resistance semiconductor layers 403 and 40.
4 is formed (FIG. 6A). Next, the interlayer insulating film 41
After 1 is formed, the impurities are activated by ELA (FIG. 6B).

Next, a contact hole is opened and the source
A film to be a drain electrode is formed and patterned to form a source electrode 409 and a drain electrode 410 (FIG. 6).
(C)).

By the above method, the gate electrode 40
Of 8c and 408d, the upper gate electrode 408c is processed to have a tapered side wall. By using the semiconductor device having such a structure, that is, by forming the side wall of the gate electrode with two-step angles, the yield decrease due to the coverage failure due to the gate electrode structure is prevented, and the active It is possible to provide a device structure that is free from defective formation. As a result, a TFT with high reliability and excellent device characteristics without a decrease in throughput
Can be obtained efficiently.

In the gate electrode processing step of the above manufacturing process, depending on the kind of metal or the crystal orientation thereof, even if the same etching condition is used, the etching is performed perpendicularly to the taper-shaped etching. There are things.
Therefore, in the gate electrode processing step of the above manufacturing process,
By appropriately selecting the materials of the upper metal film and the lower metal film, both can be processed with one resist pattern, and the photolithography process can be reduced.

It should be noted that the lower layer gate which is processed almost vertically
The taper angle of the gate electrode 408d may be an angle that satisfies the following expression for the following reason. That is, even if the gate electrode is not completely vertical, if the gate electrode is processed close to vertical, the region into which impurities are implanted is extremely narrow below the gate electrode, and in such a region, activation by laser annealing is also possible. It is possible. For example, 50n in the lateral direction from the source / drain to the bottom of the gate
It has been known from our research that a region of about m can be activated by laser annealing, so that a taper angle of that extent is acceptable.

Specifically, tan a ≧ X / 50 should be satisfied, where Xnm is the film thickness of the lower gate electrode which is processed to be nearly vertical and the taper angle is a degree. Fifth Embodiment FIG. 7 is a sectional view showing a liquid crystal display device according to a third embodiment of the present invention.

In the liquid crystal display device shown in FIG. 7, liquid crystal 510 is enclosed between a pair of substrates 500a and 500b, and the pixel display section connected to the pixel display section electrodes arranged in a matrix on one substrate 500a. The pixel thin film transistor 520 is arranged. A driving circuit 53 for driving the pixel thin film transistor 520 is provided around the pixel display unit.
0 is provided.

The structure of the thin film transistor 520 is the structure shown in the first embodiment 1 or the third embodiment. That is, the upper portion of the gate electrode 508 has a tapered side wall. The electrode 5 forming the auxiliary capacitance
Similarly to the gate electrode 30, the upper portion 30 has a tapered side wall. The electrode 530 forming the storage capacitor may also have poor coverage above it, and
This is because it is formed at the same time as the gate electrode 508.

With such a structure, the yield is lowered due to poor coverage due to the electrode structure,
A device structure without defective activation can be obtained. As a result, it is possible to efficiently obtain a liquid crystal display device having high reliability and excellent device characteristics without lowering throughput.

In the above embodiments, the device protective film is not particularly described, but it may be formed if necessary. Although the coplanar TFT has been described in the present description, various modifications can be made without departing from the gist of the invention. For example, the present invention can be applied to stagger type TFTs as shown in FIGS.

Further, as shown in the fifth embodiment, the drive circuit can be composed of a CMOS formed of an n-channel TFT and a p-channel TFT. Especially CMOS
When the drive circuit is formed by, a liquid crystal display device with low power consumption can be obtained.

The pixel thin film transistor may have an LDD structure or a multi-gate (double-gate) TFT having a plurality of gate electrodes in order to reduce the leak current (current flowing when the TFT is OFF).

[0064]

As described above, in the thin film semiconductor device according to the present invention, since the side wall of the upper part of the gate electrode is formed in a tapered shape, the yield reduction due to the coverage failure due to the gate electrode structure is prevented, In addition, a device structure without defective activation can be obtained. as a result,
It is possible to efficiently obtain a semiconductor device having high reliability and excellent device characteristics without lowering throughput.

[Brief description of drawings]

FIG. 1 is a sectional view showing a structure of a thin film transistor according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a manufacturing process of the thin film transistor shown in FIG.

FIG. 3 is a cross-sectional view showing a manufacturing process of the thin film transistor shown in FIG.

FIG. 4 is a sectional view showing a structure of a thin film transistor according to a second embodiment of the present invention.

FIG. 5 is a cross-sectional view showing a manufacturing process of the thin film transistor shown in FIG.

FIG. 6 is a cross-sectional view showing a manufacturing process of the thin film transistor shown in FIG.

FIG. 7 is a sectional view showing the structure of a liquid crystal display device according to a third embodiment of the present invention.

FIG. 8 is a sectional view showing a structure of a liquid crystal display device according to a modification of the present invention.

FIG. 9 is a sectional view showing the structure of a liquid crystal display device according to a modification of the invention.

FIG. 10 is a sectional view showing the structure of a liquid crystal display device according to a modification of the invention.

FIG. 11 is a cross-sectional view showing the structure of a conventional thin film transistor.

FIG. 12 is a cross-sectional view showing the structure of another example of a conventional thin film transistor.

FIG. 13 is an enlarged cross-sectional view showing a gate electrode of a conventional thin film transistor.

[Explanation of symbols]

100, 200, 300, 400, 500 ... Substrate 101, 201, 301, 401, 501 ... Substrate protective film 102, 202, 302, 402, 402 ... High resistance semiconductor 103, 203, 303, 403, 503 ... Source region 104 , 204, 304, 404, 504 ... Drain region 106, 206, 306, 406, 506 ... Gate insulating film 108, 208, 308a, 308b, 408c, 40
8d, 508, 608 ... Gate electrode 109, 209, 309, 409, 509 ... Source electrode 110, 210, 310, 410, 510 ... Drain electrode 111, 211, 311, 411, 511 ... Interlayer insulating film 290, 291, 490 ... resist

Claims (5)

[Claims] 1. A transparent insulating substrate, a thin film semiconductor layer formed on the transparent insulating substrate, and a thin film transistor formed on the thin film semiconductor layer, the thin film transistor comprising a high resistance semiconductor region. A channel region,
A drain region and a source region formed of a low resistance semiconductor region arranged in contact with the channel region, a gate insulating film formed on the channel region, and a gate electrode formed on the gate insulating film. The gate electrode has a taper-shaped upper side wall and a substantially vertical lower side wall. 2. The thin film semiconductor device according to claim 1, wherein the gate electrode has a laminated structure of at least two films made of different materials. 3. The thin film semiconductor device according to claim 1, wherein a taper angle of a lower side wall of the gate electrode is 80 degrees to 90 degrees. 4. The taper angle of the upper side wall of the gate electrode is 25 degrees to 45 degrees.
3. The thin film semiconductor device according to claim 1. 5. A pair of substrates, a liquid crystal layer enclosed between the substrates, a pixel display portion electrode arranged in a matrix on one of the pair of substrates, and connected to the pixel display portion electrode. In the liquid crystal display device including the thin film transistor, the thin film transistor includes a channel region formed of a high resistance semiconductor region, a drain region and a source region formed of a low resistance semiconductor region arranged in contact with the channel region, and the channel. A gate insulating film formed on the region and a gate electrode formed on the gate insulating film, the gate electrode having a tapered upper side wall and a substantially vertical lower side wall. Liquid crystal display device characterized by.