JPH09260569A - Resin sealed semiconductor device - Google Patents
Resin sealed semiconductor deviceInfo
- Publication number
- JPH09260569A JPH09260569A JP8067626A JP6762696A JPH09260569A JP H09260569 A JPH09260569 A JP H09260569A JP 8067626 A JP8067626 A JP 8067626A JP 6762696 A JP6762696 A JP 6762696A JP H09260569 A JPH09260569 A JP H09260569A
- Authority
- JP
- Japan
- Prior art keywords
- lead
- inner lead
- resin
- self
- twisted
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、樹脂封止型半導体
装置に関するものであり、特に半導体装置の組立技術に
使用されるものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resin-encapsulated semiconductor device, and more particularly to a semiconductor device assembly technique.
【０００２】[0002]
【従来の技術】電極となるパッドが中央に配置されてい
るＬＯＣ（Ｌｅａｄ Ｏｎ Ｃｈｉｐ）構造を有する樹
脂封止型半導体装置の従来の樹脂封止工程を図を用いて
説明する。2. Description of the Related Art A conventional resin encapsulation process for a resin encapsulation type semiconductor device having a LOC (Lead On Chip) structure in which a pad serving as an electrode is arranged in the center will be described with reference to the drawings.
【０００３】図３の（１）に示すように、配線となるリ
ード３１０が、接着剤３０２により半導体素子が形成さ
れている半導体チップ３０１の上に固定されており、ワ
イヤーボンディングとなるワイヤー３０６を介して、半
導体チップ３０１の上に形成された電極となるパッド３
０５に電気的に接続されている。また、図３の（２）
は、図３の（１）に示される半導体装置の正面図を、図
３の（３）は、図３の（１）に示される半導体装置のワ
イヤー３０６部分の拡大斜視図を示している。As shown in (1) of FIG. 3, a lead 310 which is a wiring is fixed on a semiconductor chip 301 on which a semiconductor element is formed by an adhesive 302, and a wire 306 which is a wire bonding is fixed. Via the pad 3 which will be an electrode formed on the semiconductor chip 301
05 is electrically connected. In addition, (2) in FIG.
3A is a front view of the semiconductor device shown in FIG. 3A, and FIG. 3C is an enlarged perspective view of the wire 306 portion of the semiconductor device shown in FIG. 3A.
【０００４】次に、図４の（１）に示すように、該半導
体装置を型４１５に入れ、この型４１５に設けられた樹
脂注入穴４２５から樹脂を注入する。また、図４の
（２）は図４の（１）におけるＡ断面図を、図４の
（３）は図４におけるＢ断面図を示している。Next, as shown in FIG. 4A, the semiconductor device is put in a mold 415, and a resin is injected from a resin injection hole 425 provided in the mold 415. 4 (2) is a sectional view taken along line A in FIG. 4 (1), and FIG. 4 (3) is a sectional view taken along line B in FIG.
【０００５】次に、図５に示される様に、注入された樹
脂が固まった後、型４１５を取り外す。また、リード５
１０において、樹脂５０７に覆われた部分を特にインナ
ーリード５０３、樹脂５０７に覆われていない外側の部
分を特にアウターリード５０８という。Next, as shown in FIG. 5, after the injected resin has set, the mold 415 is removed. Also, lead 5
In FIG. 10, the portion covered with the resin 507 is called an inner lead 503, and the outer portion not covered with the resin 507 is called an outer lead 508.
【０００６】型４１５を取り外した後、アウターリード
５０８の余分な部分を切断し、切断されずに残ったアウ
ターリード５０８を所望の形状に曲げ加工（図示せず）
する事により樹脂封止型半導体装置が形成される。After removing the mold 415, an excess portion of the outer lead 508 is cut, and the outer lead 508 left uncut is bent into a desired shape (not shown).
By doing so, a resin-sealed semiconductor device is formed.
【０００７】また、図６の（１）に示す様に、樹脂を注
入する際、半導体チップ６０１の上面に固定されたリー
ド６１０が障害となる為、かつ、半導体チップ６０１と
型６１６との距離ａ及びｂが異なる為に、半導体チップ
６０１の上面での樹脂の注入速度と、半導体チップ６０
１の下面でのそれが異なる。この樹脂の注入速度の異差
のため、半導体チップ６０１及びリード６１０にねじれ
応力６２０がかかる。特に、リード６１０は０．１２５
ｍｍから０．２ｍｍと非常に薄い金属板から形成されて
いるので上下方向の強度が弱い。この為、該応力６２０
によりリード６１０が変形し、半導体チップ６０１が傾
いてしまう。Further, as shown in FIG. 6A, when the resin is injected, the lead 610 fixed to the upper surface of the semiconductor chip 601 becomes an obstacle, and the distance between the semiconductor chip 601 and the mold 616 is increased. Since a and b are different, the resin injection speed on the upper surface of the semiconductor chip 601 and the semiconductor chip 60
It is different on the bottom of 1. Due to the difference in the injection speed of the resin, the torsion stress 620 is applied to the semiconductor chip 601 and the lead 610. In particular, the lead 610 is 0.125
Since it is formed from a very thin metal plate of mm to 0.2 mm, the strength in the vertical direction is weak. Therefore, the stress 620
As a result, the lead 610 is deformed and the semiconductor chip 601 is tilted.
【０００８】また、図６の（２）に示す様に、近年の半
導体装置の多機能化により半導体チップ６０１の幅Ｗを
含めたチップ面積が大きくなる傾向にある。また、ワイ
ヤーボンディングの接続技術の制約からワイヤー６０６
の長さは４ｍｍ程度が限界である。この為、チップ面積
が大きくなると必然的にリード６１０を長くしなければ
ならないので、リード６１０の上下方向の強度は一層弱
くなる傾向にある。また、リード６１０を長くする事
は、リード６１０の自己インダクタンス及び自己キャパ
シタンスの増大を招き、半導体装置の特性劣化の原因と
もなる。Further, as shown in (2) of FIG. 6, the chip area including the width W of the semiconductor chip 601 tends to increase due to the recent multifunctionalization of semiconductor devices. In addition, the wire 606 is restricted due to the limitation of the wire bonding connection technology.
The length is limited to about 4 mm. For this reason, when the chip area increases, the lead 610 inevitably needs to be lengthened, and therefore the strength of the lead 610 in the vertical direction tends to become weaker. Further, making the lead 610 longer leads to an increase in the self-inductance and the self-capacitance of the lead 610, which also causes deterioration of the characteristics of the semiconductor device.
【０００９】この問題を解決するために、リード６１０
を厚くする事によりリード６１０の上下方向の強度を増
強する方法がある。しかし、リード６１０を厚くする
と、前述したリード６１０の自己インダクタンス及び自
己キャパシタンスの増大を招き、半導体装置の特性が劣
化するだけではなく、動作不能となる事もある。In order to solve this problem, the lead 610 is used.
There is a method of increasing the strength of the lead 610 in the vertical direction by increasing the thickness. However, if the lead 610 is thickened, the self-inductance and the self-capacitance of the lead 610 described above are increased, which not only deteriorates the characteristics of the semiconductor device but also renders it inoperable.
【００１０】[0010]
【発明が解決しようとする課題】上述の様に、樹脂注入
工程におけるリードの変形を抑制する為、リードの強度
を増強する必要がある。この為、リードを厚くしていた
が、リードの自己インダクタンス及び自己キャパシタン
スの増大を招き、半導体装置の特性の劣化を招いてい
た。As described above, in order to suppress the deformation of the leads during the resin injection process, it is necessary to increase the strength of the leads. Therefore, although the lead is thickened, the self-inductance and the self-capacitance of the lead are increased and the characteristics of the semiconductor device are deteriorated.
【００１１】本発明は、リードの自己インダクタンス及
び自己キャパシタンスを増大させることなく、リードの
強度を増強させる事により、高歩留まり、かつ、高性能
な樹脂封止型半導体装置を提供する事を目的とする。It is an object of the present invention to provide a high-yield and high-performance resin-encapsulated semiconductor device by increasing the strength of the lead without increasing the self-inductance and self-capacitance of the lead. To do.
【００１２】[0012]
【課題を解決するための手段】上述のような目的を達成
するために、本発明は、前記インナーリードの前記接着
剤の付いていない部分に捻り加工が施されている事を特
徴とする。本発明は、インナーリードの一部分が捻り加
工されているのでリードの上下方向の強度を増強する事
ができ、インナーリードの幅が捻り加工によって見かけ
上細くなるので、自己インダクタンス及び自己キャパシ
タンスを低減する事が出来る。その上、捻り加工により
隣接するインナーリードの間隔も広くなるので、隣接す
るリード間の相互インダクタンス及び相互キャパシタン
スも低減する事が出来る。In order to achieve the above object, the present invention is characterized in that a portion of the inner lead where the adhesive is not attached is twisted. In the present invention, since a part of the inner lead is twisted, the strength of the lead in the vertical direction can be enhanced, and the width of the inner lead is apparently thinned by the twisting, so that the self-inductance and the self-capacitance are reduced. I can do things. In addition, since the distance between the adjacent inner leads is widened by the twisting process, mutual inductance and mutual capacitance between the adjacent leads can be reduced.
【００１３】[0013]
【発明の実施の形態】本発明の実施形態を図を用いて詳
細に説明する。インナーリードの捻り加工の方法を説明
する。図１の（１）に示すように、インナーリード１０
３の先端部分と、その先端部分からある程度間隔をあけ
た部分の二箇所にストリッパー１１１により上下方向か
ら加圧する事によりインナーリード１０３を固定し、ロ
ーラーポンチ１１２を通す。Embodiments of the present invention will be described in detail with reference to the drawings. A method of twisting the inner lead will be described. As shown in (1) of FIG. 1, the inner lead 10
The inner lead 103 is fixed by pressurizing the stripper 111 from above and below at two points, that is, the tip portion of 3 and a portion spaced from the tip portion to some extent, and the roller punch 112 is passed through.
【００１４】次に、図１の（２）に示すように、ローラ
ーポンチ１１２を上下より押す事により、インナーリー
ド１０３に捻り加工を施す。また、インナーリード１０
３の捻り加工が施されていない先端部分は、後述のワイ
ヤーボンディング工程の信頼性の確保のため、０．４ｍ
ｍ以上ある方が望ましい。Next, as shown in FIG. 1B, the inner punch 103 is twisted by pushing the roller punch 112 from above and below. Also, the inner lead 10
The tip portion of 3 which is not twisted is 0.4 m in order to secure the reliability of the wire bonding process described later.
It is desirable to have m or more.
【００１５】次に、図２に示すように、捻り加工された
インナーリード２０３の先端部分に接着剤２０２をが張
り付けられ、半導体チップ２０４の上に固定される。そ
の後、このインナーリード２０３と半導体チップ２０４
の上の電極となるパッド２０５がワイヤー２０６によっ
て電気的に接続される。その後、前述の樹脂封止工程に
よって樹脂封止型半導体装置が形成される。Next, as shown in FIG. 2, an adhesive 202 is attached to the tip end portion of the twisted inner lead 203 and fixed on the semiconductor chip 204. Then, the inner lead 203 and the semiconductor chip 204
The pad 205 serving as an electrode on the top of the substrate is electrically connected by the wire 206. After that, the resin-sealed semiconductor device is formed by the resin-sealing step described above.
【００１６】また、ワイヤー２０６とインナーリード２
０３とのボンディング性を考慮して、上述の捻り加工の
後に、インナーリード２０３の先端部分にのみ金または
銀メッキを施しても良い。更に、インナーリード２０３
の先端部分はフラットであるので、ワイヤー２０６を形
成する際のボンディング性には全く影響を与えない。Further, the wire 206 and the inner lead 2
In consideration of the bondability with 03, only the tip portion of the inner lead 203 may be plated with gold or silver after the above-mentioned twisting process. Furthermore, the inner lead 203
Since the tip of the wire is flat, it does not affect the bondability when the wire 206 is formed.
【００１７】また、従来はインナーリード２０３の下面
（先端部分）に張り付けられた接着剤２０２は、多数本
のリード毎に張り付けられているのが一般的であるが、
捻り加工されたリードは上下方向の強度が向上するの
で、多数本のリードを一つの接着剤に張り付ける必要は
無く、複数本（多くとも２、３本）のリードを張り付け
ることがかのうとなる。この為、半導体チップ上におけ
る接着剤の塗布面積を節約する事が出来るので、該面積
を他に有効に使用する事が出来る。また、更にリードと
半導体チップとの接着安定性を確保したい場合、接着剤
はインナーリード２０３の先端部分だけでなく捻り加工
した部分を除いた他の部分にも張り付けても良い。Further, conventionally, the adhesive 202 attached to the lower surface (tip portion) of the inner lead 203 is generally attached to each of a large number of leads.
Since the twisted lead improves the strength in the vertical direction, it is not necessary to attach a large number of leads to one adhesive, and it is possible to attach a plurality of leads (a few at most). Become. Therefore, it is possible to save the application area of the adhesive on the semiconductor chip, so that the area can be effectively used for other purposes. Further, in order to further secure the adhesive stability between the lead and the semiconductor chip, the adhesive may be attached not only to the tip portion of the inner lead 203 but also to other portions except the twisted portion.
【００１８】また、インナーリードのねじれ加工の際の
ねじれの角度は９０度のとき最も上下方向の強度が強い
が、物理的なひねりを加えるため金属疲労を引き起こす
事が考えられる。そのため、十分上下方向の強度が取れ
れば、ひねる角度は９０度でなくでなく、例えば８０
度、７０度、６０度等でも良い。When the inner lead is twisted at a twist angle of 90 degrees, the strength in the vertical direction is strongest, but it is considered that metal fatigue is caused by the physical twist. Therefore, if the strength in the vertical direction is sufficient, the twist angle is not 90 degrees, but 80 degrees, for example.
The degree may be 70 degrees, 60 degrees, or the like.
【００１９】また、インナーリード２０３の捻り加工を
施す部分にローラポンチ１１２を上下から押す事により
捻り加工する方法は、前述のアウターリードを曲げ加工
するのと同様な方法であるので、最も簡便で、かつ、現
状の組立技術を何等変更せず製造コストの増加を必要と
しない。A method of twisting the inner lead 203 by pushing the roller punch 112 from above and below to the portion to be twisted is the same as the method of bending the outer lead described above, and is the simplest method. In addition, there is no need to increase the manufacturing cost without changing the current assembly technology.
【００２０】本発明は、インナーリード２０３が捻り加
工されているので、インナーリード２０３の上下方向の
強度を増強する事が出来る。この為、従来樹脂封止工程
の際に起きていた注入樹脂の応力によるリードの変形を
抑制する事が出来る。また、インナーリード２０３が捻
り加工されているので、インナーリード２０３の幅が見
かけ上細くなる（Ｗ１＞Ｗ２、図２参照）ので、インナ
ーリード２０３の自己インダクタンス及び自己キャパシ
タンスを低減する事が出来る。その上、捻り加工により
隣接するインナーリードの間隔も広くなる（Ｘ＞Ｙ、図
２参照）ので、隣接するリード間の相互インダクタンス
及び相互キャパシタンスも低減する事ができ、高歩留ま
り、かつ、高性能な樹脂封止型半導体装置を提供する事
が出来る。In the present invention, since the inner lead 203 is twisted, the strength of the inner lead 203 in the vertical direction can be increased. Therefore, it is possible to suppress the deformation of the leads due to the stress of the injected resin, which has occurred in the conventional resin sealing step. Further, since the inner lead 203 is twisted, the width of the inner lead 203 is apparently narrowed (W1> W2, see FIG. 2), so that the self-inductance and the self-capacitance of the inner lead 203 can be reduced. In addition, the twisting process also widens the spacing between adjacent inner leads (X> Y, see FIG. 2), so mutual inductance and mutual capacitance between adjacent leads can also be reduced, resulting in high yield and high performance. It is possible to provide a simple resin-sealed semiconductor device.
【００２１】[0021]
【発明の効果】本発明は、以上の様に構成されているの
で、従来の組立技術の変更及び製造コストの増加を伴わ
ずに、インナーリードの上下方向の強度を増強する事が
でき、従来樹脂封止工程の際に起きていた注入樹脂の応
力によるリードの変形を抑制する事が出来る。また、イ
ンナーリードが捻り加工されているので、インナーリー
ドの幅が見かけ上細くなるので、インナーリードの自己
インダクタンス及び自己キャパシタンスを低減する事が
出来る。その上、捻り加工により隣接するインナーリー
ドの間隔も広くなるので、隣接するリード間の相互イン
ダクタンス及び相互キャパシタンスも低減する事がで
る。また、プロセスマージンも向上させる事で高歩留ま
り、かつ、高性能な樹脂封止型半導体装置を提供する事
が出来る。Since the present invention is constructed as described above, it is possible to increase the vertical strength of the inner lead without changing the conventional assembling technique and increasing the manufacturing cost. It is possible to suppress the deformation of the leads due to the stress of the injected resin that has occurred during the resin sealing step. Further, since the inner lead is twisted, the width of the inner lead is apparently narrowed, so that the self-inductance and the self-capacitance of the inner lead can be reduced. In addition, since the distance between the adjacent inner leads is widened by the twisting process, mutual inductance and mutual capacitance between the adjacent leads can be reduced. Further, by improving the process margin, it is possible to provide a high-yield and high-performance resin-sealed semiconductor device.
【図１】本発明の実施形態図。FIG. 1 is a diagram illustrating an embodiment of the present invention.
【図２】本発明の実施形態図。FIG. 2 is an embodiment diagram of the present invention.
【図３】従来の樹脂封止工程図。FIG. 3 is a conventional resin sealing process diagram.
【図４】従来の樹脂封止工程図。FIG. 4 is a conventional resin sealing process diagram.
【図５】従来の樹脂封止工程図。FIG. 5 is a conventional resin sealing process diagram.
【図６】従来の樹脂封止工程図。FIG. 6 is a conventional resin sealing process diagram.
３０１、６０１ 半導体チップ ２０２ 接着剤 １０３、２０３ インナーリード ２０４ 半導体チップ ２０５、３０５ パッド ２０６、３０６、６０６ ワイヤー ５０７ 樹脂 ５０８ アウターリード ３１０、５１０、６１０ リード １１２ ローラーポンチ ４１５、６１５ 型 ６２０ 応力 ４２５ 樹脂注入穴 301, 601 Semiconductor chip 202 Adhesive 103, 203 Inner lead 204 Semiconductor chip 205, 305 Pad 206, 306, 606 Wire 507 Resin 508 Outer lead 310, 510, 610 Lead 112 Roller punch 415, 615 type 620 Stress 425 Resin injection hole
Claims (2)
プと、前記半導体チップ上に形成され、前記半導体チッ
プ内の半導体素子と電気的に接続された電極として使用
するパッドと、ワイヤーにより前記半導体チップ上に形
成されたパッドと電気的に接続され、かつ、前記半導体
チップ上に接着材料により固定されたリードと、前記半
導体チップ表面と前記リードの一部が樹脂により封止さ
れている樹脂封止型半導体装置において、樹脂に封止さ
れている部分の先端を除いた部分のリードがひねり加工
されている事を特徴とする樹脂封止型半導体装置。1. A semiconductor chip having a semiconductor element formed thereon, a pad formed on the semiconductor chip and used as an electrode electrically connected to the semiconductor element in the semiconductor chip, and a wire for the semiconductor chip. A lead electrically connected to the pad formed above and fixed on the semiconductor chip with an adhesive material, and a resin encapsulation in which the surface of the semiconductor chip and a part of the lead are encapsulated with resin. A resin-encapsulated semiconductor device, characterized in that, in the semiconductor device, the leads of the portion other than the tip of the portion sealed with resin are twisted.
接着材料が複数本のリードを固定してる事を特徴とする
請求項１記載の樹脂封止型半導体装置。2. The resin-encapsulated semiconductor device according to claim 1, wherein an adhesive material attached to the twisted lead fixes a plurality of leads.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8067626A JPH09260569A (en) | 1996-03-25 | 1996-03-25 | Resin sealed semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8067626A JPH09260569A (en) | 1996-03-25 | 1996-03-25 | Resin sealed semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH09260569A true JPH09260569A (en) | 1997-10-03 |
Family
ID=13350389
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8067626A Pending JPH09260569A (en) | 1996-03-25 | 1996-03-25 | Resin sealed semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH09260569A (en) |
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-
1996
- 1996-03-25 JP JP8067626A patent/JPH09260569A/en active Pending
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