JPH09260426A - Mounting board, mounting method and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To maintain the high-speed and high-frequency characteristics of electronic parts to obtain their high-density mountings, in relation to mounting boards, mounting methods and semiconductor devices. SOLUTION: There is formed a circuit board 20 having on its one surface a recessed portion 21B with a single step-surface or a plurality of step-surfaces and having on the respective step-surfaces of the recessed portion 21B and/or on its one surface a single land or a plurality of lands 24 provided oppositely to the electrodes disposed on the circuit-surface of an electronic part mounted on it. Then, joining the electrodes of the electronic part to the opposite lands 24 thereto of the circuit board 20 via bumps 25, an insulation resin is filled subsequently into the gap between the respective step-surfaces of the recessed portion 21B of the circuit board 20 or its one surface and the circuit-surface of the electronic part of form hollow portions between the respective step-surfaces of the recessed portion 21B of the circuit board 20 and the predetermined regions of the respective opposite circuit-surfaces thereto of the electronic part and to seal the electronic part. As a result the designed values of both wiring patterns and the constants of the characteristic impedance of passive elements, etc., which are formed on the circuit-surface of the electronic part can be maintained.

Description

Detailed Description of the Invention

[0001]

[Table of Contents] The present invention will be described in the following order. TECHNICAL FIELD OF THE INVENTION Conventional Technology (FIG. 7) Problem to be Solved by the Invention (FIGS. 8 and 9) Means for Solving the Problem (FIGS. 1 to 6) Embodiment of the Invention (1) First Embodiment (FIG. 1) (2) Second embodiment (FIG. 2) (3) Other embodiment (FIGS. 3 to 6)

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mounting board, a mounting method, and a semiconductor device. For example, a mounting board in which a bare chip is mounted on one surface of a multilayer wiring board, a mounting method for the bare chip, and further, one surface of the multilayer wiring board. It is suitable for application to a semiconductor device in which a bare chip is mounted.

[0003]

2. Description of the Related Art In recent years, in information communication equipment, cellular telephones and integrated digital communication service networks (ISDN: Inte
With the progress of information communication (network) technology in grated Services Digital Network) and personal computers (PCs), circuit blocks such as high frequency communication circuits and high speed serial interface circuits are being mounted.

In this circuit block, miniaturization and compactness are desired by high-density mounting of semiconductor chips, and a mounting method considering high-speed operation and noise for the semiconductor chips is desired. Therefore, as a high-density mounting technology that realizes such demands,
Multi Chip Module (MCM: Multichip Module)
Attention is being paid to bare chip mounting such as flip chip mounting and flip chip mounting.

Usually, in flip-chip mounting using a bare chip, bumps made of solder or the like are formed on a plurality of electrodes (hereinafter referred to as pads) formed on the circuit surface of the bare chip, and then the bare chip is formed. The bumps of the bare chip are bonded to the corresponding lands provided on the one surface of the mother board by facing the circuit surface of the above and one surface of the main wiring board (hereinafter, referred to as a mother board) composed of the multilayer wiring board. The bare chip can be mounted on one surface of the motherboard.

In this case, in this flip chip mounting, as compared with the case where the bare chip is mounted on one surface of the motherboard by using a method such as wire bonding, a bonding portion (bump) for bonding each pad of the bare chip and the corresponding land of the motherboard. By shortening the length of (1), the inductance and capacitance in the bump can be reduced, and thus the high speed characteristics and high frequency characteristics of the bare chip can be improved.

The mother board on which the bare chip is mounted is usually a multilayer wiring board formed by sequentially laminating an organic substrate such as glass epoxy or glass polyimide and a predetermined wiring pattern, and a ceramic substrate such as alumina or mullite. There is used a multi-layer wiring substrate in which the wiring pattern of 1) is sequentially laminated, or a multi-layer wiring substrate in which a predetermined wiring pattern layer made of copper or the like and a polyimide layer are sequentially laminated on one surface of a silicon substrate.

Here, FIG. 7 shows an example of a mounting board in which a bare chip is mounted on one surface of a motherboard by flip chip mounting. In this mounting board 1, a plurality of pads 3 are provided on a predetermined pitch along the outermost periphery of the circuit surface 2A of the bare chip 2, and lands 5 provided on one surface 4A of the mother board 4 corresponding to these pads 3. Are bonded to each other via bumps 6 made of high melting point solder, so that the bare chip 2 is attached to one surface 4A of the mother board 4.
Is implemented.

In this case, first, in the bare chip 2, each pad 3 provided on the circuit surface 2A is made of, for example, aluminum, and on each pad 3, for example, titanium, platinum,
A BLM (Ball Limiting Metal) film layer 7 formed by sequentially laminating metal film layers made of gold
Are formed. Further, the bumps 6 are formed on the respective BLM film layers 7, and the BLM film layers 7 can prevent mutual diffusion of the bumps 6 into the pad 3.

On the other hand, in the mother board 4, ceramic board layers 8 and predetermined wiring pattern layers 9 made of copper or the like are alternately laminated, and each land 5 on one surface 4A of the mother board 4 is respectively formed. For example, a solder precoat layer 10 made of eutectic solder is laminated.

As a result, in the mounting substrate 1, the solder precoat layer 10 is reflowed at a temperature at which the high melting point solder does not melt and the eutectic solder melts during reflow, and the melted solder precoat layer 10
Are welded to each bump 6. In this case, motherboard 4
In the bare chip 2 mounted on the one surface 4A of the motherboard 4, the shape of each bump 6 is kept substantially the same as that before mounting, so that the height accuracy of the bare chip 2 with respect to the one surface 4A of the motherboard 4 can be maintained. ing.

By the way, when the bear chip 2 mounted on the one surface 4A of the mother board 4 is operated, the bear chip 2 generates heat. However, since the mother board 4 and the bare chip 2 have different thermal expansion coefficients, stress may be concentrated on the bumps 6 due to the difference in the thermal expansion coefficients, and the bumps 6 may be damaged. Therefore, in such a mounting board 1, usually, after the bare chip 2 is mounted on the one surface 4A of the mother board 4, a predetermined insulating property is provided in the gap between the one surface 4A of the mother board 4 and the circuit surface 2A of the bare chip 2. The resin 11 is filled, and the bare chip 2 is sealed thereby.

In this case, the insulating resin 11 is designed to embed the bumps 6, and alleviates the stress concentration generated in the bumps 6 due to the difference in the thermal expansion coefficient between the mother board 4 and the bare chip 2, and the bumps 6 concerned. The damage of 6 can be prevented, the circuit surface 2A of the bare chip 2 can be covered, and the circuit surface 2A can be protected from impurities and moisture contained in the outside air.

[0014]

By the way, as shown in FIG. 8, among various types of bare chips 2, particularly in a high frequency element or the like, gold, aluminum or copper is formed on a semiconductor substrate 15 made of a compound semiconductor such as silicon or gallium arsenide. And the like, and an insulating film layer 17 having a predetermined first relative permittivity are sequentially laminated, and a predetermined wiring pattern 18 made of gold, aluminum, copper or the like is formed on the insulating film layer 17. Is configured. In this case, in such a high-frequency element, the thickness h of the first insulating film layer 17, the thickness d of the wiring pattern 18, and the thickness d of the wiring pattern 18 in the state where the side facing the first insulating film layer 17 is exposed to the air. The wiring pattern 18 is designed in advance so as to have a predetermined characteristic impedance value based on the width w of the wiring pattern 18, and thus is designed to have a predetermined high speed characteristic and high frequency characteristic.

However, in the mounting board 1 described above,
By forming the insulating resin 11 having the second relative dielectric constant different from the relative dielectric constant of air on the circuit surface 2A of the bare chip 2, the capacitance of the wiring pattern 18 formed on the circuit surface 2A is increased. As a result, the characteristic impedance becomes a value different from the designed value, and there is a problem that the high speed characteristics and high frequency characteristics of the bare chip 2 are impaired.

Here, for example, when the resin layer 19 having a thickness of about 5, 10, 15, 20 [μm] is formed on the wiring pattern 18 of the bare chip 2, a change in impedance value of the wiring pattern 18 is formed. Is shown in FIG. First, the characteristic point group A shows how the impedance value changes when the width w of the wiring pattern 18 is set to about 10 [μm], and the characteristic point group B sets the width w of the wiring pattern 18 to about 20 [μm]. The change of the impedance value in the case is shown. Characteristic point group C shows how the impedance value changes when the width w of the wiring pattern 18 is set to about 40 [μm].

In this case, as is clear from FIG.
The wiring pattern 18 having a width w of about 0, 20 and 40 [μm] is 90 when exposed to the air.
While it is designed to have impedance values of about [Ω], 70 [Ω], and 50 [Ω], a resin layer 19 is formed on each of these wiring patterns 18, and the resin layer 19 As the thickness increases to about 5, 10, 15, 20 [μm], the impedance value of each wiring pattern 18 decreases. That is, this is because the circuit board 2A of the bare chip 2 is formed by sealing the bare chip 2 mounted on the one surface 4A of the mother board 4 with the insulating resin 11.
This means that the impedance value of the wiring pattern 18 formed on the wiring has a different value from the design value.

Therefore, in particular, MMIC (Monolithic Mic)
In a microstrip line or a coplanar line such as a rowave integrated circuit) or a predetermined high-speed digital IC, insulating resin 1 is used.
When the impedance value of each transmission line is covered with 1 and becomes a value different from the design value, there is a problem that impedance matching is impaired and gain characteristics are deteriorated. In addition to these, these MMICs and high-speed digital I
In C, the constant of a passive element such as a spiral inductor formed in advance on the circuit surface is changed, and
There is a problem that high-speed characteristics and high-frequency characteristics are deteriorated because stray capacitance is increased to cause dielectric loss and load characteristics are deteriorated.

Further, in the FET (Field Effect Transistor) formed on the circuit surface 2A of the bare chip 2, the noise characteristic depends on the gate capacitance. However, FET
When the insulating resin 11 is formed on the upper part of the above, the insulating resin 11 causes deterioration of the noise characteristic, and there is a problem that the gate capacitance is increased and the noise characteristic is changed.

In addition, as an electronic component mounted on the one surface 4A of the mother board 4, in a filter such as a surface acoustic wave (SAW) filter which obtains characteristics based on the vibration of surface acoustic waves, an insulating resin 11 is used.
As a result, the circuit surface is covered, so that it becomes difficult to obtain the vibration of the surface acoustic wave, and there is a problem that the characteristics are significantly changed. For this reason, when mounting such a filter on the mother board 4, for example, the filter is mounted in the recess provided in the multilayer wiring board including the ceramic board and a predetermined wiring pattern, and then the recess of the multilayer wiring board is mounted. A method is conceivable in which a semiconductor device is formed by sealing with a sealing cap made of metal or the like so as to close it, and the semiconductor device is mounted on one surface 4A of the motherboard 4. However, this method requires a sealing step of sealing the concave portion of the multilayer wiring board by using a sealing cap, which complicates the mounting step of the filter chip. Further, there is a problem that the cost of the mounting board 1 on which the filter chip is mounted increases.

The present invention has been made in consideration of the above points, and is intended to propose a mounting substrate, a mounting method, and a semiconductor device which can be mounted at high density while maintaining high-speed characteristics and high-frequency characteristics of electronic components. is there.

[0022]

In order to solve the above problems, the present invention has an electronic component having a circuit surface on which a single or a plurality of electrodes are provided, and a recess having a single or a plurality of step surfaces on one surface. , A wiring board on which one or more lands are provided on each step surface and / or one surface of the recess corresponding to each electrode of the electronic component, and each electrode of the electronic component is bonded to the corresponding land of the wiring substrate. The bumps, the step surfaces of the concave portion of the wiring board or one surface of the wiring board, and the gaps between the step surfaces or the circuit surfaces of the electronic components respectively corresponding to the bump surfaces, and the step surfaces of the concave portions of the wiring board. An insulating resin for sealing the electronic component is formed by forming a hollow portion between each of them and a predetermined area of the circuit surface of the electronic component facing each other.

Further, according to the present invention, an electronic component having a circuit surface on which a single or a plurality of electrodes are provided and a recess having a single or a plurality of step surfaces on one surface are provided on each step surface and / or one surface of the recess. A wiring board on which one or more lands are provided corresponding to each electrode of the electronic component, and each electrode of the electronic component is bonded to the corresponding land of the wiring substrate, and the electronic component and the wiring board are integrated. An anisotropic conductive film having a shape substantially the same as the circuit surface of the electronic component to be held and having an opening corresponding to a predetermined region of the circuit surface is provided.

Further, in the present invention, there is provided a concave portion having one or a plurality of step surfaces on one surface, and the concave portion corresponds to the electrode provided on each step surface and / or the circuit surface of the electronic component mounted on the one surface. A first step of forming a wiring board provided with a single or a plurality of lands, and a second step of joining electrodes of an electronic component and corresponding lands of the wiring board via bumps; By filling an insulating resin in a gap between each step surface of the concave portion or one surface of the wiring board and each step surface or one surface of the circuit surface of the corresponding electronic component, each step surface of the concave portion of the wiring board is respectively filled. A third step of forming a hollow portion between the opposing electronic component and a predetermined region of the circuit surface to seal the electronic component is provided.

Further, in the present invention, there is provided a concave portion having one or a plurality of step surfaces on one surface, and it corresponds to an electrode provided on each step surface of the concave portion and / or a circuit surface of an electronic component mounted on the one surface. The first step of forming a wiring board provided with a single or a plurality of lands, and the electrode of the electronic component and the corresponding land of the wiring board have substantially the same shape as the circuit surface of the electronic component, and And a second step of joining together through an anisotropic conductive film having an opening corresponding to a predetermined region of the circuit surface and holding the electronic component and the wiring board together through the anisotropic conductive film. To

A recess having a single or a plurality of step surfaces is provided on one surface, and a single or a plurality of electrodes are provided corresponding to each step surface of the recess and / or an electrode provided on a circuit surface of an electronic component mounted on the one surface. A wiring board provided with lands is formed, and then the electrodes of the electronic component and the corresponding lands of the wiring board are joined via bumps, and then each step surface of the concave portion of the wiring board or one surface of the wiring board and each By filling an insulating resin in the gap between the step surface or one surface and the circuit surface of the corresponding electronic component, between the step surface of the concave portion of the wiring board and a predetermined area of the circuit surface of the electronic component facing each other. By forming the hollow portion in the to seal the electronic component, it is possible to shield the wiring pattern and the passive element formed on the circuit surface of the electronic component from the outside air and expose the hollow portion in the hollow portion. Of electronic components The constant characteristic impedance, etc. of the wiring pattern and the passive elements of the road surface can be maintained at the design value.

A recess having a single or a plurality of step surfaces is provided on one surface, and a single or a plurality of electrodes are provided corresponding to each step surface of the recess and / or an electrode provided on a circuit surface of an electronic component mounted on the one surface. A wiring board provided with lands is formed, and then the electrodes of the electronic component and the corresponding lands of the wiring board are made to have an almost same shape as the circuit surface of the electronic component, and an opening corresponding to a predetermined area of the circuit surface is formed. The wiring pattern formed on the circuit surface of the electronic component and the electronic component and the wiring board are integrally held together through the anisotropic conductive film that the electronic component and the wiring board have. Since the passive element can be almost certainly shielded from the outside air and exposed in the hollow portion, constants such as the wiring pattern on the circuit surface of the electronic component and the characteristic impedance of the passive element are maintained at the designed values. Door can be.

[0028]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings.

(1) First Embodiment In FIG. 1, reference numeral 20 denotes a mounting substrate according to the first embodiment as a whole, and a bare chip is formed on the one surface 21A of a mother board 21 having a recess 21B on one surface 21A so as to close the recess 21B. A plurality of pads 23 are provided along the outermost periphery of the circuit surface 22A of the bare chip 22 and lands 24 provided corresponding to the one surface 21A of the mother board 21 through bumps 25 made of high melting point solder. Has been implemented. In addition, in the gap between the circuit surface 22A of the bare chip 22 and the one surface 21A of the motherboard 21, a hollow portion 2 is provided between the concave portion 21B of the motherboard 21 and a predetermined area of the circuit surface 22A of the bare chip 22 that faces the concave portion 21B.
6 and is filled with an insulating resin 27 so as to embed each bump 25, whereby the bare chip 22 is sealed.

In this case, in the mother board 21, the ceramic substrate layers 30 and the predetermined wiring pattern layers 31 are alternately laminated, and the lands 24 provided on the one surface 21A are each made of eutectic solder. The precoat layer 32 is formed. The bumps 25 are welded and joined to the solder precoat layer 32.

Here, in each bump 25, one surface 21A of the mother board 21 and the circuit surface 22A of the bare chip 22.
Distance (ie, one side 21 of the motherboard 21)
The shape and size are selected in advance so that the height of the bare chip 22 with respect to A is a predetermined design value, and the solder pre-coating of the motherboard 21 is performed with the bumps 25 having the shape and size selected in advance. Bonded to layer 32. As a result, the reliability of the height of the bare chip 22 with respect to the one surface 21A of the motherboard 21 can be ensured.

In the bare chip 22, the circuit surface 2
Each pad 23 of 2A is made of aluminum, for example, and a BLM film layer 33 is formed on each pad 23. Bumps 25 are formed on the respective BLM film layers 33, and the BLM film layers 33 are formed by pads (aluminum) 23 of the bumps 25 (high melting point solder).
It is designed to prevent mutual diffusion to the.

Further, in this bare chip 22, a predetermined area of the circuit surface 22A which is in contact with the hollow portion 26 is shielded from the outside air around the mounting substrate 20 by the insulating resin 27,
A predetermined area of the circuit surface 22A is protected from impurities and moisture contained in the outside air. In addition to this, in the bare chip 22, the wiring pattern and passive elements (not shown) formed in a predetermined area of the circuit surface 22A are exposed in the hollow portion 26, and constants such as characteristic impedance of these wiring patterns and passive elements are designed. It is designed so that the value can be maintained.

Here, in practice, in this mounting board 20, one surface 2 of the mother board 21 is processed by the following procedure.
The bare chip 22 can be mounted on 1A. That is, first, metal coating layers made of, for example, titanium, platinum, and gold are sequentially laminated on each pad 23 of the circuit surface 22A of the bare chip 22 by a method such as a plating method and a vapor deposition method to form these metal coating layers. The BLM film layer 33 is laminated.

Next, a photoresist film is laminated on the circuit surface 22A of the bare chip 22, the photoresist film is exposed in accordance with each BLM film layer 33, and then developed to expose each BLM film layer 33. Next, a bump material made of tin and lead forming a high melting point solder is laminated on the photoresist film by a method such as a plating method or a vapor deposition method, and then the photoresist film is peeled from the circuit surface 22A of the bare chip 22. As a result, a bump material is laminated on each BLM film layer 33. Next, a flux is applied to the bump material on each BLM film layer 33, and then each of these bump materials is reflowed and melted at a predetermined temperature to thereby form a bump 25 made of a high melting point solder on each BLM film layer 33. To form.

Subsequently, the ceramic substrate layer 30 and the wiring pattern layer 31 are alternately laminated to form a concave portion 21B at a predetermined position of the uppermost ceramic substrate layer 30, and one surface of the uppermost ceramic substrate layer 30 is formed. Recess 2
A land 24 is formed in the peripheral portion of the opening 21C of 1B so as to correspond to each pad 23 of the bare chip 22 to form the mother board 21. Thereafter, a metal mask having openings formed on the one surface 21A of the mother board 21 corresponding to the respective lands 24 is mounted.

Next, a eutectic solder having a predetermined viscosity is dropped on the metal mask by a printing method, and a squeegee is moved on the upper surface of the metal mask to form the eutectic solder on each land 24 through each opening. To print. Subsequently, the metal mask is removed from the one surface 21A of the mother board 21, and then the eutectic solder on each land 24 is reflowed at a predetermined temperature to form a solder precoat layer 32 on each land 24.

Next, a flux is applied to one surface 21A of the mother board 21 so as to cover each land 24. Then, using a predetermined mounting device, one surface 21A of the motherboard 21
And the circuit surface 22A of the bare chip 22 are opposed to each other, and then the bumps 25 formed on the pads 23 of the bare chip 22 are connected to the corresponding lands 24 of the motherboard 21, respectively.
And position it.

Then, using a predetermined heating device, the mother board 21 and the bare chip 22 are connected to each other with high melting point solder (bump 2
5) does not melt, and reflows at a predetermined temperature at which the eutectic solder (solder precoat layer 32) melts, thereby melting each solder precoat layer 32 to the corresponding bump 25. As a result, the bare chip 22
The pads 23 and the corresponding lands 24 of the mother board 21 are physically and electrically joined via the bumps 25. After this, a predetermined cleaning liquid is used to remove the motherboard 2
The extra flax adhering to the one surface 21A of 1 and the circuit surface 22A of the bare chip 22 is cleaned.

Subsequently, the gap between the circuit surface 22A of the bare chip 22 and the one surface 21A of the mother board 21 is filled with an insulating resin 27 having a predetermined viscosity. In this case, the insulating resin 27 is not filled into the concave portion 21B from the opening 21C of the concave portion 21B of the mother board 21 due to the capillary phenomenon, and the bumps 25 are embedded so that the bumps 25 are embedded.
It is filled only in the peripheral area. After that, the insulating resin 27 in the gap between the circuit surface 22A of the bare chip 22 and the one surface 21A of the mother board 21 is heated and cured. As a result, the predetermined area of the circuit surface 22A of the bare chip 22 is formed in the hollow portion 26.
Exposed by the insulating resin 27 and exposed to the bare chip 2
The bare chip 22 can be mounted on the one surface 21 </ b> A of the mother board 21 in a state where 2 is sealed.

In the above structure, the bare chip 22 is first
A BLM film layer 33 is laminated on each pad 23 of the circuit surface 22A, and then a bump 25 is formed on each BLM film layer 33. Next, the mother board 21 having the concave portion 21B on the one surface 21A is formed, and the solder precoat layer 32 is laminated and formed on each land 24 formed on the one surface 21A of the mother board 21. Subsequently, a flux is applied to the one surface 21A of the mother board 21, and then the bumps 25 on the pads 23 of the bare chip 22 are brought into contact with the corresponding lands 24 of the mother board 21 to be positioned.

Next, the solder precoat layers 32 of the mother board 21 are reflowed and welded to the corresponding bumps 25, whereby the pads 23 of the bare chip 22 and the corresponding lands 24 of the mother board 21 are bumped.
Join through 5. After this, one side 2 of the motherboard 21
1A and the circuit surface 22A of the bare chip 22 are washed to wash excess flux. Subsequently, the insulating resin 27 is filled in the gap between the one surface 21A of the mother board 21 and the circuit surface 22A of the bare chip 22.
Is cured to seal the bare chip 22. Thereby, the bare chip 22 can be mounted on the one surface 21A of the motherboard 21.

Therefore, in this mounting method, the recess 2 is formed.
After mounting the bare chip 22 on the one surface 21A of the mother board 21 on which 1B is formed so as to close the concave portion 21B,
The circuit surface 22A of these bare chips 22 and the motherboard 2
The gap between the first surface 21A and the first surface 21A is filled with the insulating resin 27 to form the hollow portion 26 between the concave portion 21B of the mother board 21 and the predetermined area of the circuit surface 22A of the bare chip 22. Since the predetermined area of the circuit surface 22A of 22 can be exposed to the hollow portion 26 in a state of being shielded from the outside air, the wiring pattern and the passive element formed in the predetermined area of the circuit surface 22A of the bare chip 22 can be exposed to the air. The exposed state can be the same as in the case of designing, and thus the constants such as the wiring pattern and the characteristic impedance of the passive element can be maintained at the designed values.

In this case, in the mounting board 20 in which the bare chip 22 is mounted on the one surface 21A of the mother board 21 by such a mounting method, the recess 2 of the mother board 21 is formed.
1B so as to have a hollow portion 26 between a predetermined area of the circuit surface 22A of the bear chip 22 facing the 1B.
Since the bare chip 22 is sealed by the insulating resin 27 filled in the gap between the second circuit surface 22A and the one surface 21A of the motherboard 21, a predetermined area of the circuit surface 22A of the bare chip 22 is formed. Hollow part 2 with the formed wiring pattern and passive elements shielded from the outside air
Since it can be exposed at 6, the design values of constants such as the characteristic impedance of these wiring patterns and passive elements can be maintained. In addition to this, by protecting a predetermined area of the circuit surface 22A of the bare chip 22 from impurities and moisture contained in the outside air, the bare chip 22 is formed.
Can be significantly improved.

Further, in the mounting board 20, when the bumps 25 are filled with the insulating resin 27 so as to seal the bare chips 22, the mounted bare chips 22 are operated to generate heat. Since the stress concentration generated in each bump 25 due to the difference in thermal expansion coefficient between the mother board 21 and the bare chip 22 can be relieved, the damage of each bump 25 can be prevented, and thus the life of the bare chip 22 can be greatly extended. Can be improved.

According to the above construction, the bare chip 22 is mounted on the one surface 21A of the mother board 21 so as to close the concave portion 21B, and thereafter, the insulating is provided in the gap between the one surface 21A of the mother board 21 and the circuit surface 22A of the bare chip 22. By filling the conductive resin 27 to seal the bare chip 22, the wiring pattern and the passive element formed in the predetermined region of the circuit surface 22A of the bare chip 22 can be exposed in the hollow portion 26. A mounting board and a mounting method capable of maintaining constants such as the characteristic impedances of the wiring pattern and the passive element of the circuit surface 22A as designed values and thus maintaining high-speed characteristics and high-frequency characteristics of the electronic component for high-density mounting Can be realized.

(2) Second Embodiment In FIG. 2, reference numeral 40 denotes a semiconductor device according to the second embodiment as a whole, which has a first recess 41B on one surface 41A and a plurality of bottom surfaces 41C of the first recess 41B. Second
Multilayer wiring board 41 having concave portions 41D (for example, two)
Pad 43 in which a plurality of bare chips 42 are provided on the circuit surface 42A of the bare chip 42 on the bottom surface 41C of the first concave part 41B so as to close each of the second concave parts 41D.
And the lands 44 provided respectively corresponding to the bottom surface 41C of the multilayer wiring board 41 with the bumps 4 made of high melting point solder.
It is mounted by joining via 5.

In the semiconductor device 40, the second recesses 41D are formed in the gaps between the second recesses 41D and the corresponding circuit surfaces 42A of the bare chip 42.
The first hollow portion 46 and the predetermined portion of the circuit surface 42A of the bare chip 42 facing each other.
Of the insulating resin 47 to seal each of the bare chips 42, and further to fill each of the bare chips 42 with the second insulating resin 48 in the first recess 41B of the multilayer wiring board 41. There is.

In this case, in the bare chip 42, the wiring pattern and passive elements (not shown) formed in a predetermined area of the circuit surface 42A are exposed in the hollow portion 46, so that the characteristic impedance of these wiring patterns and passive elements, etc. It is designed to maintain the constant design value. Further, in the bare chips 42, each of the bare chips 42 can be mechanically and electrically protected by overcoding with the second insulating resin 48.

In the multilayer wiring board 41, the ceramic substrate layers 50 and the predetermined wiring pattern layers 51 are alternately laminated, and the corresponding wiring patterns between the wiring pattern layers 51 are bonded to each other via the vias 52. Has been done. A plurality of external connection electrodes 53 are provided along the outermost circumference on the other surface 41E of the multilayer wiring board 41, and the lands 44 corresponding to the external connection electrodes 53 are provided.
And the wiring pattern of each wiring pattern layer 51 and the via 53.
Are electrically connected to each other.

Further, the first recess 41 of the multilayer wiring board 41 is provided.
A solder precoat layer 54 made of eutectic solder is formed on each land 44 provided on the bottom surface 41C of B. The bump 4 is formed on each solder precoat layer 54.
5 are welded and joined. In the bare chip 42, the BLM film layers 55 are formed on the pads 43 made of aluminum on the circuit surface 42A, and the bumps 45 are bonded to the BLM film layers 55.

As a result, in the semiconductor device 40, the external connection electrodes 53 of the multilayer wiring board 41 can be bonded to the corresponding lands of the motherboard (not shown) and mounted on the motherboard, and in this state, the semiconductor device 40 can be mounted. Each of the bare chips 42 mounted on is capable of inputting a signal from the mother board or outputting a signal via the external connection electrode 53 and the wiring pattern layer 51.

With the above structure, the semiconductor device 40
In the above, since the wiring pattern and the passive element formed on the circuit surface 42A of the bare chip 42 are exposed in the hollow portion 46, the wiring pattern and the passive element are designed on the assumption that they are exposed to the air. It is possible to maintain constants such as the designed wiring pattern and the characteristic impedance of the passive element as designed values.

According to the above structure, the bare chip 4 is formed so as to close each second recess 41D of the multilayer wiring board 41.
2 is mounted, and the bottom surface 41 of the multilayer wiring board 41 is mounted.
In the gap between C and the circuit surface 42A of the bare chip 42, the circuit surface 4 of the bare chip 42 facing each second recess 41D.
First to have a hollow portion 46 between the predetermined area of 2A
Since the wiring pattern and the passive element formed in the predetermined area of the circuit surface 42A of each bare chip 42 can be exposed in the hollow portion 46 by filling the insulating resin 47 of FIG. It is possible to maintain constants such as the characteristic impedance of the wiring pattern and the passive element as designed values, and thus it is possible to realize a semiconductor device capable of high-density mounting while maintaining high-speed characteristics and high-frequency characteristics of electronic components.

(3) Other Embodiments In the above-described first embodiment, the insulating resin 27 filled in the gap between the circuit surface 22A of the bare chip 22 and the one surface 21A of the motherboard 21 is used for the bare chip. Although the case where 22 is sealed has been described, the present invention is not limited to this, and as shown in FIG. 3 in which parts corresponding to those in FIG. After the bare chip 22 is sealed with the resin 27, various resin materials 61 such as epoxy resin are dropped on the back surface 22B side of the bare chip 22 by using a dispenser or the like, and the bare chip 22 is overcoated by heat curing. It may be done. Thereby, the bare chip 22 can be protected mechanically and electrically.

Further, in the above-described first and second embodiments, the circuit surfaces 21A and 41A of the bare chips 22 and 42 are used.
And one surface 21A of the motherboard 21 and the multilayer wiring board 41
The case in which the insulating resin 27 and the first insulating resin 47 are filled in the gap between the bottom surface 41C of the above is described, but the present invention is not limited to this, and the one surface 21A of the motherboard 21 and the multilayer wiring board. Each land 2 on the bottom surface 41C of 41
Anisotropic conductive film (ACF: Anisotropic Co) on 4 and 44
Numerous other conductive members such as nductive film) and conductive paste are laminated, and bumps 25 and 45 made of high melting point solder are used instead of bumps made of other conductive metal such as gold. Therefore, the pads 23 and 43 of the bare chips 22 and 42 and the corresponding lands 24 and 44 of the mother board 21 and the multilayer wiring board 41 may be bonded to each other through the conductive members and the bumps.

Here, for example, in FIG. 4 in which parts corresponding to those in FIG. 1 are designated by the same reference numerals, the bare chip 22 is mounted on the one surface 21A of the motherboard 21 by using the bumps 65 made of gold and the anisotropic conductive film 66. The mounted mounting board 67 is shown. That is, on each pad 23 provided on the circuit surface 22A of the bare chip 22, titanium nitride (TiN) capable of preventing mutual diffusion of the pad 23 (aluminum) and gold, respectively.
Barrier Metal consisting of a metal film layer such as
) Layer 68 is laminated, and bumps 65 are formed on the barrier metal layer 68.

An anisotropic conductive film 66 having the same shape as the circuit surface 22A of the bare chip 22 and having an opening corresponding to the recess 21B is laminated on the one surface 21A of the mother board 21 so as to cover each land 24. . Thereafter, the bumps 65 and the anisotropic conductive film 66 are heated and pressure-bonded to each other, and the bare chip 22 and the mother board 21 are held integrally, so that the bare chip 22 can be mounted on the one surface 21A of the mother board 21. Also in this case, the same effects as those of the first and second embodiments can be obtained.

In the mounting board 67 described above, when the bare chip 22 is mounted on the one surface 21A of the motherboard 21, a step of punching the anisotropic conductive film 66 in accordance with the recess 21B of the motherboard 21 to form an opening is required. Becomes However, by using the anisotropic conductive film 66, the bare chip 22 can be mounted without requiring an active material such as a flux, and the step of applying the flux and the step of cleaning the flux can be omitted.
In addition to this, a step of filling the gap between the circuit surface 22A of the bare chip 22 and the one surface 21A of the mother board 21 with the insulating resin 27 and a step of heating and hardening the insulating resin 27 can be omitted. Thus, in this case, the process can be greatly simplified as compared with the mounting method of the first embodiment.

Further, in the above-described first and second embodiments, one surface 21A of the mother board 21 and the multilayer wiring board 4 are
The case where the bare chips 22 and 42 are mounted on the bottom surface 41C of the first embodiment has been described, but the present invention is not limited to this, and the one surface 21A of the motherboard 21 and the multilayer wiring board 4 are described.
A concave portion having a plurality of step surfaces corresponding to the shapes and sizes of the plurality of types of the bare chips 22 and 42 is provided on the bottom surface 41C of the one, and the step surfaces, the one surface 21A, and the one surface 21A and The bare chips 22 and 42 may be mounted on the bottom surface 41C, respectively. As a result, the number of bare chips 22 and 42 that can be mounted on a predetermined area of the mother board 21 and the multilayer wiring board 41 can be increased, and thus, a mounting board that can maintain high-speed characteristics and high-frequency characteristics of electronic components and can be mounted at a higher density The mounting method and the semiconductor device can be realized.

Here, for example, as shown in FIG. 5, in the mounting substrate 70, the mother board 71 has a plurality of step surfaces 71.
It has a recess 71C having A and 71B, and this recess 71
In C, the step surface 71A and the one surface 7 of the motherboard 71
Spatial region 7 having a rectangular parallelepiped shape separated by 1D
The shape and size of No. 2 are selected according to the shape and size of the bare chip 73 to be mounted. Also, this recess 71
In C, the step surface 71B serving as the bottom surface is selected to have a shape and size slightly smaller than the circuit surface 73A of the bare chip 73. Further, a plurality of lands 75 are provided on the step surface 71A corresponding to a plurality of pads 74 provided on the circuit surface 73A of the bare chip 73, and a solder precoat layer 76 made of eutectic solder is laminated on each of the lands 75. Has been formed. A BLM film layer 77 is laminated on each pad 74 on the circuit surface 73A of the bare chip 73,
Bumps 7 made of high melting point solder are formed on the BLM film layer 77.
8 are formed.

As a result, in this mounting substrate 70,
The pads 74 of the bare chip 73 and the corresponding lands 75 on the step surface 71A are joined via the bumps 78 so that the bare chip 73 is dropped into the recess 71C of the motherboard 71, and the step surface of the recess 71C of the motherboard 71 is joined. 71B and circuit surface 73 of the bare chip 73
The concave portion 71C so as to have a hollow portion 79 between the concave portion 71C and
The bare chip 73 is sealed by filling it with the insulating resin 80. Thus, in this mounting board 70, the thickness of the mother board 71 can be made relatively thin, so that the bare chips 73 can be mounted at a higher density than the mounting board 20 of the first embodiment.

Further, in the above-mentioned first and second embodiments, the case where the ceramic substrate layers 30 and 50 are used as the insulating substrate layers constituting the mother board 21 and the multilayer wiring substrate 41 has been described. The present invention is not limited to this, and various other insulating substrate layers used for general multi-layer wiring substrates such as a glass epoxy substrate may be used.

Further, in the above-mentioned first and second embodiments, the case where the bare chips 22 and 42 are mounted as the electronic components mounted on the mother board 21 and the multilayer wiring board 41 has been described. Not limited to this, various other electronic components such as a filter chip may be mounted. In this case, in the mounting substrate 20 and the semiconductor device 40, since the circuit surface of the filter chip can be exposed in the hollow portion, it can be easily mounted without changing the characteristics of the filter chip.

Here, in a semiconductor device in which, for example, a filter chip is mounted on the bottom surface 41C of the multilayer wiring board 41, the circuit surface of the filter chip can be exposed to the hollow portion 46 in a state of being shielded from the outside air, so that the conventional filter chip can be exposed. Does not require a sealing cap that is considered to be required for the semiconductor device to be mounted, which simplifies the mounting process without the need for a sealing process to seal the concave portion of the multilayer wiring board using the sealing cap. You can implement a filter chip. Thus, the cost of the mounting board on which the filter chip is mounted can be reduced.

Further, in the above-mentioned second embodiment, the present invention has a first recess 41B on one surface 41A and a plurality of second recesses 41 on the bottom surface 41C of the first recess 41B.
Semiconductor device 4 in which bare chip 42 is mounted on bottom surface 41C of first recess 41B of multilayer wiring board 41 having D
However, the present invention is not limited to this and may be applied to semiconductor devices having various other package structures.

A semiconductor device 85 applied to a ball grid array (BGA) will now be described with reference to FIG. 6, for example. That is, the one surface 86 of the multilayer wiring board 86 having the plurality of concave portions 86B on the one surface 86A.
In A, the bare chip 8 is formed so as to cover each recess 86B.
A plurality of pads 88 are provided on the circuit surface 87A of the bare chip 87 and one surface 86A of the multilayer wiring board 86.
The land 89 provided corresponding to the above is bonded and mounted via, for example, a barrier metal layer 90, a bump 91 made of a conductive metal such as gold, and an anisotropic conductive film 92.

In this case, the anisotropic conductive film 92 has substantially the same shape as the circuit surface 87A of the bare chip 87 and has an opening corresponding to the concave portion 86B of the multilayer wiring board 86, and is formed on the one surface 86A of the multilayer wiring board 86. It is laminated so as to cover each land 89. As a result, the circuit surface 87 of the bare chip 87 facing the respective concave portions 86B of the multilayer wiring board 86 is formed.
A hollow portion 9 which is shielded from the outside air is provided between the predetermined area A and the predetermined area A.
3 are formed so that constant design values such as the characteristic impedance of the wiring pattern and passive elements (not shown) formed on the circuit surface 87A of each bear 87 can be maintained.

On the other surface 86C of the multilayer wiring board 86, a plurality of external connection electrodes (not shown) are provided in a grid pattern, and ball electrodes 94 are provided on each of these external connection electrodes. Further, in the multilayer wiring board 86, for example, the ceramic substrate layers 95 and the predetermined wiring pattern layers 96 are alternately laminated and formed, and the corresponding wiring patterns between the wiring pattern layers 96 and the external portions corresponding to the wiring patterns are formed. Connection electrode and land 89
And are electrically connected via the via 97.

As a result, in the semiconductor device 85, each ball electrode 94 of the multilayer wiring board 86 can be bonded to the corresponding land of the motherboard (not shown) and mounted on the motherboard, and in this state, mounted on the semiconductor device 85. Each of the formed bear chips 87 can input or output a signal from the mother board via the ball electrode 94 and the wiring pattern layer 96. Thus, also in this case, the same effect as that of the second embodiment can be obtained.

[0071]

As described above, according to the present invention, a recess having a single or a plurality of step surfaces is formed on one surface, and the step surface of the recess and / or the circuit surface of the electronic component mounted on the one surface are mounted. A wiring board provided with a single or a plurality of lands corresponding to the provided electrodes is formed, and then the electrodes of the electronic component and the corresponding lands of the wiring board are bonded via bumps, and subsequently, the recesses of the wiring board are formed. Each step surface or one surface of the wiring board,
By filling the gap between each step surface or one surface and the circuit surface of the corresponding electronic component with an insulating resin, the step surface of the concave portion of the wiring board and a predetermined area of the circuit surface of the electronic component facing each other are formed. By forming a hollow portion between and sealing the electronic component, it is possible to shield the wiring pattern and the passive element formed on the circuit surface of the electronic component from the outside air and expose the hollow portion in the hollow portion. It is possible to maintain constants such as the characteristic impedance of these wiring patterns and passive elements on the circuit surface of the electronic component as designed values, thus enabling high-density mounting while maintaining high-speed characteristics and high-frequency characteristics of the electronic component. The mounting method and the semiconductor device can be realized.

As described above, according to the present invention, the concave portion having one or a plurality of step surfaces is formed on one surface, and the concave portion is provided on each step surface of the concave portion and / or on the circuit surface of the electronic component mounted on the one surface. A wiring board provided with a single or a plurality of lands corresponding to the formed electrodes, and then the electrodes of the electronic component and the corresponding lands of the wiring substrate have substantially the same shape as the circuit surface of the electronic component, and The electronic component and the wiring board are integrally held together through the anisotropic conductive film having an opening corresponding to a predetermined region of the circuit surface, and the electronic component and the wiring board are integrally held by the anisotropic conductive film. Since the wiring pattern and passive elements formed on the circuit surface of the component can be exposed to the air by being shielded from the outside air, constants such as the characteristic impedance of the wiring pattern and the passive element on the circuit surface of the electronic component can be exposed. It can be maintained at the design value,
Thus, it is possible to realize a mounting substrate, a mounting method, and a semiconductor device that can be mounted at high density while maintaining high-speed characteristics and high-frequency characteristics of electronic components.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view showing a configuration of a mounting board according to a first embodiment of the present invention.

FIG. 2 is a schematic cross-sectional view showing the overall structure of a semiconductor device according to a second embodiment of the present invention.

FIG. 3 is a schematic cross-sectional view showing a structure of a mounting substrate on which a bare chip is overcoated according to another embodiment.

FIG. 4 is a schematic cross-sectional view showing the structure of a mounting board using an anisotropic conductive film according to another embodiment.

FIG. 5 is a schematic cross-sectional view showing a configuration of a mounting board mounted so that a bare chip is embedded in a concave portion of a motherboard according to another embodiment.

FIG. 6 is a schematic cross-sectional view showing the overall configuration of a semiconductor device according to another embodiment.

FIG. 7 is a schematic cross-sectional view showing a configuration of a conventional mounting board.

FIG. 8 is a schematic cross-sectional view showing a configuration example of a wiring pattern of a bare chip.

FIG. 9 is a graph showing how the impedance value of the wiring pattern changes when a resin layer is formed on the wiring pattern formed on the circuit surface of the bare chip.

[Explanation of symbols]

1, 20, 60, 67, 70 ... Mounting board, 2, 22,
42, 73, 87 ... Bear chips, 3, 23, 43, 7
4,88 ... Pad, 4,21,41,71 ... Motherboard, 5,24,44,79 ... Land, 6,25,
45, 65, 78, 91 ... Bumps, 11, 27 ... Insulating resin, 26, 46, 79, 93 ... Hollow part, 40,
85: Semiconductor device, 47: First insulating resin, 48
...... Second insulating resin, 61 ...... Resin material, 66, 92 ...
... anisotropic conductive film, 21B, 71C, 86B ...
1B ... 1st recessed part, 41D ... 2nd recessed part.

Claims (12)

[Claims] 1. An electronic component having a circuit surface on which a single or a plurality of electrodes are provided, and a concave portion having a single or a plurality of step surfaces on one surface, and on each of the step surfaces and / or on the one surface of the concave portion. A wiring board provided with a single or a plurality of lands corresponding to the respective electrodes of the electronic component, a bump for bonding the respective electrodes of the electronic component to the corresponding lands of the wiring board, and the wiring board Filled in a gap between each of the step surfaces of the recess or the one surface of the wiring board and each of the step surfaces or the circuit surface of the electronic component corresponding to the one surface, respectively, and the recess of the wiring board. A mounting board, which comprises an insulating resin which forms a hollow portion between each of the step surfaces and a predetermined region of the circuit surface of the electronic component, which faces each other, and seals the electronic component. . 2. The mounting board according to claim 1, further comprising an insulating resin that covers a surface side of the electronic component facing the circuit surface. 3. An electronic component having a circuit surface provided with a single or a plurality of electrodes, and a recess having one or a plurality of step surfaces on one surface thereof, and on each of the step surfaces and / or on the one surface of the recess. A wiring board provided with a single or a plurality of lands corresponding to each of the electrodes of the electronic component, and each of the electrodes of the electronic component are bonded to the corresponding land of the wiring substrate, and the electronic component and An anisotropic conductive film that holds the wiring board integrally and has substantially the same shape as the circuit surface of the electronic component and has an opening corresponding to a predetermined region of the circuit surface. Mounting board. 4. The mounting board according to claim 3, further comprising an insulating resin covering a surface side of the electronic component facing the circuit surface. 5. A concave portion having one or a plurality of step surfaces on one surface thereof, and corresponding to electrodes provided on each of the step surfaces of the concave portion and / or a circuit surface of an electronic component mounted on the one surface. A first step of forming a wiring board provided with a single or a plurality of lands; a second step of joining the electrodes of the electronic component and the corresponding lands of the wiring board via bumps; An insulating resin is filled in a gap between each of the step surfaces of the concave portion of the wiring board or the one surface of the wiring board and the circuit surface of the electronic component corresponding to each of the step surfaces or the one surface. A third step of sealing the electronic component by forming a hollow between the stepped surface of the recess of the wiring board and a predetermined region of the circuit surface of the electronic component that faces each other. Fruit characterized by having Method. 6. The method according to claim 4, further comprising a fourth step of dropping an insulating resin from the surface of the electronic component facing the circuit surface to cover the electronic component with the insulating resin. The mounting method according to Item 5. 7. A recess having a single or a plurality of step surfaces on one surface thereof, and corresponding to electrodes provided on each of the step surfaces of the recess and / or on a circuit surface of an electronic component mounted on the one surface. The first step of forming a wiring board provided with a single or a plurality of lands, the electrodes of the electronic component, and the corresponding lands of the wiring board have substantially the same shape as the circuit surface of the electronic component. And joining via an anisotropic conductive film having an opening corresponding to a predetermined region of the circuit surface, and holding the electronic component and the wiring board integrally via the anisotropic conductive film. 2. A mounting method comprising the step 2). 8. A third step of coating an insulating resin on the electronic component by dropping an insulating resin from the surface of the electronic component facing the circuit surface. The mounting method according to Item 7. 9. An electronic component having a circuit surface provided with one or a plurality of electrodes, and a recess having one or a plurality of step surfaces on one surface, and on each of the step surfaces and / or on the one surface of the recess. A wiring board provided with a single or a plurality of lands corresponding to the respective electrodes of the electronic component, a bump for bonding the respective electrodes of the electronic component to the corresponding lands of the wiring board, and the wiring board Filled in a gap between each of the step surfaces of the recess or the one surface of the wiring board and each of the step surfaces or the circuit surface of the electronic component corresponding to the one surface, respectively, and the recess of the wiring board. A semiconductor device, comprising: an insulating resin that seals the electronic component by forming a hollow portion between each of the step surfaces and a predetermined region of the circuit surface of the electronic component that faces each other. . 10. The semiconductor device according to claim 9, further comprising an insulating resin that covers a surface side of the electronic component facing the circuit surface. 11. An electronic component having a circuit surface on which a single or a plurality of electrodes are provided, and a recess having one or a plurality of step surfaces on one surface, and on each of the step surfaces of the recess and / or on the one surface. A wiring board provided with a single or a plurality of lands corresponding to each of the electrodes of the electronic component, and each of the electrodes of the electronic component are bonded to the corresponding land of the wiring substrate, and the electronic component and An anisotropic conductive film, which holds the wiring board integrally, has an almost same shape as the circuit surface of the electronic component, and has an opening corresponding to a predetermined region of the circuit surface. Semiconductor device. 12. The semiconductor device according to claim 11, further comprising an insulating resin that covers a surface side of the electronic component facing the circuit surface.