JP2001102517A - Circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a circuit device wherein a power-source and a ground are supplied to an electronic component housed inside an insulating resin layer with a short wiring distance, for improved electrical, characteristics. SOLUTION: A bare chip 10 is incorporated in insulating resin layers 31 and 32 built up on both surfaces of a multilayer substrate 30, respectively, with wiring layers 40 and 41 on both sides of the bare chip 10 as ground layer, while wiring layers 36 and 39 as power-source line.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit device, and more particularly to a circuit device using a multilayer circuit board having two or more wiring layers.

[0002]

2. Description of the Related Art In a conventional circuit device using a multilayer circuit board, a power supply layer and a ground layer are generally arranged in an inner layer of the board, and through-holes and via holes are used to connect electrodes of electronic components on a surface layer of the board. The connection was made electrically. In particular, in the case of a wiring board having a build-up structure, the wiring layer on the surface layer is often used for component mounting pads and wiring processing.

FIG. 6 shows an example of a circuit device using such a conventional multilayer circuit board. Here, the wiring layers 61, 62, 63, and 64 are formed in four layers by the three insulating layers 60, and the insulating resin layers 65 are respectively formed above and below them.
And a wiring layer 66 is formed on the outer surface of the insulating resin layer 65.

In a multilayer substrate having such a structure, a through hole 67 and a via hole 68 are formed so as to penetrate the insulating layer 60 or the insulating resin layer 65, and wiring layers 61 to 64 and 66 are formed by these interlayer connecting means. Are electrically connected to each other. The bare chip 6 is placed on the wiring layer 66 on the outer surface side of the insulating resin layer 65.
9 and an electronic component 70 composed of an active element or a passive element.

[0005]

As described above, in the conventional circuit device using the multilayer circuit board, the bare chip 69 is mounted on the surface of the outer build-up layer 65. This is because it is necessary to form fine wiring at a portion where the bare chip is to be mounted. Conventionally, power supply lines and ground layers are formed particularly by the inner wiring layers 61 to 64, and these wiring layers 61 to 64 are formed by through holes 67 and via holes 68.
9, 70 electrodes.

Therefore, according to such a wiring structure, wiring is performed from the power supply line or the ground layer in the inner layer through the through hole 67 or the via hole 68.
The wiring length tends to be long. This leads to an increase in inductance component and reactance component due to long wiring, deteriorating the electrical characteristics of the circuit, or causing unnecessary noise to be emitted to the outside, which also affects the outside of the device. Become.

For this reason, measures have been taken such as providing a large number of through-holes 67 so as to strengthen the power supply line and the ground layer so that the power supply line and the ground layer have the same wiring length as the inner layer portion. Was. Here, it becomes necessary to form a considerable number of through holes in order to make the impedance the same.

That is, according to the conventional circuit device, the power supply line and the wiring of the ground layer have a potential difference from the portion formed in the inner layer portion by the wiring resistance, which is a characteristic of the circuit. Deterioration and an increase in impedance due to routing of a power supply line and a wiring of a ground layer in a surface layer portion have caused adverse effects such as unnecessary radiation. In particular, when a structure in which a bare chip such as an LSI is buried in a substrate is employed, the concern associated with the above-described adverse effects deepens.

SUMMARY OF THE INVENTION The present invention has been made in view of such a problem, and enables a power supply line and a ground to be supplied to an electronic component embedded therein with a short wiring distance, and the electrical characteristics are improved. It is an object of the present invention to provide an improved circuit device.

[0010]

According to one aspect of the present invention, in a circuit device using a multilayer circuit board having two or more wiring layers, an insulating resin layer is further formed on the surface of the multilayer circuit board. An electronic component is buried inside the insulating resin layer, a wiring layer is formed on the surface of the insulating resin layer, and the wiring layer is electrically connected to the wiring layer of the multilayer circuit board via interlayer connection means, and The present invention relates to a circuit device, wherein wiring layers on both sides of an electronic component embedded inside the insulating resin layer are used as a power supply line and a ground layer.

Here, it is preferable that the material forming the insulating resin layer has a higher dielectric constant than the insulating material forming the multilayer circuit board. Alternatively, the insulating resin layer may be formed in a plurality of stages, and the electronic component may be embedded in any of the insulating resin layers. Further, a wiring layer formed on the outer surface outside the insulating resin layer may be used as a ground layer, thereby providing a shielding effect.

According to another aspect of the present invention, in a circuit device using a multilayer circuit board having two or more wiring layers, an insulating resin layer is further formed on the surface of the multilayer circuit board, and the insulating resin layer is formed inside the insulating resin layer. A bare chip of an integrated circuit is buried, a wiring layer is formed on a surface of the insulating resin layer, and the wiring layer is electrically connected to a wiring layer of the circuit board via interlayer connection means, whereby the wiring layer is formed. And an active element or a passive element mounted on the surface of the insulating resin layer.

[0013]

According to the present invention, electronic components are embedded in a build-up layer made of an insulating resin layer further provided on the surface of a multilayer circuit board, and such electronic components are placed on both sides thereof. It is connected to the power supply line and the ground line directly or through the interlayer connection means.

According to another aspect of the present invention, a bare chip of an integrated circuit is embedded in a build-up layer formed of an insulating resin layer formed on an outer surface of a multilayer circuit board, and a surface of the insulating resin layer is formed. An active element or a passive element is mounted on a portion where the wiring layer is formed,
These form an electronic circuit.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION
An insulating resin layer is formed on both sides of a multilayer substrate, and LS
The present invention relates to a structure of a circuit device in which electronic components such as I are embedded. In particular, an insulating resin layer is further formed on a multilayer substrate having two or more electric wiring layers, electronic components are accommodated therein, and a wiring layer is formed on the insulating resin layer to form a wiring inside the multilayer substrate. A circuit board having a structure for making electrical connection with a layer, wherein a wiring layer sandwiching an electronic component is a wiring having a power supply line or a ground layer.

Here, the insulating resin layer is preferably made of a material having a higher dielectric constant than the insulating material constituting the multilayer substrate. Further, the insulating resin layer may be formed in a plurality of stages on the wiring board as described above, and the electronic component may be accommodated in any of the layers. Further, in the above wiring structure, it is preferable to use the outermost layer as a ground layer so as to have a shielding effect.

According to the circuit device having such a structure, the power supply line and the ground can be supplied to the electronic components housed in the insulating resin layer with a short wiring distance, and the electric characteristics are improved. Also, when electronic components with a large number of input / output pins are stored inside the board, via holes are used to connect the board surface and the built-in electronic components.However, by arranging the power supply line and ground in a nearby wiring layer, The number of via holes to be formed can be reduced. With such a wiring structure, noise from the outside and unnecessary radiation from the inside can be reduced by the shielding effect of the ground layer formed on the outer surface.

[0018]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. FIG. 1 shows a bare chip 10 of an LSI. Normally, a semiconductor chip is usually surrounded by a package made of a ceramic, a resin material or the like, and is usually provided with a lead frame for external connection. The electrode of the semiconductor chip and the external lead frame are mainly made of Au which is a metal conductor, and are mainly connected by wires such as Al and Cu.

In recent years, with the demand for smaller, lighter and thinner electronic devices, there has been a remarkable movement to directly mount semiconductor chips on circuit boards and respond to the demands. This is called bare chip mounting. The embodiment shown in FIG. 1 is also an embodiment in which such a semiconductor chip 10 can be directly mounted on a circuit board.

The semiconductor chip 10 can be directly mounted on a wiring board by a method of wiring between a semiconductor and a wiring board to be mounted via a wiring board called an interposer;
There is a method of directly mounting a semiconductor chip on a wiring board.
In addition, as a method of connecting the semiconductor chip and the substrate including the interposer, there are a method of forming the bump, that is, a projecting electrode, and a method of connecting directly or through a connecting material such as an anisotropic conductive film or a conductive adhesive. And a method using a wire bonding technique used for forming a package type LSI. In recent years, since the method of forming and connecting bumps can be mounted in a smaller space, they are often used in circuits that require high density, small size, light weight and thinness.

The bumps 11 as shown in FIG. 1 are formed by vapor deposition or sputter vapor deposition using solder, a printing method, Au, Au-Pd.
Method of forming by electroless and electroless plating, such as a material called Al and Cu mainly composed of Au called a stud bump, that is, a thin wire is connected to an LSI electrode portion using heat or ultrasonic waves and cut. Thus, a bump having a predetermined shape is formed. Further, a method of combining two of the above methods is also employed.

The bumps 11 may be formed on the surface of the LSI chip 10 using the electrodes formed for wire bonding as it is, or by performing rewiring to form area pads and forming bumps there. It is roughly divided into those that do. Although the present embodiment allows any type of bare chip mounting, in any case, it is more preferable to adopt a type that can be mounted as thin as possible in the thickness direction of the bare chip 10.

FIG. 2 is an enlarged view of a portion of the bump 11 formed on the bare chip 10. The bump 11 is formed of a solder material or a plating material. Here, an electrode 15 is formed on the outermost surface of the IC circuit 10 formed on the semiconductor wafer, a passivation film such as SiO ₂ or SiN _x is formed, and an opening 17 is formed at a predetermined position. Usually, it is stored in ceramic or mold resin, but here, a heat-resistant resin film such as polyimide for protecting the surface of the semiconductor wafer in this state for bare chip mounting is applied by spin coating or the like. After the aluminum electrode portion 15 is opened, an adhesion metal layer 18 and a diffusion prevention metal layer 19 are formed as shown.

The adhesion metal layer 18 is a layer for ensuring connection with the aluminum electrode 15. The diffusion prevention metal film 19 is a barrier layer for preventing the influence of thermal diffusion on the semiconductor chip 10. Although not shown in FIG. 2, depending on the bump material to be further formed, a metal layer desirable for connection may be formed thereon. As an example, the configuration of a solder bump / Cu / W, a barrier metal layer of Pt, Ni / Ni, Ti, Cr, Ni adhesion film / Al electrode, and the like are known.

The adhesion metal layer 18 and the diffusion preventing metal layer 19 are formed on the electrode portion 15 having the protective resin film opened by a dry system such as vapor deposition, sputter vapor deposition, CVD, or plating. . The plating method places restrictions on materials that can be used irrespective of electrolysis or electroless. In particular, the metal material used for the barrier metal layer has many restrictions. After the above-described film formation is completed, cream-shaped solder is printed and heat-treated, whereby spherical bumps 11 are formed as shown in FIG.

Another method of forming a bump using a solder material is to deposit Pb or Sn on an electrode surface of a Si substrate by an appropriate vapor deposition method, apply a flux or the like, and perform a heat treatment. And Sn are melted to form solder, and are made spherical by the action of surface tension.

The formation of the bumps by plating is performed by plating the electrodes with Au, C by electrolysis and electroless methods using a plating solution.
This is a method in which u, Ni, and the like are accumulated and formed. In general, the plating method has a bump height of about 20 to 40 μm, which is low, and the pad pitch can be narrower than that of solder. On the other hand, solder bumps often have a structure in which creamy solder is re-applied between the electrodes prepared on the electrode side of the board and melt-bonded to the bumps. The pad pitch must be widened. Further, since it is necessary to fill a resin between the substrate and the bare chip in order to protect the joint, it is necessary to increase the bump height.

FIG. 3 shows a structure in which another bump, that is, a stud bump 23 is formed on the electrode 15 of the bare chip 10. The bumps can be formed in the state of the semiconductor wafer or the chip 10 as compared with the formation of the bumps by the soldering and plating method of FIG. 2, and the metal film in the state of the wafer as compared with the configuration shown in FIG. That is, there is no need to add the adhesion metal layer 18 or the diffusion prevention metal layer 19,
In addition, there is a feature that a relatively small pitch can be handled.

As a material of such a bump 23, an Au wire having a diameter of about 20 to 60 μm is mainly used. In principle, this is an application of a technique of connecting a pad made of an aluminum electrode and a lead frame with a wire in the manufacture of a normal package IC. That is, wire wiring is usually performed by a thermocompression bonding method, an ultrasonic method, or a combination thereof. As a means of forming using this method, the connection is usually made under the condition of connecting to the aluminum electrode, the wire is cut perpendicularly to the surface, and the cut surface is crushed by securing a predetermined bump height. It is formed by performing leveling. This method is performed for each pad of the bare chip 10.

In the mounting method of the bare chip 10 having such bumps 23, the bare chip 10 is connected to the substrate by a method of interposing an anisotropic conductive film, Ag paste, cream solder, conductive adhesive or the like.

The bumps 11 and 23 shown in FIG.
The bare chip 10 on which the pattern is formed has a thickness of about 400 to 600 μm especially at the chip portion, but there is also a chip polished to about 50 μm due to a recent demand for a thinner chip. In the present embodiment, the thickness of the chip 10 is set to 100 μm
A bump having a height of about 30 μm is mounted on the surface of the multilayer substrate.

FIG. 4 conceptually shows a mounting state of the bare chip 10 shown in FIG. That is, in FIG.
0 indicates a multilayer substrate having two or more wiring layers. The multilayer substrate 30 may be an organic material substrate or a substrate made of an inorganic material such as ceramic. Then, an LSI composed of the bare chip 10 is mounted on the upper surface and the lower surface of such a multilayer substrate 30, respectively. The LSI 10 has an insulating resin layer 31,
32 buried. The insulating resin layers 31 and 32 are formed by applying and curing a resin material on the front and back of the multilayer substrate 30 by a method such as spin coating or screen printing. Needless to say, the insulating resin layers 31 and 32 are made of a material having reduced stress due to curing shrinkage or a material having heat resistance enough to withstand heat during component mounting. As a characteristic of such a material, a material that can change a dielectric constant, tan δ, or the like is desirable.

The chips 10 buried in the insulating resin layers 31 and 32 may be those shown in FIGS. 1 to 3 and are respectively housed in the insulating resin layers 31 and 32 formed on both surfaces of the multilayer substrate 30. Is done. As a built-in method, the multilayer substrate 30
The bare chip 10 is connected to electrodes provided on the multilayer substrate 30 corresponding to the bumps formed on the LSI side by solder, anisotropic conductive film, conductive adhesive or the like.

FIG. 5 shows the structure of the multilayer substrate 30 shown in FIG. 4 more precisely. In this example, the multilayer substrate 30 is formed from three insulating layers 35, and between these insulating layers 35. In addition, wiring layers 36, 37, 38, and 39 are sequentially formed on the surface of the insulating layer 35 from the top. In addition, the multilayer substrate 3
Insulating resin layers 31 and 32 formed on the upper and lower portions of
Are further formed on the outer surface of the substrate. These wiring layers 36 to 39 are connected to each other via via holes 43 and through holes 44. In the insulating resin layer 31, a via hole 45 penetrating them in the thickness direction is formed. The bumps 11 of the bare chip 10 embedded in the insulating resin layers 31 and 32 are
39. Also, an electronic component 4 composed of active elements and passive elements mounted on the surfaces of the insulating resin layers 31 and 32.
7 and 48 are connected to a wiring layer 50 formed on the wiring layers 40 and 41 via an insulating layer 49.

The multilayer structure shown in FIG. 5 is a substrate in which wiring layers 40, 41, 50 are formed on both sides of a four-layer substrate. Such a substrate is called a build-up substrate and is a substrate used for bare chip mounting or high-density mounting. Although the build-up layers 31, 32, and 49 are formed here two by two, these insulating resin layers 31,
The number of build-up layers composed of 32 is not limited to two, but may be one, or three or more.

As shown in FIG. 5, this embodiment is characterized in that insulating resin layers 31 and 32 thicker than the thickness of the bare chip 10 are formed on both sides of the multilayer substrate 30 and the bare chip 10 is formed therein.
Is to be buried. Here, the thickness of the insulator of the conventional build-up layer is 50 to 80 μm. Here, if the thickness is increased, it becomes difficult to form fine wiring and via holes. In this embodiment, the insulating resin layers 31 and 32 formed on both surfaces of the multilayer substrate 30 have a thickness of about 200 μm, the bare chip 10 is mounted therein, and a via hole is formed by using a laser or a powder beam. I have.

Here, if the power supply line and the ground layer are formed in the inner layer like the conventional multilayer substrate shown in FIG. 6, the wiring length for supplying the power and the ground to the bare chip 10 cannot be shortened. When the wiring layer 40 in FIG. 5 is a power supply line and the wiring layer 41 is a ground layer, power and ground are supplied through the through holes 44 and the via holes 45, and the insulating resin layer 31,
As the thickness of the wiring 32 increases, the wiring length becomes longer, which is disadvantageous. This may cause deterioration of circuit characteristics or unnecessary radiation.

Therefore, this concern can be eliminated by using the wiring layers 36, 39 and 40, 41 formed on both sides of the insulating resin layers 31, 32 containing the bare chip 10 of the LSI as power supply lines and ground layers, respectively. Will be possible. The wiring layers 40 and 41 are ground layers,
By using the power supply lines for the wiring layers 36 and 39, power and ground lines for the bare chip 10 can be formed close to each other.
The number of via holes 45 formed in the first and the second 32 also decreases. A wiring layer 50 is formed directly on the outer surfaces of the wiring layers 40 and 41 or further through an insulating layer 49 to form an electronic component 4.
It is also possible to arrange 7, 48, and taking this into account, the effect becomes very large.

[0039]

According to one aspect of the present invention, in a circuit device using a multilayer circuit board having two or more wiring layers, an insulating resin layer is further formed on the surface of the multilayer circuit board, and the inside of the insulating resin layer is formed. Embed an electronic component, form a wiring layer on the surface of the insulating resin layer, electrically connect the wiring layer to the wiring layer of the multilayer circuit board via interlayer connection means, and bury the wiring layer inside the insulating resin layer. The wiring layers on both sides of the electronic component are used as power supply lines and ground layers.

Therefore, according to such a circuit device, the electronic component is embedded in the insulating resin layer formed on the surface of the multilayer circuit board, and the electronic component is provided on both sides of the power supply line and the ground layer. Connected to the power supply line and the ground layer, so that the length of the wiring for the power supply line and the ground layer can be reduced, and a circuit device having excellent electrical characteristics can be provided.

Another invention of the present application is a circuit device using a multilayer circuit board having two or more wiring layers, wherein an insulating resin layer is further formed on the surface of the multilayer circuit board, and the insulating resin layer is formed inside the insulating resin layer. A bare chip of an integrated circuit is buried, a wiring layer is formed on a surface of an insulating resin layer, and the wiring layer is electrically connected to a wiring layer of a circuit board through an interlayer connection means, and the insulating layer on which the wiring layer is formed is formed. An active element or a passive element is mounted on the surface of a resin layer.

Therefore, according to this structure, the bare chip of the integrated circuit is embedded in the insulating resin layer formed on the outer surface of the multilayer substrate, and the active element or the passive element is mounted on the surface of the insulating resin layer. They are mounted and connected to each other by interlayer connection means to form a circuit device.

[Brief description of the drawings]

FIG. 1 is a sectional view of a bare chip.

FIG. 2 is an enlarged sectional view of a bump formed on the bare chip.

FIG. 3 is an enlarged vertical sectional view of another bump.

FIG. 4 is a vertical sectional view of an insulating resin layer containing a bare chip and a multilayer substrate.

FIG. 5 is a longitudinal sectional view showing the internal structure of the multilayer substrate.

FIG. 6 is a longitudinal sectional view of a conventional circuit device.

[Explanation of symbols]

10 ‥‥ bare chip, 11 ‥‥ bump, 15 ‥‥ electrode,
16 passivation film, 17 opening, 18 adhesion metal layer, 19 diffusion prevention metal layer, 23 stud bump, 30 multilayer substrate, 31, 32 insulation resin layer, 35 Insulation layer, 36 ‥‥ wiring layer, 37-39 ‥‥
Wiring layer, 40, 41 wiring layer, 43 via hole, 44 through hole, 45 via hole, 4
7, 48 ‥‥ electronic component, 49 ‥‥ insulation layer, 50 ‥‥ wiring layer, 60 ‥‥ insulation layer, 61１〜64 ‥‥ wiring layer, 65 ‥‥
Insulating resin layer, 66 ‥‥ wiring layer, 67 ‥‥ through hole,
68 ‥‥ Via Hole, 69 ‥‥ Bare Chip, 70 ‥‥
Electronic components

Claims (5)

[Claims] 1. A circuit device using a multilayer circuit board having two or more wiring layers, wherein an insulating resin layer is further formed on the surface of the multilayer circuit board, and an electronic component is embedded inside the insulating resin layer. Forming a wiring layer on the surface of the insulating resin layer, electrically connecting the wiring layer to the wiring layer of the multilayer circuit board via interlayer connection means, and burying the wiring layer inside the insulating resin layer; Wherein the wiring layers on both sides of the electronic component are a power supply line and a ground layer. 2. The circuit device according to claim 1, wherein a material forming the insulating resin layer has a higher dielectric constant than an insulating material forming the multilayer circuit board. 3. The circuit device according to claim 1, wherein the insulating resin layer is formed in a plurality of stages, and an electronic component is embedded in any of the insulating resin layers. 4. The circuit device according to claim 1, wherein the wiring layer formed on the outer surface outside the insulating resin layer is a ground layer. 5. A circuit device using a multilayer circuit board having two or more wiring layers, wherein an insulating resin layer is further formed on the surface of the multilayer circuit board, and a bare chip of an integrated circuit is provided inside the insulating resin layer. A wiring layer is formed on the surface of the insulating resin layer, and the wiring layer is electrically connected to a wiring layer of the circuit board via interlayer connection means; and the insulating resin layer on which the wiring layer is formed. A circuit device, wherein an active element or a passive element is mounted on a surface of the device.