CN108336056A - General-purpose built-up circuit layer for semiconductor package - Google Patents
General-purpose built-up circuit layer for semiconductor package Download PDFInfo
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- CN108336056A CN108336056A CN201810326389.7A CN201810326389A CN108336056A CN 108336056 A CN108336056 A CN 108336056A CN 201810326389 A CN201810326389 A CN 201810326389A CN 108336056 A CN108336056 A CN 108336056A
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- purpose built
- circuit layer
- area
- semiconductor package
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 44
- 239000000758 substrate Substances 0.000 claims abstract description 35
- 238000009413 insulation Methods 0.000 claims abstract description 15
- 239000004020 conductor Substances 0.000 claims description 3
- 239000000463 material Substances 0.000 abstract description 5
- 238000005538 encapsulation Methods 0.000 description 9
- 230000011664 signaling Effects 0.000 description 4
- 230000005540 biological transmission Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000004064 dysfunction Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000003247 decreasing effect Effects 0.000 description 2
- 230000007812 deficiency Effects 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 241000218202 Coptis Species 0.000 description 1
- 235000002991 Coptis groenlandica Nutrition 0.000 description 1
- 229910000831 Steel Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229920003023 plastic Polymers 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 238000007711 solidification Methods 0.000 description 1
- 230000008023 solidification Effects 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
- H01L23/49531—Additional leads the additional leads being a wiring board
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49861—Lead-frames fixed on or encapsulated in insulating substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Abstract
The invention discloses a kind of general-purpose built-up circuit layers for semiconductor package, it is disposed upon on chip, and chip is disposed upon on substrate, and the general-purpose built-up circuit floor includes extending signal region, at least a relay contact area, access area, power supply area and electric insulation layer, wherein extend signal region, relay contact area, access area and power supply area are to be constructed from a material that be electrically conducting and conductive, and positioned at the upper surface of electric insulation layer.In addition, it includes multiple signal line and multiple connection pads to extend signal region, and relay contact area includes multiple relay contacts.Especially, it is arranged in parallel between each signal line, and connects an at least connection pad, and connection pad, relay contact, access area, power supply area and the pin selecting type are electrically connected by lead to the connection mound of the substrate.
Description
Technical field
The present invention relates to a kind of general-purpose built-up circuit layers for semiconductor package, especially with connection pad, relaying
Contact, access area, power supply area and pin and be electrically connected by corresponding lead according to the electric function of chip.
Technical background
In the encapsulation procedure of the general prior art, need partly to lead to realize using bonding wire or routing (wire bonding)
Electrical connection between the integrated circuit (IC) and lead frame of body, and routing typically uses gold thread, aluminum steel or copper wire, will integrate
The pin of circuit is connected to the pin of lead frame, finally carries out encapsulating solidification and completes to encapsulate.
The pin of integrated circuit must be configured with the design of internal circuit, used and reached optimum performance, and when difference
When routing between pin and corresponding pin occurs to interlock, it is easy to short circuit occur, alternatively, if between pin and pin
Routing is apart from too long, then when follow-up pressing mold is handled, bonding wire is highly susceptible to excessive mould stream punching press and deviates, and influences electrically,
Even short circuit and fail.
Therefore, it is sought after a kind of general-purpose built-up circuit layer for semiconductor package of innovation, can not only simplify and beat
The design of line shortens routing distance, moreover it is possible to avoid interlocking, use and solve above-mentioned problem of the prior art.
Invention content
In view of the deficiencies of the prior art, the object of the present invention is to provide a kind of general-purpose switchings for semiconductor package
Circuit layer.
To realize the above goal of the invention, present invention employs technical solutions as described below：
The present invention discloses a kind of general-purpose built-up circuit layer for semiconductor package comprising：One extends signal region,
Including multiple signal line and multiple connection pads, such signal line are arranged in parallel, and each such signal line connects to few one
Connection pad, and the corresponding connection pad that the different signal line is connected is arranged to be spaced from each other without contacting；At least one relaying
Contact areas, each relay contact area include multiple relay contacts；One access area；One power supply area；And an electric insulation layer, tool
Electric insulating quality, and the extension signal region, at least a relay contact area, the access area and the power supply area are by a conductive material for this
Constitute and it is conductive, and positioned at the electric insulation layer a upper surface；Wherein the general-purpose built-up circuit layer is disposed upon one
One upper surface of chip, and the chip is further placed in a upper surface of a substrate, the substrate have a line pattern and more
A pin, the connection pad, the relay contact, the access area, the power supply area and the pin of the general-purpose built-up circuit layer, selecting type
It is electrically connected by lead to the connection mound of the substrate.
Preferably, this at least a relay contact area is disposed on a left border region of the general-purpose built-up circuit floor, one
Top edge region and a right border region.
Preferably, the access area and the power supply area are arranged to adjacent and do not contact.
Preferably, such signal line connected this at least a connection pad is arranged to wavy arrangement.
Preferably, at least connection pad that such signal line is connected is arranged to parallel shape arrangement.
Preferably, the access area and the power supply area are strip.
In one embodiment of this invention, which is a flash memory.
Preferably, the substrate or the flash memory are equipped with a controller, which has multiple connection gaskets, general-purpose switching
The connection pad of circuit layer, the relay contact, the access area, the power supply area and the contact, selecting type electrically connect by lead
It is connected to the connection mound of the substrate, the connection gasket of the flash memory or the controller.
The present invention discloses another general-purpose built-up circuit layer for being used for semiconductor package comprising：One extends signal
Area, including multiple signal line and multiple connection pads, such signal line are arranged in parallel, and each such signal line connects to less
One connection pad, and the corresponding connection pad that the different signal line is connected is arranged to be spaced from each other without contacting；In at least one
After contact areas, each relay contact area includes multiple relay contacts；One access area；One power supply area；And an electric insulation layer,
Has electric insulating quality, and the extension signal region, at least a relay contact area, the access area and the power supply area are by a conduction material for this
Material constitute and it is conductive, and positioned at the electric insulation layer a upper surface；Wherein the general-purpose built-up circuit layer is disposed upon
One upper surface of one first chip, and first chip is further placed in a upper surface of one of lead frame supporting seat, it should
The connection pad, the relay contact, the access area, the power supply area and pin selecting type of general-purpose built-up circuit layer by lead and
It is electrically connected to one of lead frame pin.
Preferably, this at least a relay contact area is disposed on a left border region of the general-purpose built-up circuit floor, one
Top edge region and a right border region.
Preferably, the access area and the power supply area are arranged to adjacent and do not contact.
Preferably, such signal line connected this at least a connection pad is arranged to wavy arrangement.
Preferably, at least connection pad that such signal line is connected is arranged to parallel shape arrangement.
Preferably, the access area and the power supply area are strip.
Preferably, one second chip is set between first chip and the supporting seat, and this of the general-purpose built-up circuit layer connects
Pad, the relay contact, the access area, the power supply area selecting type are electrically connected one of lead frame pin and second by lead
The connection gasket of chip.
Therefore, compared with the prior art, advantages of the present invention includes：The present invention general-purpose built-up circuit layer can provide substrate,
Signal signaling transfer point between chip can significantly simplify matching for lead so being not required between substrate, chip directly carry out routing
It sets, improves routing yield, and shorten the distance of lead, improve the transmission quality of electrical signal, while being also avoided that lead interlocks,
It effectively prevent that signal short circuit occurs and leads to dysfunction or even fails.
In addition, the general-purpose built-up circuit layer of the present invention has higher design flexibility, exploitation pinboard can be greatly decreased
Design cost is especially not limited to specific chip design, so the present invention can be used on various chips or be taken with it
Match, thus promotes application elasticity and expand application field.
Description of the drawings
Fig. 1 is the schematic diagram of the general-purpose built-up circuit layer for semiconductor package in an exemplary embodiments of the invention.
Fig. 2 is the signal of the general-purpose built-up circuit layer for semiconductor package in another exemplary embodiments of the present invention
Figure.
Fig. 3 is the upper of the semiconductor package completed using the general-purpose built-up circuit layer of an exemplary embodiments of the invention
View.
Fig. 4 is the A-A sectional views of semiconductor package in Fig. 3.
Fig. 5 is another semiconductor package completed using the general-purpose built-up circuit layer of an exemplary embodiments of the invention
Top view.
Fig. 6 is the sectional view of semiconductor package in Fig. 4.
Fig. 7 is the another semiconductor package completed using the general-purpose built-up circuit layer of an exemplary embodiments of the invention
Top view.
Fig. 8 is the sectional view of semiconductor package in Fig. 7.
Fig. 9 is the another semiconductor package completed using the general-purpose built-up circuit layer of an exemplary embodiments of the invention
Sectional view.
Reference sign：10- general-purpose built-up circuit layers, 11- extend signal region, 11A- signal line, 11B- connection pads, 12-
Relay contact area, 12A- relay contacts, the access areas 13-, 14- power supply areas, 15- electric insulation layers, 20- chips, 30- substrates, 32-
Pin, 33 connections are abundant, 34- lead frames, 35- supporting seats, 36- pins, and 40,41- leads, 60- controllers, 62- connection gaskets, 70-
Flash memory.
Specific implementation mode
In view of deficiency in the prior art, inventor is able to propose the present invention's through studying for a long period of time and largely putting into practice
Technical solution.Below in conjunction with attached drawing and more specifically embodiment is to technical scheme of the present invention, its implementation process and principle etc.
Make further clear, complete explanation.
Icon and component symbol is coordinated to do more detailed description to the embodiment of the present invention below, so that being familiar with this skill
Skill person can implement according to this after studying this specification carefully.
Referring to Fig. 1, schematic diagram of the embodiment of the present invention for the general-purpose built-up circuit layer of semiconductor package.Such as figure
Shown in 1, the general-purpose built-up circuit floor 10 of the embodiment of the present invention includes extending signal region 11, at least a relay contact area 12, ground connection
Area 13, power supply area 14 and electric insulation layer 15, wherein extending signal region 11, relay contact area 12, access area 13 and power supply area
14 be to be constructed from a material that be electrically conducting and conductive, and positioned at the upper surface of electric insulation layer 15.Further, above-mentioned extension news
Number area 11 includes multiple signal line 11A and multiple connection pad 11B, wherein such signal line 11A is arranged in parallel, and each signal
A line 11A connections at least connection pad 11B, and the corresponding connection pad 11B that are connected of different signal line 11A be arranged to it is spaced
It opens without contacting.In addition, relay contact area 12 includes multiple relay contact 12A, and electric insulation layer 15 is tool electric insulating quality.
In particular, it is to be constructed from a material that be electrically conducting and have conduction to extend signal region 11, relay contact area 12, access area 13 and power supply area 14
Property, and positioned at the upper surface of electric insulation layer 15.
More specifically, the general-purpose built-up circuit layer 10 in Fig. 1 is that exemplary expression shares 16 signal line 11A,
And it is divided into 4 groups, that is, each group includes 4 signal line 11A, wherein each signal line 11A connect multiple connection pad 11B certainly, because
And it will be apparent that the corresponding connection pad 11B of adjacent two signal line 11A is not in the same horizontal position, but there is difference of height, institute
With on the whole, all signal line 11A are such as to be repeated as many times with the arrangement mode from top to bottom right from a left side, use to be formed
Dipping and heaving it is wavy.This wavy connection pad 11B can solve the problems, such as that chip 20 occurs staggeredly in routing.
In addition, each relay contact 12A in relay contact area 12 can be adopted to turn wire jumper, it is avoided that the distance mistake of lead 40
Yield that is long and influencing routing, or generate the risk of cross-line.Furthermore since access area 13 and power supply area 14 are designed to strip
Shape, so will not all interlock when with 20 routing of chip.Generally speaking, the present invention can provide apply upper shortest routing road
Diameter.
As shown in Fig. 2, the adjacent two signal line 11A and connection pad 11B of the general-purpose built-up circuit layer 10 of the present invention are visually electrical
Connection needs, and is designed as being arranged parallel to each other, so without being limited thereto, and general-purpose built-up circuit layer is adjacent two signal line 11A and connection pad
11B can be the design of the assembled arrangement of rule or random geometry.
As shown in Figures 3 and 4, the semiconductor to be completed using the general-purpose built-up circuit layer of an exemplary embodiments of the invention
The top view and sectional view of encapsulating structure, in this semiconductor package, general-purpose built-up circuit layer 10 of the invention is placement
In the upper surface of chip 20, and chip 20 is further to be placed in the upper surface of substrate 30, and then by general-purpose built-up circuit layer 10
There is provided the electrical signal signaling transfer point between chip 20 and substrate 30 so that the connection pad 11B of general-purpose built-up circuit layer 30, in this
It is electrically connected and extremely should by lead 40 after contact 12A, the access area 12 in relay contact area 12,13 selecting type of power supply area
The connection mound 33 of substrate 30.As shown in figure 3, the connection mound 33 of substrate 30 is electrically connected the power supply area 14, it is to be passed through using lead 40
By the connection pad 11B of the adjacent specific range on same signal line 11A, relaying is electrically connected the connection mound 33 and the electricity of the substrate 30
Source region 14 improves the transmission quality of electrical signal, while can also keep away to prevent deformation that is long using single lead 40 and generating
Exempt from lead 40 to interlock, effectively prevent that signal short circuit occurs and leads to dysfunction or even fails.
As shown in Figures 5 and 6, respectively view and sectional view on another semiconductor package according to the present invention,
And also referring to Fig. 1.In this embodiment, there is semiconductor package lead frame 34, wherein lead frame 34 to be born including one
Seat 35 and a pin 36.The general-purpose built-up circuit layer 10 of the present invention can be placed in the upper surface of the first chip 20, the first chip 20
Be further be placed on the second chip 21, and the second chip 21 be positioned over lead frame 34 supporting seat 35 and simultaneously can be according to first
Lead 40 is electrically connected connecing for general-purpose built-up circuit layer 10 by the electric function of chip 20 and the second chip 21, selecting type respectively
Pad 11B, relay contact 12A, access area 13, power supply area 14 and the connection gasket 22 of the second chip 21 and the pin 36 of lead frame 34.
Therefore the present invention is used for the general-purpose built-up circuit layer of semiconductor package, is suitable for classes of semiconductors encapsulation knot
Structure, such as the attached leaded chip bearing (PLCC) of encapsulation group (DIP), plastics, quadrangle flat panel enclosure group (QFP), low shape four in two-wire
Angle flat panel enclosure group (LQFP), thin small outline border encapsulation group (TSOP), slim quadrangle flat panel enclosure group (TQFP), band bearing are sealed
The non-lead encapsulation group (QFN) of dress group (TCP), ball trellis array (BGA), Chip Size Package group (CSP), quadrangle tablet,
The non-lead encapsulation group (SON) of small-sized outline border, lead frame BGA (LF-BGA), module array encapsulation group type BGA (MAP-BGA)
And the usual well known semiconductor package of memory card (Memory Card) etc..
With further reference to the top view and sectional view of Fig. 7 and Fig. 8, general-purpose built-up circuit of the embodiment of the present invention is respectively utilized
The schematic diagram for the another semiconductor package that layer is completed, and also referring to Fig. 1.It is packet in this semiconductor package
General-purpose built-up circuit layer 10, substrate 30, controller 60 and flash memory 70 containing the present invention, wherein general-purpose built-up circuit layer 10 is to work as
Make the signal switching medium between substrate 30, controller 60, flash memory 70, meanwhile, it is connected using corresponding lead 41.
Furthermore, flash memory 70 is disposed upon the upper surface of substrate 30, and general-purpose built-up circuit layer 10 and controller
60 are disposed upon the upper surface of flash memory 70.Furthermore include multiple connection gaskets 62 positioned at controller 60 on flash memory 70, wherein general-purpose turns
Connecing circuit layer 10 and controller 60 is separated without being in contact.Furthermore please refer to the semiconductor package such as Fig. 9, flash memory
70 can optionally be placed on substrate 30 with controller 60, non-flash memory 70 as shown in Figure 8 and the mode that controller 60 is storehouse
It is placed on substrate 30.Specifically, the controller 60 of Fig. 8 and Fig. 9 is connected by corresponding lead 41 in the way of routing
Certain connection gaskets 62 to general-purpose built-up circuit layer 10 and substrate 30, such as controller 60 may be connected to general-purpose built-up circuit layer 10
Corresponding multiple relay contact 12A, and other connection gaskets 62 may be connected to the corresponding multiple connections mound 33 of substrate 30, make
Obtaining controller 60 can transfer via the signal of general-purpose built-up circuit layer 10 and be electrically connected to substrate 30.
Generally speaking, each connection pad 11B of general-purpose built-up circuit layer 10, each relay contact 12A, access area 13, power supply
14 selecting type of area is by being by corresponding lead and the connection mound 33 of electric connecting substrate 30, the connection gasket 62 of controller 60
Or flash memory 70, in other words, the primary efficacy of general-purpose built-up circuit layer 10 be to provide substrate 30, flash memory 70 and controller 60 it
Between electrical connection so that flash memory 70 is not required to direct routing to substrate 30, controller 60, thus can shorten routing distance, and letter
Change routing configuration, while generation routing being avoided staggeredly to influence electric property.Furthermore above-mentioned semiconductor package is well suited for
Applied to the encapsulation field of memory card, but it is not limited by this.
In conclusion the main characteristic of the invention lies in that providing signal signaling transfer point, general-purpose using general-purpose built-up circuit layer
Built-up circuit layer is electrically connected to substrate by lead, can be substantially so be not required between substrate, chip directly carry out routing
Simplify the configuration of lead, improves routing yield, and shorten the distance of lead, improve the transmission quality of electrical signal, while can also
It avoids lead from interlocking, effectively prevent that signal short circuit occurs and leads to dysfunction or even fails.
Another feature of the present invention is to provide using general-purpose built-up circuit layer electrical between substrate, flash memory, controller
Signaling transfer point, wherein general-purpose built-up circuit layer, controller are on flash memory, and flash memory is electrically connected to the line pattern of substrate.
Since the wiring layout of whole structure simplifies very much, it is well suited for being applied to memory card or needs high integration and more light and short production
The encapsulation process of product.
Generally speaking, the design cost of exploitation pinboard can be greatly decreased in general-purpose built-up circuit layer of the invention, especially
The design flexibility of general-purpose built-up circuit layer is higher, it is not limited to specific chip design, so the present invention can be used in respectively
It arranges in pairs or groups on kind chip or with it, thus promotes application elasticity, expand application field.
It should be appreciated that the above preferred embodiment is merely to illustrate present disclosure, in addition to this, the present invention also has other
Embodiment, as long as those skilled in the art because of technical inspiration involved in the present invention, and use equivalent replacement or equivalent deformation
The technical solution that mode is formed is all fallen in protection scope of the present invention.
Claims (15)
1. a kind of general-purpose built-up circuit layer for semiconductor package, it is characterised in that including：
One extends signal region, including multiple signal line and multiple connection pads, such signal line are arranged in parallel, and each such news
Number linear system connects an at least connection pad, and the corresponding connection pad that is connected of the different signal line be arranged to be spaced from each other without
Contact；
An at least relay contact area, each relay contact area include multiple relay contacts；
One access area；
One power supply area；And
One electric insulation layer, have electric insulating quality, and the extension signal region, an at least relay contact area, the access area and should
Power supply area is made of and conductive a conductive material, and positioned at a upper surface of the electric insulation layer,
Wherein the general-purpose built-up circuit layer is disposed upon a upper surface of a chip, and the chip is further placed in a substrate
One upper surface, the substrate have a line pattern and a multiple pins, the connection pad of the general-purpose built-up circuit layer, the relay contact,
The access area, the power supply area and the pin, selecting type are electrically connected by lead to the connection mound of the substrate.
2. the general-purpose built-up circuit layer according to claim 1 for semiconductor package, it is characterised in that：This is at least
One relay contact area is disposed on a left border region, a top edge region and a right edge for the general-purpose built-up circuit floor
Edge region.
3. the general-purpose built-up circuit layer according to claim 1 for semiconductor package, it is characterised in that：The ground connection
Area and the power supply area are arranged to adjacent and do not contact.
4. the general-purpose built-up circuit layer according to claim 1 for semiconductor package, it is characterised in that：Such news
Number line connected this at least a connection pad is arranged to wavy arrangement.
5. the general-purpose built-up circuit layer according to claim 1 for semiconductor package, it is characterised in that：Such news
At least connection pad that number line is connected is arranged to parallel shape arrangement.
6. the general-purpose built-up circuit layer according to claim 1 for semiconductor package, it is characterised in that：The ground connection
Area and the power supply area are strip.
7. the general-purpose built-up circuit layer according to claim 1 for semiconductor package, it is characterised in that：The chip
System is a flash memory.
8. the general-purpose built-up circuit layer according to claim 7 for semiconductor package, it is characterised in that：The substrate
Or the flash memory is equipped with a controller, which has multiple connection gaskets, the connection pad, the relaying of the general-purpose built-up circuit layer
Contact, the access area, the power supply area and the contact, selecting type be electrically connected by lead the connection to the substrate it is abundant,
The connection gasket of the flash memory or the controller.
9. a kind of general-purpose built-up circuit layer for semiconductor package, it is characterised in that including：
One extends signal region, including multiple signal line and multiple connection pads, such signal line are arranged in parallel, and each such news
Number linear system connects an at least connection pad, and the corresponding connection pad that is connected of the different signal line be arranged to be spaced from each other without
Contact；
An at least relay contact area, each relay contact area include multiple relay contacts；
One access area；
One power supply area；And
One electric insulation layer, have electric insulating quality, and the extension signal region, an at least relay contact area, the access area and should
Power supply area is made of and conductive a conductive material, and positioned at a upper surface of the electric insulation layer,
Wherein the general-purpose built-up circuit layer is disposed upon a upper surface of one first chip, and first chip is further placed in
One upper surface of one of one lead frame supporting seat, the connection pad of the general-purpose built-up circuit layer, the access area, are somebody's turn to do at the relay contact
Power supply area and the pin selecting type are electrically connected by lead to one of lead frame pin.
10. the general-purpose built-up circuit layer according to claim 9 for semiconductor package, it is characterised in that：This is extremely
A few relay contact area is disposed on a left border region, a top edge region and a right side for the general-purpose built-up circuit floor
Fringe region.
11. the general-purpose built-up circuit layer according to claim 9 for semiconductor package, it is characterised in that：This connects
Area and the power supply area are arranged to adjacent and do not contact.
12. the general-purpose built-up circuit layer according to claim 9 for semiconductor package, it is characterised in that：It is such
Signal line connected this at least a connection pad is arranged to wavy arrangement.
13. the general-purpose built-up circuit layer according to claim 9 for semiconductor package, it is characterised in that：It is such
At least connection pad that signal line is connected is arranged to parallel shape arrangement.
14. the general-purpose built-up circuit layer according to claim 9 for semiconductor package, it is characterised in that：This connects
Area and the power supply area are strip.
15. the general-purpose built-up circuit layer according to claim 9 for semiconductor package, it is characterised in that：This
One second chip, the connection pad of the general-purpose built-up circuit layer, the relay contact, the ground connection are set between one chip and the supporting seat
Area, the power supply area selecting type are electrically connected the connection gasket of one of lead frame pin and the second chip by lead.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810326389.7A CN108336056A (en) | 2018-04-12 | 2018-04-12 | General-purpose built-up circuit layer for semiconductor package |
| TW107113313A TWI677956B (en) | 2018-04-12 | 2018-04-19 | A universal transfer layer for semiconductor packaging structure |
| TW107205109U TWM565880U (en) | 2018-04-12 | 2018-04-19 | Universal adapting circuit layer for semiconductor package structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810326389.7A CN108336056A (en) | 2018-04-12 | 2018-04-12 | General-purpose built-up circuit layer for semiconductor package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN108336056A true CN108336056A (en) | 2018-07-27 |
Family
ID=62934105
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810326389.7A Pending CN108336056A (en) | 2018-04-12 | 2018-04-12 | General-purpose built-up circuit layer for semiconductor package |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108336056A (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050224962A1 (en) * | 2004-03-31 | 2005-10-13 | Sharp Kabushiki Kaisha | Manufacturing method for semiconductor integrated circuit, semiconductor integrated circuit, and semiconductor integrated circuit apparatus |
| US20050253278A1 (en) * | 2004-04-30 | 2005-11-17 | Lam Ken M | Universal interconnect die |
| US20050280034A1 (en) * | 2004-06-02 | 2005-12-22 | Fujitsu Limited | Semiconductor device |
| US20130168842A1 (en) * | 2011-12-30 | 2013-07-04 | Chul Park | Integrated circuit packages having redistribution structures |
| US20180019194A1 (en) * | 2016-07-14 | 2018-01-18 | Semtech Corporation | Low Parasitic Surface Mount Circuit Over Wirebond IC |
| CN207966971U (en) * | 2018-04-12 | 2018-10-12 | 苏州震坤科技有限公司 | General-purpose built-up circuit layer for semiconductor package |
-
2018
- 2018-04-12 CN CN201810326389.7A patent/CN108336056A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050224962A1 (en) * | 2004-03-31 | 2005-10-13 | Sharp Kabushiki Kaisha | Manufacturing method for semiconductor integrated circuit, semiconductor integrated circuit, and semiconductor integrated circuit apparatus |
| US20050253278A1 (en) * | 2004-04-30 | 2005-11-17 | Lam Ken M | Universal interconnect die |
| US20050280034A1 (en) * | 2004-06-02 | 2005-12-22 | Fujitsu Limited | Semiconductor device |
| US20130168842A1 (en) * | 2011-12-30 | 2013-07-04 | Chul Park | Integrated circuit packages having redistribution structures |
| US20180019194A1 (en) * | 2016-07-14 | 2018-01-18 | Semtech Corporation | Low Parasitic Surface Mount Circuit Over Wirebond IC |
| CN207966971U (en) * | 2018-04-12 | 2018-10-12 | 苏州震坤科技有限公司 | General-purpose built-up circuit layer for semiconductor package |
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