JPH09260232A - Compound semiconductor substrate and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make it possible to enhance the production efficiency of a compound semiconductor substrate by a method wherein patterns, which are the generation source of cracks generated along cleavage surfaces formed in a compound semiconductor layer, are formed on a single crystal substrate. SOLUTION: Cracks 35 are generated in a GaAs layer 11 grown epitaxially in a thickness thicker than a critical film thickness along cleavage surfaces to be decided by the arrangement of a GaAs crystal with microscopic patterns 30 formed on a silicon substrate 10 as their starting points or end points. That is, the cracks 35, which are generated in the layer 11, are controlled by the patterns 30 formed on the substrate 10. These cracks 35 reach the upper part of the surface of the substrate 10 and a conductive layer 20, which is generated in the part of the interface between the substrate 10 and the layer 11, is divided by the cracks 35. Accordingly, if various types of devices are formed using a substrate obtained in such a way, the devices are formed into devices having good characteristics like ones manufactured using a high-resistance GaAs bulk substrate.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a compound semiconductor substrate formed by epitaxially growing a compound semiconductor layer on a single crystal substrate and a method for manufacturing the same.

[0002]

2. Description of the Related Art A semiconductor device using a compound semiconductor is generally used as a semiconductor device used in a high frequency region because it can operate at higher speeds and higher frequencies than those using a silicon semiconductor. Since it is also used as a semiconductor laser, its usage is gradually expanding.

Despite the increasing demand for devices using compound semiconductors as described above, the diameter of the bulk substrate made of only compound semiconductors is still 3 to 4 inches, and at most 5 inches, 8 inches. Compared with the silicon substrate that has achieved a large diameter such as 12 inches,
This is one of the factors that make mass production of semiconductor devices formed thereon difficult.

Therefore, what is drawing attention is a compound semiconductor substrate in which a compound semiconductor layer is grown on a silicon substrate by an epitaxial growth method. By epitaxially growing the compound semiconductor on the silicon substrate in this way, it becomes possible to increase the diameter of the provided compound semiconductor substrate. In addition, the substrate in which the compound semiconductor layer is formed on this silicon substrate is strong and has high heat conductivity, and therefore has excellent heat dissipation when a semiconductor device is formed.

However, in such a compound semiconductor substrate in which a compound semiconductor layer is formed on a silicon substrate, the silicon of the silicon substrate serves as a donor source for the epitaxially grown compound semiconductor, and at the interface between the silicon substrate and the compound semiconductor layer. A conductive layer having a low resistance value is formed, for example,
A large parasitic capacitance is generated between the electrode, wiring, and pad of an element formed on this compound semiconductor substrate with the electrode, wiring, or pad of another element through this conductive layer, and the high frequency characteristics of the element There is a problem that it adversely affects.

Therefore, in order to prevent such a defect due to the conductive layer, it is necessary to divide the conductive layer portion. Conventionally, as a method for dividing such a conductive layer, for example, Japanese Patent Laid-Open No. 7-326731 has a structure in which GaAs layers 11 and 12 are laminated on a silicon substrate 10 as shown in FIG. Disclosed is a semiconductor device using a substrate, in which a high resistance region 7 is provided in a conductive layer 20 formed at an interface between a silicon substrate 10 and a GaAs layer 11 so as to surround a region including electrodes, wirings or pads. Has been done.

In this publication, a specific example of the high resistance region 7 is that a GaAs layer 11 is formed on a silicon substrate 10.
After epitaxial growth, impurities are ion-implanted into the portion where the high resistance region 7 is formed to increase the resistance of the conductive layer,
Further, the portion to be the high resistance region 7 is removed by etching up to the surface of the silicon substrate (as shown in FIG. 6).
It is formed by this.

[0008]

As described above, in the conventional technique, in order to divide the conductive layer, it is necessary to perform ion implantation after the epitaxial growth or to perform a processing step for removing it by etching.

Therefore, according to the present invention, after the compound semiconductor layer is epitaxially grown, a compound semiconductor substrate is manufactured without performing a special processing step for dividing a conductive layer generated at an interface between the silicon substrate and the compound semiconductor layer. An object of the present invention is to provide a compound semiconductor substrate in which a conductive layer is separated and a method for manufacturing the same, which can improve efficiency.

[0010]

In order to achieve the above object, the present invention according to claim 1 is a compound semiconductor substrate in which a compound semiconductor layer is laminated on a single crystal substrate, and a cleavage plane of the compound semiconductor layer is provided. A compound semiconductor substrate comprising: a crack formed along the crack; and a pattern formed on the single crystal substrate, which is a source of the crack.

[0011] In order to achieve the above object, a second aspect of the invention is provided.
The present invention described is a method for producing a compound semiconductor substrate in which a compound semiconductor layer having a different thermal expansion coefficient from that of the single crystal substrate is epitaxially grown on the single crystal substrate, and the compound semiconductor layer is epitaxially grown on the single crystal substrate. When forming a pattern for generating cracks in the cleavage direction of the compound semiconductor layer, and on the single crystal substrate on which the pattern is formed, the compound semiconductor layer until the film thickness of the crack occurs And a step of epitaxially growing the compound semiconductor substrate.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the accompanying drawings. The members having the same function are designated by the same reference numerals.

One embodiment of the invention described herein is
It is a compound semiconductor substrate (GaAs on Si) in which a silicon substrate is used as a single crystal substrate and a GaAs layer is formed as a compound semiconductor by epitaxial growth on the silicon substrate.

To manufacture a GaAs on Si substrate to which the present invention is applied, first, as shown in FIG.
00) GaAs to be formed later on the silicon substrate 10
A minute pattern 30 is formed at the starting point and the ending point of the crack generated in the layer.

The fine pattern 30 is formed by, for example, silicon oxide (SiO ₂ ) or silicon nitride (SiNx) on the entire surface of the silicon substrate 10 by CVD or thermal oxidation to a thickness of about 0.2 to 0.5 μm, and thereafter. , Resist coating, photolithography and etching,
The square pattern is about 1 to 10 μm square. Here, the size of the minute pattern is set to 1 to 10 μm as described above because the lower limit value is particularly in consideration of the current photolithography and etching technology.
In the case of forming an extremely minute pattern, a special lithography apparatus and method are required, and the cost for the process is high, which is not preferable, and thus such a size is adopted. However, the upper limit of the size is 10 μm,
This is because when a too large pattern is formed, the crystallinity of the GaAa layer to be epitaxially grown thereafter is adversely affected (for example, the crystallinity is not uniform and polycrystallization or irregular cracks occur). Also, the film thickness is not limited to 0.2 to 0.5 μm,
If it is too thin, it is not preferable because it is peeled off by the cleaning process before it or dissolved by the etching action of the cleaning liquid in the GaAs epitaxial growth process described later, and the lower limit is set to about 0.2 μm and the upper limit is set. Is thicker than 0.5 μm,
GaA around this pattern during epitaxial growth
Since it affects the crystallinity of s itself and is not preferable, 0.5
It is about μm.

The pattern interval of this minute pattern 30 is
For example, the pattern of electrodes of GaAs transistors or other elements to be formed later may be matched in advance,
Alternatively, a plurality of transistors or elements to be formed may be formed at a constant interval based on the channel interval so that only a channel formation portion of the transistor or the element is separated from the conductive layer.

Then, GaAs is epitaxially grown on the silicon substrate 10 on which such a minute pattern 30 is formed to a thickness equal to or more than its limit thickness. Here, the limit film thickness is the film thickness at which a crack is generated in the epitaxially grown GaAs layer 11 due to the stress applied due to the difference in thermal expansion coefficient between the grown GaAs and the silicon substrate. This limit film thickness is about 4 μm in the case of GaAs on a silicon substrate as a result of past experience and experiments.

During the epitaxial growth of GaAs, the silicon atoms of the silicon substrate are G
A maximum of 10 silicon atoms diffused into aAs
An n-type conductive layer 20 diffused by about ¹⁸ cm ⁻³ is formed.

As shown in FIGS. 2a and 2b, on the GaAs layer 11 epitaxially grown to a thickness not less than the critical thickness, the fine pattern 30 previously formed on the silicon substrate 10 is formed.
As a start point or an end point, a crack 35 is generated along the cleavage plane determined by the GaAs crystal arrangement. That is, by applying the present invention, the GaAs layer 11
The cracks 35 generated in the above are controlled by the minute pattern 30 formed on the silicon substrate 10.
The crack 35 reaches the surface of the silicon substrate 10 and divides the conductive layer 20 generated at the interface between the silicon substrate 10 and the GaAs layer 11. 2a is a plan view, and FIG. 2b is a sectional view taken along the line CC in FIG. 2a.

Therefore, the GaA thus obtained
When various devices are formed using the sonSi substrate, the conductive layer 20 generated at the interface between the silicon substrate 10 and the GaAs layer 11 is divided at an arbitrary position, so that it is the same as that using the high resistance GaAs bulk substrate. The device has excellent characteristics. When forming this device,
Further on the GaAs layer 11, GaAs and other compound semiconductors such as AlGaAs, InGaAs, InP, Zn
It goes without saying that Se or the like may be laminated.

The present invention can be easily carried out if the compound semiconductor layer can be epitaxially grown on the single crystal substrate so as to have the limit film thickness. GaAs
The layer is not limited to the epitaxially grown layer, and tensile stress may be applied to the compound semiconductor layer on the single crystal substrate due to the difference in thermal expansion coefficient between the single crystal substrate and the compound semiconductor layer formed thereon. Any combination can be suitably implemented. For example, as the single crystal substrate, a SiC single crystal substrate may be used in addition to the silicon substrate, and as the compound semiconductor layer, a III-V group compound semiconductor, for example, III. Ga, In, Al as group elements,
It may be a single layer or a stacked layer of compound semiconductor layers in which As, P, N and the like are appropriately combined as the V group element. Strictly speaking, the critical film thickness on these substrates is determined by the difference in the coefficient of thermal expansion between the substrate and the compound semiconductor layer formed thereon, and the difference in the lattice constant also has an influence, but in many cases the compound semiconductor Approximately the same with respect to the single crystal substrate regardless of the type, and the compound semiconductor layer is cracked at about 4 μm on the silicon substrate and about 0.6 μm on the SiC substrate.

[0022]

EXAMPLES Examples of devices using the compound semiconductor substrate according to the present invention will be described below.

Example 1 Example 1 is a device in which a power semiconductor GaAs MESFET is integrated on a compound semiconductor substrate to which the present invention is applied.
3 is a plan view, FIG. 4a is a sectional view taken along the line AA of FIG. 3, and FIG. 4b is a sectional view taken along the line BB of FIG.

This device has four FETs 41, 4
2, 43, 44 are integrated, and the structure thereof is, as shown in the figure, a high resistance p-type silicon substrate 10 having a specific resistance of 100 Ωcm or more, preferably 500 Ωcm or more, which is a single crystal substrate, and an impurity concentration of 1 ×. 10 ¹⁵ cm ^-3 p-type Ga
An As layer 11 having a thickness of 4 μm and an impurity concentration of 5 × 10 ¹⁶ c
m ⁻³ p-type AlGaAs layer 12 is 1 μm, and an n-type GaAs layer 13 having an impurity concentration of 2 × 10 ¹⁷ cm ⁻³ to be a channel layer is further epitaxially grown thereon to 1 μm. Type GaAs layer 13
Is removed, the gate electrode 4 is formed in the channel portion, and Ga is
A source pad 2 connected to the source region 4, a drain pad 3 similarly connected to the drain region 6, and a gate pad 1 connected to the gate electrode 4 are formed in the portion where the As layer 13 is removed. . Here, the source pad 2 and the drain pad 3 are shared by the four FETs, and the gate pad 1 is shared by the two FETs. In the first embodiment, each FE
A crack 35 is formed so that T is separated.

The crack 35 is the same as that already described as the embodiment, and a fine pattern made of silicon oxide or silicon nitride is previously provided on the silicon substrate 10 at the starting point and the ending point of the crack 35. rear,
It is formed by epitaxially growing the GaAs layer 11 with a thickness of 4 μm, which is the same as the limit film thickness. As a result, the silicon substrate 10 and the GaAs layer 11 are
The conductive layer 20 formed at the interface with and is divided, and the four integrated FETs can be electrically isolated from the conductive layer 20, respectively, and the parasitic capacitance generated in one FET portion is generated in the other FET. It is not coupled in series with the parasitic capacitance, and the characteristics of the device in which the power GaAs MESFET is integrated are improved.

Embodiment 2 Next, an embodiment in which the present invention is applied to manufacture an OEIC will be described.

The OEIC (Opto Electric IC) is an integrated semiconductor laser device and peripheral circuits such as FETs for driving the semiconductor laser device. By applying the present invention as described below, As shown in FIG. 5, the semiconductor laser element 50 and the peripheral circuit 51 such as an FET for driving the semiconductor laser element 50 can be formed on one silicon substrate 10.

In the OEIC according to the second embodiment, on the silicon substrate 10, first, a minute pattern for generating a crack to be a cleavage reflection surface 52 of the semiconductor laser device 50 described later is formed by silicon oxide, silicon nitride or the like. . This minute pattern is the same as that described as the embodiment of the present invention.

After that, a GaAs layer 11 is epitaxially grown on the silicon substrate 10 on which the minute pattern is formed to a thickness such that a crack is not formed, for example, 4 μm or more, and a buffer layer is formed on the GaAs layer 11 in the same manner as in the normal semiconductor laser formation. 61, the clad layer 62, the active layer 60, and various compound semiconductor layers to be the contact layer 63 are laminated.

As a result, cracks are generated when the temperature is lowered from the growth temperature to room temperature with the fine pattern formed on the silicon substrate 10 as the starting point and the ending point.

Since this crack is generated along the cleavage plane of the compound semiconductor layer, this crack can be used as it is as the cleavage reflection plane 52 of the semiconductor laser 50.
After that, unnecessary portions of the GaAs layer formed last are removed to form electrodes, and then all compound semiconductor layers on the silicon substrate 10 other than the portion used as the semiconductor laser device 50 are removed to remove the first surface of the silicon substrate. By exposing the substrate and forming a peripheral circuit 51 such as an FET in this portion, an OEIC in which the semiconductor laser and the peripheral circuit are integrated on the same substrate can be manufactured as described above. The peripheral circuit on the silicon substrate may be formed before forming the compound semiconductor layer. In that case, after the peripheral circuit is formed, a portion where a semiconductor laser element is formed is formed as described above.
After forming a minute pattern that becomes the starting point and the ending point of the crack, epitaxially grow various compound semiconductor layers,
A semiconductor laser device may be formed.

[0032]

According to the present invention described above, the following effects can be obtained for each claim. According to the first aspect of the present invention, in the compound semiconductor substrate in which the compound semiconductor layer is formed on the single crystal substrate, the compound semiconductor layer is formed with a crack having a pattern formed in advance as a generation source.
Since the conductive layer generated at the interface between the compound semiconductor layer and the single crystal substrate can be divided by this crack, when a device is manufactured using this semiconductor substrate, electrodes or wirings between a plurality of elements or within the element, pads Parasitic capacitance generated between them is not coupled through the conductive layer, and the parasitic capacitance of the entire device can be reduced,
Device characteristics can be improved.

According to the second aspect of the present invention, the compound semiconductor layer is epitaxially grown on the single crystal substrate, and the compound semiconductor layer is epitaxially grown on the compound semiconductor layer to be cracked. The position of the crack generated in the layer can be controlled by the pattern formed on the single crystal substrate.For example, if this crack is used for the cleavage reflective surface of the semiconductor laser device, the crack is automatically generated during the manufacturing process of the compound semiconductor substrate. It is possible to obtain a cleavage plane.

[Brief description of drawings]

FIG. 1 is a plan view for explaining an embodiment of the present invention.

2A and 2B are a plan view and a cross-sectional view for explaining an embodiment of the present invention, FIG. 2A is a plan view, and FIG. 2B is a cross-sectional view taken along line CC in FIG. 2A.

FIG. 3 is a plan view of a MESFET device of Example 1 to which the present invention is applied.

4 is a cross-sectional view of the MESFET shown in FIG. 3, FIG.
3 is a sectional view taken along the line AA in FIG. 3, and FIG.
It is sectional drawing which follows the BB line | wire in a middle.

FIG. 5 is a sectional view of an OEIC according to a second embodiment of the present invention.

FIG. 6 is a cross-sectional view of a conventional semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Gate pad, 2 ... Source pad, 3 ... Drain pad, 4 ... Gate electrode, 5 ... Source region, 6 ... Drain region, 10 ... Silicon substrate, 11 ... GaAs layer, 12 ... AlGaAs layer, 13 ... GaAs layer ( Channel), 20 ... Conductive layer, 30 ... Smile pattern, 35 ... Crack, 50 ... Semiconductor laser, 51 ... Peripheral circuit, 52 ... Cleave reflection surface.

Claims (2)

[Claims] 1. In a compound semiconductor substrate in which a compound semiconductor layer is laminated on a single crystal substrate, cracks generated along a cleavage plane of the compound semiconductor layer and generation of the cracks formed on the single crystal substrate. And a pattern serving as a source. 2. A method of manufacturing a compound semiconductor substrate, wherein a compound semiconductor layer having a thermal expansion coefficient different from that of the single crystal substrate is epitaxially grown on the single crystal substrate, wherein the compound semiconductor layer is epitaxially grown on the single crystal substrate. At this time, the step of forming a pattern for generating a crack in the cleavage direction of the compound semiconductor layer, and the epitaxial growth of the compound semiconductor layer on the pattern-formed single crystal substrate until a film thickness of the crack is generated. A method of manufacturing a compound semiconductor substrate, comprising: