JPH09252119A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH09252119A JPH09252119A JP8059043A JP5904396A JPH09252119A JP H09252119 A JPH09252119 A JP H09252119A JP 8059043 A JP8059043 A JP 8059043A JP 5904396 A JP5904396 A JP 5904396A JP H09252119 A JPH09252119 A JP H09252119A
- Authority
- JP
- Japan
- Prior art keywords
- gate electrode
- gate
- well
- insulating film
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 31
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 239000012535 impurity Substances 0.000 claims abstract description 7
- 239000011159 matrix material Substances 0.000 claims abstract description 4
- 239000010410 layer Substances 0.000 claims description 33
- 239000002344 surface layer Substances 0.000 claims description 6
- 239000011229 interlayer Substances 0.000 description 17
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 5
- 238000011084 recovery Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 239000005368 silicate glass Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41741—Source or drain electrodes for field effect devices for vertical or pseudo-vertical devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、縦型ＭＯＳＦＥ
Ｔ，ＩＧＢＴ等の半導体装置に関し、ゲート電極パッド
部の改良に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vertical MOSFE.
The present invention relates to semiconductor devices such as T and IGBTs, and to improvements in gate electrode pad portions.
【０００２】[0002]
【従来の技術】縦型ＭＯＳＦＥＴ，ＩＧＢＴ(insulated
gate bipolar transistor)は、周波数特性に優れ、し
かも低電力で駆動できる等多くの特徴を有することか
ら、幅広い分野で利用されている。従来の縦型ＭＯＳＦ
ＥＴを例に挙げると、図４（ａ）の概略平面図、図４
（ｂ）のＸ−Ｘに沿った断面図に示すように、ｎ+型の
半導体基板１に形成されたｎ型のエピタキシャル層２の
表層部にＰ型のウエル３と矩形環状のｎ+型のソース領
域４とからなる単位セル１０が複数個マトリクス状に形
成されている。この単位セル１０間を電気的に接続する
ソース電極８がソース電極パッド１１に接続するよう形
成されている。2. Description of the Related Art Vertical MOSFETs, IGBTs (insulated)
The gate bipolar transistor) is used in a wide range of fields because it has many characteristics such as excellent frequency characteristics and low power consumption. Conventional vertical MOSF
Taking ET as an example, the schematic plan view of FIG.
As shown in the cross-sectional view taken along the line XX in (b), the P-type well 3 and the rectangular annular n + -type well 3 are formed in the surface layer portion of the n-type epitaxial layer 2 formed on the n + -type semiconductor substrate 1. A plurality of unit cells 10 including the source regions 4 are formed in a matrix. The source electrode 8 that electrically connects the unit cells 10 is formed so as to be connected to the source electrode pad 11.
【０００３】ゲート電極６は単位セル１０間を跨ぐよう
にゲート酸化膜５を介して形成されるとともに、ゲート
電極パッド１２と電気的に接続するよう形成されてい
る。ゲート電極６は比抵抗が比較的高いポリシリコンが
使用されるため、ゲート電極パッド１２から遠い位置の
セル１０に対してはゲート直列抵抗が増大してしまうの
で、アルミニウムからなるゲートフィンガー１３をゲー
ト電極パッド１２から直接チップ内部に延長させて直列
抵抗を低減している。The gate electrode 6 is formed so as to extend across the unit cells 10 with the gate oxide film 5 interposed therebetween and is electrically connected to the gate electrode pad 12. Since the gate electrode 6 is made of polysilicon having a relatively high specific resistance, the gate series resistance of the cell 10 located far from the gate electrode pad 12 is increased. The series resistance is reduced by directly extending from the electrode pad 12 to the inside of the chip.
【０００４】このゲート電極６はソース電極８と短絡し
ないように層間絶縁膜７で覆われているとともに、半導
体基板１の裏面にはドレイン電極９が形成されている。The gate electrode 6 is covered with an interlayer insulating film 7 so as not to be short-circuited with the source electrode 8, and a drain electrode 9 is formed on the back surface of the semiconductor substrate 1.
【０００５】[0005]
【発明が解決しようとする課題】従来の縦型ＭＯＳＦＥ
Ｔでは、ゲート電極パッド１２及びゲートフィンガー１
３下の領域には単位セル１０が形成されず、単位セル１
０間の空乏層の延びがこの領域で分離してしまうのを防
ぐためにドレインとなるエピタキシャル層２とは反対の
導電型のＰ型の第２のウエル１４が絶縁膜１５を介して
形成されている。[Problems to be Solved by the Invention] Conventional vertical MOSFE
At T, the gate electrode pad 12 and the gate finger 1
The unit cell 10 is not formed in the region under 3 and the unit cell 1
In order to prevent the extension of the depletion layer between 0s from being separated in this region, a P-type second well 14 having a conductivity type opposite to that of the epitaxial layer 2 serving as a drain is formed via an insulating film 15. There is.
【０００６】ところで、上述のようにゲートフィンガー
１３として使用される領域には単位セル１０が形成され
ないので、チップ上に占める単位セル１０がその分だけ
少なくなっていた。特に、チップ面積が大きくなるほど
ゲートフィンガー１３を多く形成する必要が生じ、さら
にチップ上に占める単位セル１０が少なくなる傾向にあ
った。By the way, since the unit cell 10 is not formed in the region used as the gate finger 13 as described above, the unit cell 10 occupying the chip is reduced accordingly. In particular, the larger the chip area, the larger the number of gate fingers 13 needed to be formed, and the smaller the unit cells 10 occupied on the chip tended to be.
【０００７】また、チップ面積に応じてゲートフィンガ
ー１３を数多く設けてもチップ上に形成される単位セル
１０の全のゲート電極６に均一にゲート電圧を印加する
ことは比抵抗の関係から困難であった。さらに、Ｐ型の
ウエル３及びウエル１４とｎ型のエピタキシャル層２と
で形成されるＰＮダイオードにおいて、一旦順方向電流
が流れた後、逆回復するときに転流（ｄＶ／ｄｔ）が生
じる。このときウエル３及びウエル１４からエピタキシ
ャル層２に注入されたホールは、注入源の各ウエルに戻
ろうとするが、ウエル１４では抵抗が大きいため、ウエ
ル１４から大量に注入されたホールの大部分が、戻りき
れず近接するウエル３に引き寄せられ、結果、ウエル１
４に近接するウエル３では、他のウエルに対しより多く
の電流が流れることになり、場合によってはに単位セル
１０が破壊されてしまうこともあった。Further, even if a large number of gate fingers 13 are provided according to the chip area, it is difficult to uniformly apply the gate voltage to all the gate electrodes 6 of the unit cells 10 formed on the chip because of the specific resistance. there were. Further, in the PN diode formed by the P-type well 3 and the well 14 and the n-type epitaxial layer 2, a commutation (dV / dt) occurs when reverse recovery is performed after a forward current once flows. At this time, the holes injected from the well 3 and the well 14 into the epitaxial layer 2 try to return to the respective wells of the injection source. However, since the well 14 has a large resistance, most of the holes injected from the well 14 in a large amount. , Could not be returned and was attracted to the adjacent well 3, resulting in well 1
In the well 3 adjacent to the well 4, a larger amount of current will flow to other wells, and the unit cell 10 may be destroyed in some cases.
【０００８】本発明の目的は、上述した問題点に鑑み、
ゲート電極パッドから延長するゲートゲートフィンガー
をなくす構造とするとともに、各単位セルのゲート電極
にゲート電圧が均一に印加できるＭＯＳＦＥＴ，ＩＧＢ
Ｔ等の半導体装置を提供することにある。[0008] In view of the above problems, an object of the present invention is to provide
MOSFETs and IGBs that have a structure in which the gate gate fingers extending from the gate electrode pad are eliminated and that a gate voltage can be uniformly applied to the gate electrode of each unit cell
It is to provide a semiconductor device such as a T.
【０００９】[0009]
【課題を解決するための手段】本発明は、上記目的を達
成するために次のような構成をとる。すなわち、本発明
の半導体装置は、共通ドレイン領域となる半導体基板上
に形成された第１導電型の低不純物濃度層と、前記低不
純物濃度層の表面部に選択的に形成された行及び列のマ
トリクス状に独立に配列された第２導電型のウエル領域
と、前記ウエル領域内の表層部に矩形環状に形成された
第１導電型のソース領域と、前記ウエル領域及び前記ソ
ース領域に共通に接触するソース電極と、前記ウエル領
域間を覆うようにゲート絶縁膜を介して設けられたゲー
ト電極とを有する半導体装置において、前記ゲート電極
パッドがソース電極に形成された絶縁膜上に形成される
とともに、前記絶縁膜に形成された開口部を介してゲー
ト電極と電気的に接続していることを特徴とするもので
ある。The present invention has the following configuration to achieve the above object. That is, the semiconductor device of the present invention includes a low impurity concentration layer of the first conductivity type formed on a semiconductor substrate to be a common drain region, and rows and columns selectively formed on a surface portion of the low impurity concentration layer. Common wells of the second conductivity type well region, the first conductivity type source region formed in a rectangular ring shape in the surface layer portion in the well region, and the well region of the second conductivity type In a semiconductor device having a source electrode in contact with a well and a gate electrode provided so as to cover the well region via a gate insulating film, the gate electrode pad is formed on the insulating film formed on the source electrode. In addition, it is electrically connected to the gate electrode through the opening formed in the insulating film.
【００１０】本発明によれば、ゲート電極パッドをソー
ス電極に形成された絶縁膜上に形成し、絶縁膜に形成さ
れた開口部を介してゲート電極と電気的に接続すること
でゲートフィンガーを設けない構造としているので、ゲ
ートフィンガーが占めていた領域にも単位セルを形成す
ることができ、チップ自体の面積を小さくすることがで
きる。According to the present invention, the gate finger is formed by forming the gate electrode pad on the insulating film formed on the source electrode and electrically connecting to the gate electrode through the opening formed in the insulating film. Since the structure is not provided, the unit cell can be formed in the region occupied by the gate finger, and the area of the chip itself can be reduced.
【００１１】また、本発明によれば、ゲート電極への電
圧の印加は、チップのほぼ全面に形成されたゲート電極
パッドから絶縁膜の開口部を介して行われるので、従来
に比べ均一にしかも速くゲート電極に電圧を伝えること
ができる。さらに、本発明によれば、ゲート電極パッド
およびゲートフィンガーの下部領域にエピタキシャル層
とは反対の導電型の第２のウエルを形成する必要がない
ので、転流（ｄＶ／ｄｔ）が生じても単位セルが破壊さ
れにくくなる。しかも、ホールがウエルに引き抜かれる
時間である逆回復時間（ｔrr）を短くすることもでき
る。Further, according to the present invention, since the voltage is applied to the gate electrode from the gate electrode pad formed on substantially the entire surface of the chip through the opening of the insulating film, it is more uniform than in the prior art. The voltage can be quickly transmitted to the gate electrode. Further, according to the present invention, since it is not necessary to form the second well of the conductivity type opposite to that of the epitaxial layer in the lower region of the gate electrode pad and the gate finger, even if commutation (dV / dt) occurs. Unit cells are less likely to be destroyed. Moreover, the reverse recovery time (t rr ) which is the time taken for the holes to be drawn into the well can be shortened.
【００１２】[0012]
【発明の実施の形態】以下、本発明の実施例を、図面を
参照しつつ具体的に説明する。尚、従来と同一部分や相
当部分には同一の符号を付している。本発明の縦型ＭＯ
ＳＦＥＴは、図１（ａ）の平面図及び（ｂ）のＹ−Ｙ断
面図に示すように、ｎ+型の半導体基板１上にｎ型のエ
ピタキシャル層２が形成されている。これら半導体基板
１ならびにエピタキシャル層２が縦型ＭＯＳＦＥＴの共
通ドレイン領域として働く。このエピタキシャル層２の
表層部には矩形状のＰ型のウエル３が数百から数千個行
及び列にマトリクス配列するように形成されるととも
に、ウエル３内の表層部には矩形環状のｎ+型のソース
領域４が形成されている。これらウエル３とソース領域
４とが単位セル１０を構成している。Embodiments of the present invention will be specifically described below with reference to the drawings. Note that the same reference numerals are given to the same or corresponding parts as in the related art. Vertical MO of the present invention
In the SFET, as shown in the plan view of FIG. 1A and the Y-Y sectional view of FIG. 1B, an n type epitaxial layer 2 is formed on an n + type semiconductor substrate 1. The semiconductor substrate 1 and the epitaxial layer 2 serve as a common drain region of the vertical MOSFET. In the surface layer portion of the epitaxial layer 2, hundreds to thousands of rectangular P-type wells 3 are formed in a matrix arrangement in rows and columns, and in the surface layer portion in the well 3, a rectangular ring-shaped n is formed. A + type source region 4 is formed. The well 3 and the source region 4 form a unit cell 10.
【００１３】このウエル３の半導体基板１側には高濃度
のＰ+型領域３’がエピタキシャル層２に深く形成され
ており、この領域が空乏層を広げ、耐圧を向上させる働
きをする。単位セル１０のソース領域４間を電気的に接
続するために、ウエル３とソース領域４に接触するよう
にアルミニウム等からなるソース電極８が形成されてい
る。このソース電極８はソース電極パッド１１に電気的
に接続されており、ソース電極パッド１１からソース電
極８に電圧が印加される。A high-concentration P + type region 3'is deeply formed in the epitaxial layer 2 on the semiconductor substrate 1 side of the well 3, and this region serves to expand the depletion layer and improve the breakdown voltage. In order to electrically connect the source regions 4 of the unit cell 10, a source electrode 8 made of aluminum or the like is formed so as to contact the well 3 and the source region 4. The source electrode 8 is electrically connected to the source electrode pad 11, and a voltage is applied from the source electrode pad 11 to the source electrode 8.
【００１４】さらに、単位セル１０の間を跨ぐように、
ポリシリコンからなるゲート電極６がゲート酸化膜５を
介して形成されるとともに、ゲート電極６とソース電極
８とが短絡しないよう、例えばリン・シリケートガラス
等からなる層間絶縁膜７で覆われている。そして、半導
体基板１の裏面にはアルミニウム等からなるドレイン電
極９が形成されている。この種の縦型ＭＯＳＦＥＴで
は、ゲート電極６に印加された電圧によりゲート電極６
下部のウエル３の表面にエピタキシャル層２（＝ドレイ
ン領域）とソース領域４とを結ぶチャネル層が形成され
る。このときソース電極８に電圧を印加すると電流がソ
ース電極８からチャネル層を介してエピタキシャル層２
ならび半導体基板１を通過してドレイン電極９に流れ
る。Further, so as to straddle between the unit cells 10,
The gate electrode 6 made of polysilicon is formed via the gate oxide film 5, and is covered with an interlayer insulating film 7 made of, for example, phosphorus silicate glass or the like so that the gate electrode 6 and the source electrode 8 are not short-circuited. . A drain electrode 9 made of aluminum or the like is formed on the back surface of the semiconductor substrate 1. In this type of vertical MOSFET, the voltage applied to the gate electrode 6 causes the gate electrode 6
A channel layer connecting the epitaxial layer 2 (= drain region) and the source region 4 is formed on the surface of the lower well 3. At this time, when a voltage is applied to the source electrode 8, a current flows from the source electrode 8 through the channel layer to the epitaxial layer 2.
Then, it passes through the semiconductor substrate 1 and flows to the drain electrode 9.
【００１５】ところで、本発明ではゲート電極６への電
圧の印加は従来のようなゲートフィンガーを利用せずに
行われている。すなわち、ゲート電極６はソース電極８
と短絡しないように層間絶縁膜７で覆われているが、ゲ
ート電極６上の層間絶縁膜７には開口部１７が形成され
ている。この開口部１７を介してゲート電極６と電気的
に接続するようにアルミニウムからなるゲート電極パッ
ド１６がチップの全面を覆うように形成されている。そ
して、ゲート電極パッド１６とソース電極８が短絡しな
いように第２の層間絶縁膜１８が形成されており、ゲー
ト電極パッド１６とソース電極８とは２層構造となって
いる。By the way, in the present invention, the voltage is applied to the gate electrode 6 without using the conventional gate finger. That is, the gate electrode 6 is the source electrode 8
Although it is covered with the interlayer insulating film 7 so as not to be short-circuited with, an opening 17 is formed in the interlayer insulating film 7 on the gate electrode 6. A gate electrode pad 16 made of aluminum is formed so as to cover the entire surface of the chip so as to be electrically connected to the gate electrode 6 through the opening 17. Then, the second interlayer insulating film 18 is formed so that the gate electrode pad 16 and the source electrode 8 are not short-circuited, and the gate electrode pad 16 and the source electrode 8 have a two-layer structure.
【００１６】ゲート電極６とゲート電極パッド１６を接
続するために形成される開口部１７は、単位セル１０を
避けるようにチップの全面に形成されており、ゲート電
極６とゲート電極パッド１６とは全域で電気的に接続す
る構造となっている。このチップの全面を覆うゲート電
極パッド１６上の点線で示す領域にワイヤがボンディン
グされ、このワイヤからゲート電極パッド１６を介して
ゲート電極６に電圧が印加されることになる。The opening 17 formed to connect the gate electrode 6 and the gate electrode pad 16 is formed on the entire surface of the chip so as to avoid the unit cell 10, and the gate electrode 6 and the gate electrode pad 16 are separated from each other. The structure is such that it is electrically connected throughout the entire area. A wire is bonded to a region shown by a dotted line on the gate electrode pad 16 covering the entire surface of this chip, and a voltage is applied from this wire to the gate electrode 6 via the gate electrode pad 16.
【００１７】単位セル１０間を接続するソース電極８は
チップ全面を覆っているが開口部１７が形成される関係
から網目形状をしており、最終的にソース電極パッド１
１に接続されている。本発明の縦型ＭＯＳＦＥＴによれ
ば、ゲート電極パッド１６をソース電極８に形成された
第２の層間絶縁膜上１８に形成する２層の構造とするこ
とで、ゲート電極６を覆う層間絶縁膜７に形成された開
口部１７を介してゲート電極６と電気的に接続すること
でゲートフィンガーを設けない構造としている。そのた
め、従来ではゲート電極パッド及びゲートフィンガー下
部領域には、空乏層の延びが分離してしまうのを防ぐた
めにエピタキシャル層２の表層部にＰ型の第２のウエル
が形成されているが、ゲートフィンガーが占めていた領
域にも単位セル１０を形成することができるので、チッ
プの面積を変えることなく単位セル１０の数を増やすこ
とができ、チップの縮小化を図ることができる。The source electrode 8 connecting the unit cells 10 covers the entire surface of the chip, but has a mesh shape because of the formation of the opening 17, and finally the source electrode pad 1 is formed.
1 connected. According to the vertical MOSFET of the present invention, the gate electrode pad 16 has the two-layer structure in which it is formed on the second interlayer insulating film 18 formed on the source electrode 8, so that the interlayer insulating film covering the gate electrode 6 is formed. The gate finger 6 is not provided by electrically connecting to the gate electrode 6 through the opening 17 formed in 7. Therefore, in the related art, a P-type second well is formed in the surface layer portion of the epitaxial layer 2 in order to prevent the extension of the depletion layer from being separated in the region below the gate electrode pad and the gate finger. Since the unit cells 10 can be formed in the area occupied by the fingers, the number of unit cells 10 can be increased without changing the area of the chip, and the size of the chip can be reduced.
【００１８】また、ゲート電極６への電圧の印加は、従
来はゲートフィンガーを介して行われていたが、本発明
ではチップのほぼ全面に形成されたゲート電極パッド１
６から層間絶縁膜７の開口部１７を介して行われる。結
果、全てのゲート電極６に均一に電圧を印加でき、しか
もゲート電極パッド１６は比抵抗が小さいので、従来に
比較して速く電圧を伝えることができる。Further, the voltage application to the gate electrode 6 has conventionally been performed through the gate finger, but in the present invention, the gate electrode pad 1 formed on almost the entire surface of the chip.
6 through the opening 17 of the interlayer insulating film 7. As a result, the voltage can be uniformly applied to all the gate electrodes 6, and since the gate electrode pad 16 has a small specific resistance, the voltage can be transmitted faster than in the conventional case.
【００１９】さらに、ゲート電極パッドならびにゲート
フィンガーの下部に第２のウエルを設けられていないの
でホールが大量に注入されることがなく、例え、転流
（ｄＶ／ｄｔ）が生じた場合においても、ウエル３に対
しより多くの電流が流れることにより生じる単位セル１
０の破壊が抑えられる。また、ホールの注入量が少なく
なるので逆回復時間（ｔrr）を短くすることもできる。Further, since the second well is not provided under the gate electrode pad and the gate finger, a large amount of holes are not injected, and even when commutation (dV / dt) occurs, for example. , Unit cell 1 caused by more current flowing to well 3
The destruction of 0 is suppressed. Further, since the injection amount of holes is reduced, the reverse recovery time (t rr ) can be shortened.
【００２０】次に本発明に係る半導体装置の製造方法の
図２の参照に説明する。まず、図２（ａ）に示すよう
に、シリコン基板などのｎ型の半導体基板１上に低濃度
不純物層であるｎ-型のエピタキシャル層２を数１０μ
ｍの厚さに成長させる。これら半導体基板１ならびにエ
ピタキシャル層２が縦型ＭＯＳＦＥＴの共通ドレイン領
域として働く。次に、ドレイン耐圧を高めるため高濃度
のＰ+型領域３’が、ボロンのイオン注入及び熱拡散に
よりエピタキシャル層２内に約３〜６μｍの深さで形成
されている。Next, a method of manufacturing a semiconductor device according to the present invention will be described with reference to FIG. First, as shown in FIG. 2A, an n − type epitaxial layer 2 which is a low concentration impurity layer is formed on the n type semiconductor substrate 1 such as a silicon substrate by several tens μ.
grow to a thickness of m. The semiconductor substrate 1 and the epitaxial layer 2 serve as a common drain region of the vertical MOSFET. Next, a high-concentration P + -type region 3 ′ is formed in the epitaxial layer 2 at a depth of about 3 to 6 μm by ion implantation of boron and thermal diffusion in order to increase the drain breakdown voltage.
【００２１】次に、図２（ｂ）に示すようにエピタキシ
ャル層２を熱酸化して厚さ約１００ｎｍのゲート酸化膜
５を成長させる。このゲート酸化膜５上にＣＶＤ法等に
よりポリシリコンを厚さ約５００ｎｍ堆積し、フォトエ
ッチング法により不要部分を除去してゲート電極６を形
成する。次に、ゲート電極６をマスクにボロンをイオン
注入及び熱拡散することで深さ約４μｍの深さのＰ型の
ウエル３を形成する。Next, as shown in FIG. 2B, the epitaxial layer 2 is thermally oxidized to grow a gate oxide film 5 having a thickness of about 100 nm. Polysilicon is deposited to a thickness of about 500 nm on the gate oxide film 5 by the CVD method or the like, and unnecessary portions are removed by the photo etching method to form the gate electrode 6. Next, boron is ion-implanted and thermally diffused using the gate electrode 6 as a mask to form a P-type well 3 having a depth of about 4 μm.
【００２２】次に、図２（ｃ）に示すように、イオン注
入及び熱拡散により深さ約１．５μｍの矩形環状のｎ+
型のソース領域４をウエル３領域内に形成する。次い
で、ＣＶＤ法等により全面にリン・シリケートガラス
（ＰＳＧ）等からなる厚さ約５００μｍの層間絶縁膜７
を形成する。次に、図３（ｄ）に示すように、層間絶縁
膜７をフォトエッチング法により開口しソース電極８を
形成するための開口部と、ゲート電極パッドとゲート電
極８との接続を可能にするための開口部１７を形成す
る。次いで、アルミニウム等の導電材料を蒸着させた
後、エッチングすることでソース電極８を形成する。こ
のときソース電極８が開口部１７を覆わないように形成
する。Next, as shown in FIG. 2C, a rectangular annular n + having a depth of about 1.5 μm is formed by ion implantation and thermal diffusion.
A source region 4 of the mold is formed in the well 3 region. Then, an interlayer insulating film 7 made of phosphorus silicate glass (PSG) or the like and having a thickness of about 500 μm is formed on the entire surface by CVD or the like
To form Next, as shown in FIG. 3D, it is possible to connect the gate electrode pad and the gate electrode 8 with the opening for forming the source electrode 8 by opening the interlayer insulating film 7 by the photoetching method. The opening 17 for forming is formed. Next, after depositing a conductive material such as aluminum, the source electrode 8 is formed by etching. At this time, the source electrode 8 is formed so as not to cover the opening 17.
【００２３】最後に、図３（ｅ）に示すように、チップ
全面をＣＶＤ法等により絶縁膜で覆い、その後フォトエ
ッチング法によりゲート電極６との開口部１７のみが露
出するように絶縁膜を除去し、第２の層間絶縁膜１８を
形成する。層間絶縁膜１８はソース電極８とゲート電極
パッド１６との短絡を防ぐために設けられている。次い
で、チップ全面にアルミニウムを蒸着しゲート電極パッ
ド１６を形成する。このとき、層間絶縁膜７には開口部
１７が形成されているので、ゲート電極パッド１６とゲ
ート電極６とが開口部１７を介して電気的に接続される
ことになる。最後に、半導体基板１の裏面に導電材料を
蒸着しドレイン電極９を形成することこで、縦型ＭＯＳ
ＦＥＴが完成する。Finally, as shown in FIG. 3E, the entire surface of the chip is covered with an insulating film by the CVD method or the like, and then the insulating film is exposed by the photoetching method so that only the opening 17 with the gate electrode 6 is exposed. Then, the second interlayer insulating film 18 is formed. The interlayer insulating film 18 is provided to prevent a short circuit between the source electrode 8 and the gate electrode pad 16. Then, aluminum is deposited on the entire surface of the chip to form the gate electrode pad 16. At this time, since the opening 17 is formed in the interlayer insulating film 7, the gate electrode pad 16 and the gate electrode 6 are electrically connected through the opening 17. Finally, by depositing a conductive material on the back surface of the semiconductor substrate 1 to form the drain electrode 9, the vertical MOS is formed.
The FET is completed.
【００２４】なお、縦型ＭＯＳＦＥＴでは半導体基板１
とエピタキシャル層２が同じ導電型であるが、ＩＧＢＴ
では半導体基板１とエピタキシャル層２が異なる導電型
を有しているが同様の効果を得ることができる。In the vertical MOSFET, the semiconductor substrate 1
And the epitaxial layer 2 have the same conductivity type, but the IGBT
Then, although the semiconductor substrate 1 and the epitaxial layer 2 have different conductivity types, the same effect can be obtained.
【００２５】[0025]
【発明の効果】以上、説明したように本発明による半導
体装置によれば、ゲート電極パッドをソース電極に形成
された層間絶縁膜上に形成し、層間絶縁膜に形成された
開口部を介してゲート電極と電気的に接続することでゲ
ートフィンガーを設けない構造としているので、ゲート
フィンガーが占めていた領域にも単位セルを形成するこ
とができ、チップ自体の面積を小さくすることができ
る。As described above, according to the semiconductor device of the present invention, the gate electrode pad is formed on the interlayer insulating film formed on the source electrode and the opening is formed on the interlayer insulating film. Since the gate finger is not provided by being electrically connected to the gate electrode, the unit cell can be formed in the region occupied by the gate finger, and the area of the chip itself can be reduced.
【００２６】ゲート電極への電圧の印加は、チップのほ
ぼ全面に形成されたゲート電極パッドから絶縁膜の開口
部を介して行われるので、従来に比べ均一にしかも速く
ゲート電極に電圧を伝えることができる。さらに、本発
明によれば、ゲート電極パッドおよびゲートフィンガー
の下部領域にエピタキシャル層とは反対の導電型の第２
のウエルを形成する必要がないので、転流（ｄＶ／ｄ
ｔ）が生じても単位セルが破壊されにくくなる。しか
も、ホールがウエルに引き抜かれる時間である逆回復時
間（ｔrr）を短くすることもできる。Since the voltage is applied to the gate electrode from the gate electrode pad formed on almost the entire surface of the chip through the opening of the insulating film, the voltage can be transmitted to the gate electrode more uniformly and faster than in the conventional case. You can Further, according to the present invention, the second region of the conductivity type opposite to the epitaxial layer is formed in the lower region of the gate electrode pad and the gate finger.
Since it is not necessary to form a well of the commutation (dV / d
Even if t) occurs, the unit cell is less likely to be destroyed. Moreover, the reverse recovery time (t rr ) which is the time taken for the holes to be drawn into the well can be shortened.
【図１】本発明の実施例を示す説明図。FIG. 1 is an explanatory diagram showing an embodiment of the present invention.
【図２】本発明の製造方法を示す断面図。FIG. 2 is a cross-sectional view showing the manufacturing method of the present invention.
【図３】本発明の製造方法を示す断面図。FIG. 3 is a cross-sectional view showing the manufacturing method of the present invention.
【図４】従来の縦型ＭＯＳＦＥＴを示す平面図。FIG. 4 is a plan view showing a conventional vertical MOSFET.
１ 半導体基板 ２ エピタキシャル層 ３ ウエル ４ ソース領域 ５ ゲート酸化膜 ６ ゲート電極 ７ 層間絶縁膜 ８ ソース電極 ９ ドレイン電極 １０ 単位セル １１ ソース電極パッド １６ ゲート電極パッド １７ 開口部 １８ 層間絶縁膜 1 semiconductor substrate 2 epitaxial layer 3 well 4 source region 5 gate oxide film 6 gate electrode 7 interlayer insulating film 8 source electrode 9 drain electrode 10 unit cell 11 source electrode pad 16 gate electrode pad 17 opening 18 interlayer insulating film
Claims (3)
形成された第１導電型の低不純物濃度層と、前記低不純
物濃度層の表面部に選択的に形成された行及び列のマト
リクス状に独立に配列された第２導電型のウエル領域
と、前記ウエル領域内の表層部に環状に形成された第１
導電型のソース領域と、前記ウエル領域及び前記ソース
領域に共通に接触するソース電極と、前記ウエル領域間
を覆うようにゲート絶縁膜を介して設けられたゲート電
極とを有する半導体装置において、前記ゲート電極パッ
ドがソース電極に形成された絶縁膜上に形成されるとと
もに、前記絶縁膜に形成された開口部を介してゲート電
極と電気的に接続していることを特徴とする半導体装
置。1. A matrix of rows and columns selectively formed on a surface portion of the first conductivity type low impurity concentration layer formed on a semiconductor substrate to be a common drain region. Independently arranged second conductivity type well regions and a first annular region formed in the surface layer in the well regions in a ring shape.
In a semiconductor device having a conductive type source region, a source electrode commonly contacting the well region and the source region, and a gate electrode provided via a gate insulating film so as to cover the well region, A semiconductor device, wherein a gate electrode pad is formed on an insulating film formed on a source electrode and is electrically connected to the gate electrode through an opening formed on the insulating film.
純物濃度層とが同じ導電型を有することで縦型ＭＯＳＦ
ＥＴを構成する請求項１記載の半導体装置。2. The vertical MOSF, wherein the semiconductor substrate and the first conductivity type low impurity concentration layer have the same conductivity type.
The semiconductor device according to claim 1, which constitutes an ET.
純物濃度層とが異なる導電型を有することでＩＧＢＴを
構成する請求項１記載の半導体装置。3. The semiconductor device according to claim 1, wherein the semiconductor substrate and the low-impurity-concentration layer of the first conductivity type have different conductivity types to constitute an IGBT.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8059043A JPH09252119A (en) | 1996-03-15 | 1996-03-15 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8059043A JPH09252119A (en) | 1996-03-15 | 1996-03-15 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH09252119A true JPH09252119A (en) | 1997-09-22 |
Family
ID=13101895
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8059043A Pending JPH09252119A (en) | 1996-03-15 | 1996-03-15 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH09252119A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100967251B1 (en) * | 2002-01-17 | 2010-07-01 | 알스톰 | A matrix converter for transforming electrical energy |
-
1996
- 1996-03-15 JP JP8059043A patent/JPH09252119A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100967251B1 (en) * | 2002-01-17 | 2010-07-01 | 알스톰 | A matrix converter for transforming electrical energy |
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