JPH09252082A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH09252082A JPH09252082A JP8058795A JP5879596A JPH09252082A JP H09252082 A JPH09252082 A JP H09252082A JP 8058795 A JP8058795 A JP 8058795A JP 5879596 A JP5879596 A JP 5879596A JP H09252082 A JPH09252082 A JP H09252082A
- Authority
- JP
- Japan
- Prior art keywords
- recess
- solder
- metal layer
- corner
- insulating substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は半導体装置に係り、
特に内部絶縁型のパワー半導体モジュールに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device,
In particular, it relates to an internally-insulated power semiconductor module.
【０００２】[0002]
【従来の技術】図６に、従来のパワー半導体モジュール
の構造を示す。１はパワー半導体素子、２ａ〜２ｃは半
田、３は絶縁基板、４ａ〜４ｃは金属板、５は支持基
板、６は配線端子、７はボンディングワイヤ、８はケー
ス、９はゲル充填物、１０はレジンである。2. Description of the Related Art FIG. 6 shows the structure of a conventional power semiconductor module. 1 is a power semiconductor element, 2a to 2c are solders, 3 is an insulating substrate, 4a to 4c are metal plates, 5 is a supporting substrate, 6 is a wiring terminal, 7 is a bonding wire, 8 is a case, 9 is a gel filler, and 10 Is a resin.
【０００３】絶縁基板３は、アルミナなどの絶縁材で作
られ、その一方の面には配線パターンが形成された金属
板４ａが、他方の面には半田などの接合材による接合を
可能とするための金属板４ｂがそれぞれ設けられてい
る。金属板４ａの所定の部分には、複数個のパワー半導
体素子１が半田２ｃにより接着される。さらに、金属板
４ｂと支持基板５とが半田２ａによって接着され、絶縁
基板３及び半導体素子１が支持基板５上に積層される。
支持基板５は、パワー半導体素子１で発生した熱を拡散
させるヒートシンクを兼ねているが、実装状態では所定
の冷却フィンに取り付けられる。配線端子６は、金属板
４ａに形成されている配線パターンの所定の部分と外部
導線とを接続する。ケース８は、パワー半導体モジュー
ルの容器を構成し、絶縁材により、側板部を有する底の
無い箱型に作られる。このケース８が支持基板５に接着
されることにより、パワー半導体モジュールの内部が封
止される。このとき、ケース８の内部には、半導体素子
を保護するためのゲル９が封入され、その上にレジン１
０が注入されて固化される。The insulating substrate 3 is made of an insulating material such as alumina, and has a metal plate 4a having a wiring pattern formed on one surface thereof and a bonding material such as solder on the other surface thereof. The metal plates 4b are provided for each of them. A plurality of power semiconductor elements 1 are bonded to predetermined portions of the metal plate 4a with solder 2c. Further, the metal plate 4b and the supporting substrate 5 are bonded by the solder 2a, and the insulating substrate 3 and the semiconductor element 1 are stacked on the supporting substrate 5.
The support substrate 5 also serves as a heat sink for diffusing the heat generated in the power semiconductor element 1, but is attached to a predetermined cooling fin in the mounted state. The wiring terminal 6 connects a predetermined portion of the wiring pattern formed on the metal plate 4a to an external conductor. The case 8 constitutes a container of the power semiconductor module, and is made of an insulating material into a box shape having a side plate portion and having no bottom. By bonding the case 8 to the support substrate 5, the inside of the power semiconductor module is sealed. At this time, a gel 9 for protecting the semiconductor element is enclosed inside the case 8, and the resin 1 is placed on the gel 9.
0 is injected and solidified.
【０００４】[0004]
【発明が解決しようとする課題】従来のパワー半導体モ
ジュールが動作すると、本モジュールには温度変化が生
じる。この温度変化によって、モジュール内の各部材に
は熱膨張係数の違いによる応力が発生する。モジュール
が動作，停止を繰り返すと、この応力によって絶縁基板
下の半田２ａが熱疲労する。熱疲労により、半田には外
周部から亀裂が生じ、最終的には半田が破断してモジュ
ールが破壊する。熱疲労耐量は絶縁基板下の半田厚が厚
いほど高くなることが知られている。When a conventional power semiconductor module operates, the temperature of this module changes. Due to this temperature change, stress is generated in each member in the module due to the difference in thermal expansion coefficient. When the module repeatedly operates and stops, this stress causes thermal fatigue of the solder 2a under the insulating substrate. Due to thermal fatigue, the solder is cracked from the outer peripheral portion, and eventually the solder is broken and the module is broken. It is known that the thermal fatigue resistance increases as the solder thickness under the insulating substrate increases.
【０００５】しかし、絶縁基板下の半田厚を厚くする
と、絶縁基板下の半田の熱疲労耐量は向上するものの、
同時に熱抵抗が高くなる。このため、パワー半導体素子
の温度上昇が大きくなり、モジュールの寿命が短くな
る。However, although increasing the solder thickness under the insulating substrate improves the thermal fatigue resistance of the solder under the insulating substrate,
At the same time, the thermal resistance increases. As a result, the temperature of the power semiconductor element rises significantly and the life of the module is shortened.
【０００６】本発明は、上記の問題点を考慮してなされ
たものであり、半導体装置の寿命を向上することを目的
とする。The present invention has been made in consideration of the above problems, and an object thereof is to improve the life of a semiconductor device.
【０００７】[0007]
【課題を解決するための手段】本発明者の検討によれ
ば、絶縁基板表面に形成される金属層と支持基板を接合
材により接着する場合、熱応力による接合材のクラック
は、金属層の角部において発生しやすい。本検討結果に
基づき、本発明においては、支持基板の金属層との接着
面には、金属層の角部において凹部が設けられ、この角
部の外周が凹部の内側に位置する。According to the study of the present inventor, when a metal layer formed on the surface of an insulating substrate and a supporting substrate are bonded by a bonding material, cracks in the bonding material due to thermal stress are generated in the metal layer. It tends to occur at the corners. Based on the results of this study, in the present invention, a concave portion is provided at the corner of the metal layer on the surface of the support substrate that is bonded to the metal layer, and the outer periphery of this corner is located inside the concave portion.
【０００８】本発明によれば、金属層の角部や凹部にお
いては、接合材の厚みが凹部以外の金属層部分よりも厚
くなるので、熱疲労耐量が向上する。このため、半導体
装置の寿命が長くなる。According to the present invention, at the corners and recesses of the metal layer, the thickness of the bonding material is thicker than that of the metal layer portion other than the recesses, so that the thermal fatigue resistance is improved. Therefore, the life of the semiconductor device is extended.
【０００９】[0009]
【発明の実施の形態】図１は、本発明の一実施例である
パワー半導体モジュールの側面から見た内部の構造を示
す。図２は、図１における支持基板，絶縁基板，パワー
半導体素子の積層部分を示す。なお、これらの図におい
て、図６の各部に対応または相当する部分には同じ符号
を付けている（後述する図３も同様）。FIG. 1 shows the internal structure of a power semiconductor module according to an embodiment of the present invention as seen from the side. FIG. 2 shows a laminated portion of the supporting substrate, the insulating substrate, and the power semiconductor element in FIG. In these figures, parts corresponding to or corresponding to the parts in FIG. 6 are given the same reference numerals (the same applies to FIG. 3 described later).
【００１０】本実施例において従来のパワー半導体モジ
ュールと異なる点は、アルミナ製の絶縁基板３の４個の
角部の直下において、銅製の支持基板５の表面に凹部１
１が設けられる点である。This embodiment is different from the conventional power semiconductor module in that the concave portion 1 is formed on the surface of the support substrate 5 made of copper just below the four corners of the insulating substrate 3 made of alumina.
1 is provided.
【００１１】凹部１１の深さは０.１〜０.３mm程度であ
り、その平面形状は矩形状である。絶縁基板３下の金属
板４ｂの角部の外周が凹部１１の内部に位置する。ま
た、絶縁基板３の外周は、金属板４ｂの外周よりも外側
に在るが、絶縁基板３の角部においては金属基板４ｂと
同様に凹部１１の内部に位置する。すなわち、絶縁基板
３は、その角部の外周が凹部１１からはみ出さないよう
に位置決めされ、半田２ａにより支持基板５と接着され
る。The depth of the recess 11 is about 0.1 to 0.3 mm, and its planar shape is rectangular. The outer periphery of the corner of the metal plate 4b below the insulating substrate 3 is located inside the recess 11. Further, the outer periphery of the insulating substrate 3 is outside the outer periphery of the metal plate 4b, but the corner portion of the insulating substrate 3 is located inside the recess 11 like the metal substrate 4b. That is, the insulating substrate 3 is positioned so that the outer periphery of its corner does not protrude from the recess 11, and is bonded to the supporting substrate 5 with the solder 2a.
【００１２】半田２ａは、凹部１１を埋め、かつ絶縁基
板３の下の凹部１１以外の部分の半田厚さが０.０５mm
程度となるように半田の量が調整される。なお、絶縁基
板３上の金属板４ａに半田２ｃにより接着されるパワー
半導体素子１は、凹部１１以外の部分すなわち半田２ａ
厚さが薄い部分上に位置する。The solder 2a fills the recess 11 and has a solder thickness of 0.05 mm under the insulating substrate 3 except the recess 11.
The amount of solder is adjusted so that it becomes a degree. The power semiconductor element 1 adhered to the metal plate 4a on the insulating substrate 3 by the solder 2c has a portion other than the concave portion 11, that is, the solder 2a.
It is located on the thin part.
【００１３】図４及び図５は、それぞれ絶縁基板下の半
田厚さと半田の熱疲労耐量との関係及び絶縁基板下の半
田厚さと熱抵抗との関係を示し、いずれも本発明者が検
討した結果である。FIGS. 4 and 5 show the relationship between the solder thickness under the insulating substrate and the thermal fatigue resistance of the solder, and the relationship between the solder thickness under the insulating substrate and the thermal resistance, both of which were investigated by the present inventors. The result.
【００１４】図４によれば、本実施例において、凹部１
１内に位置する金属板４ｂの角部では、半田２ａの厚さ
が少なくとも凹部１１の深さすなわち０.１〜０.３mm程
度は確保されるので、それ以外の半田２ａの厚さが０.
０５mm の部分に比べ熱疲労耐量は大きくなる。ところ
で、本発明者の検討によれば、半田に生じるクラックは
金属板４ａの角部から発生し内側へ進展していくことが
多い。従って、本実施例のように金属板４ａの角部のみ
熱疲労耐量を向上すれば、モジュールの寿命は向上す
る。さらに、金属板４ａの角部のみ半田厚さを厚くして
いるので、接着に使用する半田の量はほとんど増加しな
い。According to FIG. 4, in this embodiment, the recess 1
At the corners of the metal plate 4b located inside 1, the thickness of the solder 2a is ensured to be at least the depth of the concave portion 11, that is, about 0.1 to 0.3 mm, so that the thickness of the solder 2a other than that is 0. .
The thermal fatigue resistance is larger than that of the 05 mm portion. By the way, according to the study by the present inventor, cracks generated in the solder often occur from the corners of the metal plate 4a and propagate inward. Therefore, if the thermal fatigue resistance of only the corners of the metal plate 4a is improved as in the present embodiment, the life of the module is improved. Furthermore, since the solder thickness is increased only at the corners of the metal plate 4a, the amount of solder used for bonding hardly increases.
【００１５】さらに図５によれば、熱抵抗が増加するの
は金属板４ａの角部のみであり、半導体素子１が搭載さ
れている位置の直下では熱抵抗は小さい。従って、半導
体素子１からは十分熱が放出されるので、パワー半導体
素子１の特性劣化によりモジュールの寿命が低下するよ
うな不都合は起こらない。Further, according to FIG. 5, the thermal resistance increases only at the corners of the metal plate 4a, and the thermal resistance is small immediately below the position where the semiconductor element 1 is mounted. Therefore, sufficient heat is emitted from the semiconductor element 1, so that there is no inconvenience that the life of the module is shortened due to deterioration of the characteristics of the power semiconductor element 1.
【００１６】図３は、本発明の他の実施例であるパワー
半導体モジュールの内部の構造を示す。本実施例におい
ては、支持基板５において凹部１１が金属板４ｂの外周
部全体に設けられる。凹部１１の外周は金属板４ｂの外
周より外側に位置し、かつ凹部１１の内周は金属板４ｂ
の外周より内側に位置する。本実施例によれば、金属板
４ｂの角部も含め、クラックが発生しやすい外周部全体
に凹部１１が設けられるので、熱抵抗を増加させること
無く半田の熱疲労耐量がさらに向上する。従って、モジ
ュールの寿命がさらに長くなる。FIG. 3 shows the internal structure of a power semiconductor module according to another embodiment of the present invention. In the present embodiment, the recess 11 is provided in the support substrate 5 over the entire outer peripheral portion of the metal plate 4b. The outer periphery of the recess 11 is located outside the outer periphery of the metal plate 4b, and the inner periphery of the recess 11 is the metal plate 4b.
It is located inside the outer circumference. According to the present embodiment, the concave portion 11 is provided on the entire outer peripheral portion where cracks are likely to occur, including the corner portions of the metal plate 4b, so that the thermal fatigue resistance of the solder is further improved without increasing the thermal resistance. Therefore, the life of the module is further extended.
【００１７】なお、上記の各実施例において、パワー半
導体素子１としては、絶縁ゲートバイポーラトランジス
タ（ＩＧＢＴ），パワートランジスタ，パワーMOSFET，
ダイオードなど各種の素子が適用できる。また、支持基
板５としては、銅製のものに限らず、他の金属でもよ
い。特に、支持基板５をモリブデンやタングステンなど
の比較的熱膨張係数が小さく半導体に近い材料を用いれ
ば、さらに熱疲労耐量が向上する。また、半田の代わり
に銀ろうなどの金属ろう材を接合材として用いてもよ
い。また、絶縁基板に限らず、接合材により支持基板と
接着される部材がある場合には、本実施例のような凹部
を設けることにより、接合材の量をあまり増やすこと無
く、接合材の熱疲労耐量を向上できる。In each of the above embodiments, the power semiconductor element 1 is an insulated gate bipolar transistor (IGBT), a power transistor, a power MOSFET,
Various elements such as diodes can be applied. Further, the support substrate 5 is not limited to the one made of copper, but may be another metal. In particular, if the supporting substrate 5 is made of a material such as molybdenum or tungsten which has a relatively small thermal expansion coefficient and is close to a semiconductor, the thermal fatigue resistance is further improved. Further, instead of solder, a metal brazing material such as silver brazing material may be used as a joining material. In addition to the insulating substrate, when there is a member that is bonded to the supporting substrate by the bonding material, the recess of the present embodiment is provided so that the amount of the bonding material is not increased so much that the heat of the bonding material is increased. Fatigue resistance can be improved.
【００１８】[0018]
【発明の効果】本発明によれば、モジュール型半導体装
置の寿命が長くなり高い信頼性が得られる。According to the present invention, the module-type semiconductor device has a long life and high reliability.
【図１】本発明の一実施例であるパワー半導体モジュー
ルの側面から見た内部の構造。FIG. 1 is an internal structure of a power semiconductor module according to an embodiment of the present invention as seen from a side surface.
【図２】図１における支持基板，絶縁基板，半導体素子
の積層部分。FIG. 2 is a laminated portion of a supporting substrate, an insulating substrate, and a semiconductor element in FIG.
【図３】本発明の他の実施例であるパワー半導体モジュ
ールの内部の構造。FIG. 3 is an internal structure of a power semiconductor module which is another embodiment of the present invention.
【図４】絶縁基板下の半田厚さと半田の熱疲労耐量との
関係。FIG. 4 shows the relationship between the solder thickness under the insulating substrate and the thermal fatigue resistance of the solder.
【図５】絶縁基板下の半田厚さと熱抵抗との関係。FIG. 5 shows the relationship between the solder thickness under the insulating substrate and the thermal resistance.
【図６】従来のパワー半導体モジュールの構造。FIG. 6 is a structure of a conventional power semiconductor module.
１…パワー半導体素子、２ａ〜２ｃ…半田、３…絶縁基
板、４ａ〜４ｂ…金属板、５…支持基板、６…配線端
子、７…ボンディングワイヤ、８…ケース、９…ゲル、
１０…レジン、１１…凹部。DESCRIPTION OF SYMBOLS 1 ... Power semiconductor element, 2a-2c ... Solder, 3 ... Insulating substrate, 4a-4b ... Metal plate, 5 ... Support substrate, 6 ... Wiring terminal, 7 ... Bonding wire, 8 ... Case, 9 ... Gel,
10 ... Resin, 11 ... Recessed portion.
Claims (3)
れ、他方の表面には金属層が形成される絶縁基板と、 接合材により前記金属層と接着される支持基板と、を備
え、 支持基板の金属層との接着面には、該金属層の角部にお
いて凹部が設けられ、該角部の外周が該凹部の内側に位
置することを特徴とする半導体装置。1. An insulating substrate having a semiconductor element and a pair of surfaces, a semiconductor element being mounted on one surface, and a metal layer being formed on the other surface, and an adhesive substrate bonded to the metal layer. And a concave portion is provided at a corner portion of the metal layer on a surface of the supporting substrate that is bonded to the metal layer, and an outer periphery of the corner portion is located inside the concave portion. Semiconductor device.
子の直下には位置しないことを特徴とする半導体装置。2. The semiconductor device according to claim 1, wherein the recess is not located immediately below the semiconductor element.
の外周に沿って設けられ、凹部の外周は金属層の外周よ
り外側に位置し、凹部の内周は金属層の外周より内側に
位置することを特徴とする半導体装置。3. The recess according to claim 1, wherein the recess is provided along the outer circumference of the metal layer, the outer circumference of the recess is located outside the outer circumference of the metal layer, and the inner circumference of the recess is located inside the outer circumference of the metal layer. A semiconductor device characterized by being located.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8058795A JPH09252082A (en) | 1996-03-15 | 1996-03-15 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8058795A JPH09252082A (en) | 1996-03-15 | 1996-03-15 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH09252082A true JPH09252082A (en) | 1997-09-22 |
Family
ID=13094523
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8058795A Pending JPH09252082A (en) | 1996-03-15 | 1996-03-15 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH09252082A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013187396A (en) * | 2012-03-08 | 2013-09-19 | Daikin Ind Ltd | Power module |
| JP2021040119A (en) * | 2019-09-05 | 2021-03-11 | 朋程科技股▲ふん▼有限公司 | Package structure for power device |
-
1996
- 1996-03-15 JP JP8058795A patent/JPH09252082A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013187396A (en) * | 2012-03-08 | 2013-09-19 | Daikin Ind Ltd | Power module |
| JP2021040119A (en) * | 2019-09-05 | 2021-03-11 | 朋程科技股▲ふん▼有限公司 | Package structure for power device |
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