JPH09251799A - Semiconductor integrated circuit and test method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable testing an incorporated memory at high speed and to reduce a manufacturing cost without degrading quality of a semiconductor product. SOLUTION: When a test is performed, a low-order address decoder 33 interrupts a bit line switch section 34 in accordance with a control signal 1 for a test. Also, a switch section 36 for a test is made continuity in accordance with a control signal 2 for a test, and electrically connects each bit line BL1 to BLn and corresponding terminals 6c1 to 6cn respectively. Further, a high-order address decoder 32 selects some word line based on an inputted address, and activates all memory cells on this word line. In this state, an user applies the prescribed voltage for a test to terminals 6c1 to 6cn , and tests simultaneously data stored by activated each memory cell depending on a value of a current made to flow in.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit equipped with a memory such as a one-chip CPU (Central Processing Unit), and more particularly to a semiconductor integrated circuit having a test mode for testing data stored in the memory, And the test method.

[0002]

2. Description of the Related Art In recent years, the degree of integration of semiconductor integrated circuits has improved more and more, and ROM (Read-Only Memory) and RAM
CPU (Central Processing Unit) for storage devices such as (Random access Memory) and peripheral circuits such as timer unit.
A one-chip microcomputer (one-chip microcomputer) provided on the same chip as is also widely used. In the one-chip microcomputer incorporating the ROM, when testing the written data, the data is read from all bits (data bit width) over all addresses (all areas of the address space) to perform the test.

Specifically, as shown in FIG. 4, when an address to be tested is designated in the ROM section 50 provided for each output data bit, the upper address decoder 52 is arranged in a matrix. it is no memory cell C ₁₁ in the memory cell portion 51 consisting of C _mn, selects a word line WL _i connected to the memory cell C _ij corresponding to the address, it is arranged on the word line WL _i memory Activate all cells C _ij . Further, the lower address decoder 53 recognizes the bit line BL _j to which the memory cell C _ij corresponding to the designated address is connected, and the bit line switch unit interposed between each bit line BL and the amplification unit 55. Bit line switch BS provided at the end of the bit line BL _j
Make W _j conductive. As a result, the signal from the desired memory cell C _ij is transmitted to the amplification section 55 via the bit line switch BSW _j , and the amplification section 55 amplifies this signal and outputs it from the output terminal. The above operation is performed by the ROM unit 5
ROM by repeating over all addresses of 0
It is possible to test whether or not all the data stored in the unit 50 is normally written.

[0004]

However, in the ROM section 50 having the above configuration, when detecting whether or not the written data is normal, all the addresses are individually designated in an arbitrary order, and all the bits are written. It is necessary to read and inspect the data. Therefore, there is a problem that the test time increases as the storage capacity of the ROM unit 50 increases. In recent years, the storage capacity has increased as the integration degree of semiconductor integrated circuits has improved, and the increase in test time has become a major problem.

In order to solve this problem, for example, in Japanese Unexamined Patent Publication No. 4-328399, the data of each memory cell C _ij is not read, but only the signatures of a plurality of memory cells C _ij are read and the memory cell C _ij is read. A semiconductor integrated circuit for testing ... Is disclosed. In the semiconductor integrated circuit, the memory cells C _ij on one word line are activated at one time, and the data in the memory cell group is latched in the shift register group (latch circuit group). Further, the data compression circuit receives and compresses the data from the shift register group, and takes the signature of the memory cells C _ij ... On the word line. After that, the data compression circuit outputs only the signature from the output terminal. Therefore,
For each word line, the user can test the data stored in the memory cell group on the word line depending on whether the output signature has a desired value. As a result, the time required to test the data stored in the memory cell unit 51 is shortened according to the data compression rate.

However, in the semiconductor integrated circuit having the above-mentioned configuration, since data compression is performed, there is a possibility that data defects may be missed. Therefore, a new problem that the quality of the semiconductor integrated circuit is deteriorated occurs, and the above problem has not been completely solved.

In addition, since the transistors of the memory cell section 51 generally have low driving ability, some kind of amplifier circuit is required for each bit line when transferring the data of the bit line to the shift register group. Furthermore, it is necessary to add a data compression circuit and the like. As a result, the circuit area of the semiconductor integrated circuit increases and the manufacturing cost of the semiconductor integrated circuit also increases.

The present invention has been made in view of the above problems, and an object of the present invention is to test stored data at high speed without deteriorating the quality of semiconductor products, and to manufacture the same. An object of the present invention is to provide a low cost semiconductor integrated circuit and a test method thereof.

[0009]

In order to solve the above-mentioned problems, a semiconductor integrated circuit according to a first aspect of the present invention includes a plurality of bit lines and a plurality of word lines which are arranged orthogonal to each other, and both lines. In a semiconductor integrated circuit having memory cells arranged at the respective intersections and connected to both lines, the following means are taken.

That is, a plurality of test terminals, activation means for simultaneously activating a plurality of memory cells arranged on the same word line in a test mode for testing the contents of each memory cell, and each of the above-mentioned test terminals. A switching means is provided between the terminal and each bit line, and electrically connects each test terminal and the bit line to which the activated memory cell is connected in the test mode. .

In the switching means, when the test terminals and the bit lines have a one-to-one correspondence,
It is composed of switches and the like, and in the case of one-to-many correspondence, it is composed of a multiplexer and the like.

In the above structure, the activating means activates the plurality of memory cells connected to the word line in the test mode, for example, by applying a predetermined voltage to the word line to be tested. Further, the switching means electrically connects each test terminal to the corresponding bit line by, for example, making the switch conductive or causing the multiplexer to select the switch. Further, for example, by supplying a voltage or current to each test terminal, the state of the memory cell connected to the corresponding bit line and activated is tested.

Therefore, the contents of multiple memory cells can be tested simultaneously. Therefore, as compared with the conventional semiconductor integrated circuit in which an address is designated for each memory cell to test the content, the time required for testing the memory cell can be significantly reduced. Further, the accuracy of the test, that is, the quality of the semiconductor integrated circuit can be improved as compared with the configuration in which the content of the memory cell is tested only by the conventional signature.

According to a second aspect of the present invention, in the semiconductor integrated circuit according to the first aspect of the invention, the test terminals and the bit lines have a one-to-one correspondence, and the activating means is In the test mode, all memory cells arranged on the same word line are activated.

There is a one-to-one correspondence between each test mode and bit line.
Therefore, the switching means can be easily realized by a switch having a simple structure.
Further, since the contents of all the memory cells arranged on the same word line can be tested at the same time, the time required for the test can be further shortened as compared with the case of testing a part of the memory cells arranged on the word line.

Furthermore, a semiconductor integrated circuit test method according to a third aspect of the present invention is the semiconductor integrated circuit test method according to the first aspect, wherein a plurality of memory cells are arranged on the same word line in the test mode. Simultaneously activating the memory cells, conducting the switching means provided in the activated memory cells and the corresponding test terminals, and simultaneously applying a predetermined voltage to each of the test terminals. And a step of measuring the current flowing into each test terminal when a voltage is applied and simultaneously measuring the state of each memory cell connected to each test terminal.

According to the above method, the content of the memory cell is tested by the current value flowing into each memory cell, so that the driving capability of the memory cell is higher than that in the case of driving the device connected to the test terminal. Can be kept low. Therefore, even if a memory cell having a low driving capability as in the conventional case is used, it is not necessary to provide an amplifier between each memory cell and the test terminal. As a result, the structure of the semiconductor integrated circuit can be simplified. As a result, a semiconductor integrated circuit having a short test time and a simple structure can be realized.

On the other hand, in order to solve the above-mentioned problems, a semiconductor integrated circuit according to a fourth aspect of the present invention has a plurality of bit lines and a plurality of word lines arranged orthogonally to each other, and each intersection of both lines. In a semiconductor integrated circuit having a memory cell connected to both lines,
It is characterized by the following measures.

That is, a plurality of test terminals, activation means for simultaneously activating a plurality of memory cells arranged on the same word line in a test mode for testing the contents of each memory cell, and each of the above test An amplifying means which is interposed between the terminal and each bit line, individually amplifies the signal of the bit line connected to the activated memory cell in the test mode, and outputs the amplified signal to the corresponding test terminal. Is equipped with.

In the above structure, the activating means activates a plurality of memory cells connected to the word line to be tested at the same time in the test mode, similarly to the activating means according to the first aspect. Further, each amplification means amplifies the signal of the corresponding bit line and outputs it to the corresponding test terminal as a difference in voltage level, for example.

Therefore, the contents of each activated memory cell can be tested at the same time, for example, as the voltage level output to the corresponding test terminal. Therefore,
As compared with the conventional semiconductor integrated circuit in which an address is designated for each memory cell to test the contents, the time required for testing the memory cell can be significantly reduced.

In addition, since each amplifying means amplifies the signal on the bit line, the contents of the memory cell can be tested, for example, as a difference in voltage level, as in the data output during normal use. As a result, in the test device for testing the semiconductor integrated circuit, the circuit for testing the data output in the normal state and the circuit for testing the data in the test mode can be shared. As a result, the configuration of the test device for testing the semiconductor integrated circuit can be made easier than that of the semiconductor integrated circuit according to the first aspect.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an embodiment of the present invention.
The following is a description with reference to FIG. That is, as shown in FIG. 2, a one-chip microcomputer (semiconductor integrated circuit) 1 according to this embodiment includes a CPU 2, a ROM (Read-Only Memory) unit 3, and a RAM (Random access Memory) that are connected to each other by an internal bus. ) 4, a timer unit 5, and a group of ports 6 for transmitting and receiving data to and from external devices (not shown) such as controlled devices and test devices.

At the time of normal use, the port group 6 is connected to the controlled device, and the CPU 2 causes the port group 6 to be connected.
Data of the control target device received through the timer unit 5
Based on the time data obtained from the above, a predetermined program stored in the ROM section 3 can be executed to control the above-mentioned controlled device via the port group 6. In addition, RAM
Reference numeral 4 is used as a work area when the program is executed.

A first port group 6a for applying a control signal to the port group 6 in the test mode for testing the data stored in the ROM section 3 and a second port group 6 for instructing the ROM section 3 to verify an address. Port group 6b and ROM
A third port group (test terminal) 6c for testing the data of the section 3 is provided.

In the one-chip microcomputer 1 according to this embodiment, 100 to 200 or more are provided, which is a sufficiently large number for the number of terminals required to control the ROM section 3 of 30 to 40, as in a normal one-chip microcomputer. It is provided in the port group 6.
Therefore, even if the port groups 6a, 6b, 6c used only in the test mode are provided in the port group 6, no trouble occurs.

These port groups 6a, 6b, 6c are used for other purposes such as transmitting a control signal to the above-mentioned controlled device or outputting the data itself of the ROM section 3 except in the test mode. Has been diverted to. Of the third port group 6c, the port group that outputs the data itself of the ROM section 3 during normal use is particularly referred to as a fourth port group 6d. The number of terminals of the port group 6 can be reduced by using the port group 6 of the one-chip microcomputer 1 for different purposes in the test mode and the normal use.

As shown in FIG. 1, the ROM section 3 includes a plurality of word lines WL ₁ to WL _m and a plurality of bit lines BL ₁ to BL arranged so as to intersect each other.
_n , and the memory cell C arranged at each intersection of the two
Based on an address designated by the memory cell unit 31 having ₁₁ to C _mn and the second port group 6b or the CPU 2 or the like, the word lines WL ₁ to W ₁
An upper address decoder (activating means) 32 for selecting any one of L _m and each of the bit lines BL ₁ to BL
Each bit line switch BSW ₁ provided at one end of _n
To BSW _n bit line switch unit 34
A lower address decoder 33 for controlling conduction / interruption of each bit line switch BSW ₁ to BSW _n based on the address, and each bit line switch B
The signal from SW ₁ to BSW _n is amplified to
It is provided with an amplification unit 35 for outputting to the port group 6d or the CPU 2 or the like. In the following, when any member among a plurality of members is shown like any of the memory cells C ₁₁ to C _mn , for example, the memory cell C
_{Like ij} , display with subscript _i or subscript _j .

In the memory cell section 31 according to this embodiment,
Each memory cell C _ij has one cell transistor Tr _ij, the gate of the cell transistor Tr _ij is the adjacent word lines WL _i, drain the adjacent bit lines BL _j, are connected ing. In addition,
The source of each cell transistor Tr _ij is grounded.

The high-order address decoder 32 is shown in FIG.
A gate voltage is applied to the word line WL _i connected to the desired memory cell C _ij based on the address designated by the second port group 6b shown in FIG.
As a result, all the memory cells C _i1 to C _in connected to the word line WL _i can be activated at the same time.

Further, the lower address decoder 33
Turns on the bit line switch BSW _j connected to the desired memory cell C _ij and cuts off the remaining bit line switch BSW based on the address. As a result, among the activated memory cells C _i1 to C _in , only the memory cell C _{ij at} a desired address is electrically connected to the amplification unit 35 via the bit line switch BSW _j .

On the other hand, the amplifying section 35 includes a load transistor 35a for supplying a current to the selected memory cell C _ij via each bit line switch BSW _j and bit line BL _j , the load transistor 35a and each bit. The amplifier 35b that amplifies the potential at the connection point of the line switch BSW is provided. The amount of current flowing from the load transistor 35a to the selected memory cell C _ij differs depending on whether the memory cell C _ij stores high data or low data. Therefore, the output potential of the bit line switch BSW _j changes. By the amplifier 35b amplifying the potential,
The data stored in the memory cell C _ij can be output.

In the present embodiment, the ROM section 3 has, for example, a capacity of 2048 × 8 bits, and is configured to read out 8-bit data in parallel from an address designated by 11 bits. Therefore, the memory cell unit 31, the bit line switch 34, and the amplification unit 35.
Are provided, and the high-order address decoder 32 and the low-order address decoder 33 include
34 and 35 are controlled respectively. Also, 2048
Each memory cell portion 31 having a bit capacity includes 32 word lines WL and 8 bit lines BL. Therefore, 32 terminals 6c _j are required for the data width of the ROM section 3, that is, for every 8 terminals. Therefore,
In the present embodiment, the total number of terminals of the third port group 6c including the fourth port group 6d is set to 32 × 8 bits = 256. Since the 1-chip microcomputer 1 according to the present embodiment is provided with 100 to 200 or more terminals as the port group 6, even if these terminals are assigned to the third port group 6c only in the test mode. , Does not cause any problems.

Further, the ROM section 3 according to the present embodiment is
A test switch SW (switching means) for selecting whether to output the signal of each bit line BL to the third port group 6c based on the test control signal 2 input from the first port group 6a shown in FIG. ), And the test switch section 36 is composed of these test switches SW ₁ to SW _n . Switch SW for each test
One end of _j is connected to the corresponding bit line BL _j at the connection point of the bit line switch BSW _j and the memory cell section 31, and the other end is provided in the third port group 6c shown in FIG. It is directly connected to the terminal 6c _j .

As a result, when the test control signal 2 is input, the test switches SW ₁ to SW _n become conductive, and each memory cell C _ij and each terminal 6c _j can be electrically connected. On the other hand, while the test control signal 2 is not input, the test switches SW ₁ to SW _n
Are shut off, and the third port group 6c and the memory cell portion 31 can be electrically insulated. Therefore, the amplification unit 3
5 can amplify the signal of the selected memory cell C _ij without being affected by the device connected to the third port group 6c.

Further, the lower address decoder 33 according to the present embodiment can shut off each bit line switch unit 34 when the test control signal 1 is input from the first port group 6a shown in FIG. As a result, the memory cell section 31 and the amplification section 35 can be insulated from each other in the test mode.

Next, the operation of each part at the time of testing the memory cell in the above structure will be described as follows.

That is, when testing the memory cell, the user inputs the test control signal 1 and the test control signal 2 to the one-chip microcomputer 1 through the first port group 6a shown in FIG. Test switches SW ₁ to SW
_n conducts according to the instruction of the test control signal 2. As a result, the bit lines BL ₁ to BL _n are electrically connected to the corresponding terminals 6c ₁ to 6c _n , respectively. When the test control signal 1 is input, the lower address decoder 33 receives the bit line switch BSW ₁
To BSW _n are cut off. As a result, each bit line BL _j is electrically insulated from the amplification unit 35.

In this state, the user inputs the address indicating the word line WL _i to be tested through the second port group 6b shown in FIG. Upper address decoder 32
In the same manner as in normal data reading, all the word lines WL _i connected to the word line WL _i are selected by selecting the word line WL _i based on the designated address and applying a gate voltage, for example. Memory cells C _i1 to C
The _in is activated.

Further, the user can use the terminals 6c ₁ to 6
through c _n, to the memory cell C _i1 not to C _in, for applying a voltage for testing. The test voltage is higher than the drain voltage of the cell transistor Tr _ij when the memory cell C _ij stores low level data,
Moreover, the drain voltage is set to be lower than that when the high level data is stored. Therefore, when the memory cell C _ij stores high-level data, the cell transistor Tr _ij does not turn on and the bit line BL _j
No current flows into the. On the other hand, when the memory cell C _ij stores low level data, the cell transistor Tr _ij is turned on, and the bit line BL _j is connected to the terminal 6
An electric current flows from the outside through c _j .

Therefore, the user, after designating the address, measures the current value flowing into the terminals 6c ₁ to 6c _{n of} the third port group 6c shown in FIG. 2 to obtain the data of the memory cells C _i1 to C _in . It is possible to determine whether is low or high at the same time.

The upper address decoder 32 is caused to sequentially select the word lines WL ₁ to WL _m , and each word line W
By performing the same operation for each L _i , the user can test all the memory cells C _ij included in the memory cell unit 31.

For example, the memory cell section 3 according to the present embodiment.
In 1, 32 bit lines BL and word lines WL
64 are provided. Therefore, as before,
When sequentially testing all the memory cells C _ij , 20
The output data must be verified by specifying the address 48 times. However, in this embodiment, all the bit lines BL ₁ to BL _n are provided for each word line WL _i.
Can be tested at the same time. Therefore, the number of times the address is designated can be reduced to the number of word lines WL, that is, 64 times. As a result, the time required to test all the memory cells C _ij is 1/32 that of the conventional case, which can be greatly reduced.

As described above, the ROM section 3 according to this embodiment has a plurality of word lines WL arranged orthogonally to each other.
And bit line BL, and a memory cell portion 31 having memory cells C _ij arranged at each intersection of both and connected to both lines, a third port group 6c shown in FIG. 2, and each memory cell C _ij . An upper address decoder 3 which simultaneously activates a plurality of memory cells C _ij arranged on the same word line WL in a test mode for testing the contents.
2, and a test switch section 36 including a bit line switch BSW _j interposed between each terminal 6c _j provided in each third port group 6c and each bit line BL _j .

In the above structure, in the test mode, the upper address decoder 32 simultaneously activates, for example, the plurality of memory cells C _ij arranged on the designated word line WL. Furthermore, for example, electrically based on the instructions such as test control signal 2, the bit line switch BSW _j corresponding to each terminal 6c _j becomes conductive, and the memory cell C _ij activated and pin 6c _j Connect to.

[0046] Further, a prescribed voltage is applied from the terminals 6c _j, such as by measuring the current value flowing to the respective terminals 6c _j, determines data memory cell C _ij activated is stored. As a result, the contents of the plurality of memory cells C _ij can be determined at the same time.

Therefore, as in the conventional case, each memory cell C
The test time of the ROM section 3 can be significantly shortened as compared with the case where _ij is sequentially read and tested. Moreover, since the data itself of each memory cell C _ij can be determined, the reliability of the ROM section 3 is not lowered unlike the case where the data on the word line WL is compressed and the content is determined by the signature.

In this embodiment, the third port group 6c
As many terminals 6c as the number of bit lines BL
_j , and each bit line BL _j and each terminal 6c _j is 1
Corresponding to one-to-one, but is not limited to this. When the number of terminals that can be used during the test is smaller than the number of bit lines BL provided in the memory cell section 31 due to the limitation of the number of terminals of the one-chip microcomputer 1, for example, one terminal 6c _j It is also possible to connect a plurality of bit lines BL via a multiplexer or the like and test each bit line BL while sequentially switching the bit lines BL connected to the terminals 6c _j by the multiplexer. Alternatively, a plurality of bit lines B may be connected to one terminal 6c _j via a bit line switch or the like.
It is also possible to test the bit line BL by connecting L and turning on the connected bit lines BL one by one.

When the bit lines BL to be tested are divided into groups as described above, if the number of groups, that is, the number of bit lines BL to be tested at one time is n, the test time can be shortened to 1 / n. In this case, the number of terminals required to test the data is n.
For example, with the same configuration as this embodiment, one terminal 6c _j
When two bit lines BL are connected to each other, the number of terminals required for the third port group 6c is 128. in this case,
At the same time, since the contents of 16 memory cells C _ij can be tested, the test time is shortened to 1/16 as compared with the conventional case.

However, each terminal 6c _j and each bit line B
By making one-to-one correspondence with L _j , a multiplexer is unnecessary. Also, a bit line switch BS whose conduction / interruption is controlled by a test control signal 2 or the like
The test switch unit 36 can be realized by a relatively simple element such as W _j . Further, unlike a semiconductor integrated circuit having a conventional compression circuit, it is not necessary to provide an amplifier that requires a large circuit area for each bit line BL. As a result, the circuit configuration of the 1-chip microcomputer 1 can be simplified and the manufacturing cost can be reduced. Further, since the contents of the memory cells C _ij connected to all the bit lines BL can be tested at the same time, the time required for the test can be further shortened as compared with the case of one-to-many correspondence.

In addition, since the operation of the upper address decoder 32 is the same in the normal use and the test mode, the upper address decoder according to the present embodiment can be provided without adding a special function to the conventional upper address decoder. Decoder 3
2 can be easily realized.

Further, in the present embodiment, the third port group 6c
Although a predetermined test voltage is applied to the terminal 6c _j provided at, the invention is not limited to this. For example, a predetermined current is applied to measure the voltage value generated in each bit line BL _j , and based on this, it is tested whether the data in the memory cell C _ij is low or high. Good. Also,
The contents of the memory cell C _ij can be determined by the difference in the voltage level generated by driving the device connected to each terminal 6c _j by each memory cell C _ij .

[0053] However, by applying a predetermined voltage to the terminals 6c _j, by determining the content of the memory cell C _ij by a current value flowing into the corresponding memory cell C _ij, required for each memory cell C _ij The driving capability can be significantly reduced as compared with the case of driving a device connected to the terminal 6c _j .

In this embodiment, each bit line B
A bit line switch unit 34 is provided between L _j and the amplification unit 35 to select the bit line BL _j connected to the amplification unit 35 from all the bit lines BL during normal data output. In the test mode, the bit line switch unit 34 causes each bit line BL _j
And the amplifier section 35 are cut off, and during normal use, the test switch section 36 cuts off between each bit line BL _j and the terminal 6c _j . As a result, in the normal use and the test mode, each memory cell C _ij
It is connected to only one of the amplifier 35 and the terminal 6c _j . Therefore, even if the memory cell C _ij having the same driving ability as the conventional one is used, the data in the memory cell C _ij can be accessed or tested without any trouble.

On the other hand, like the ROM section 3a shown in FIG.
Instead of the test switch section 36 shown in FIG. 1, a test amplifying section 37 may be provided between the bit line BL _j and the terminal 6c _j provided in the third port group 6c shown in FIG. For convenience of explanation, members having the same functions as those shown in FIG. 1 will be designated by the same reference numerals, and the description thereof will be omitted.

The test amplifying section 37 is an amplifier (amplifying means) provided for each of the bit lines BL ₁ to BL _n.
It is composed of A ₁ to A _n . Each amplifier A
_In the corresponding bit line BL _j , _j can amplify the potential at the connection point between the memory cell unit 31 and the bit line switch unit 34 and output it to the corresponding terminal 6c _j . Note that the input impedance of each amplifier A _j is set sufficiently high so as not to hinder data access during normal use.

Further, in the ROM section 3a according to this embodiment, the test switch section 36 is omitted, so that
The test control signal 2 becomes unnecessary. Therefore, the first port group 6a shown in FIG. 2 does not include a terminal for inputting the test control signal 2.

Also in the above configuration, when testing the ROM section 3a, the lower address decoder 33, based on the instruction of the test control signal 1, is similar to the ROM section 3 described above.
All bit line switches BSW ₁ to BSW _n are turned off. At this time, the amplifier A _{1 to the} amplifier A
_n is activated, and each bit line BL ₁ to B
The signals of L _n are respectively amplified and the terminals 6c ₁ to 6c
_It outputs from _n .

When an address is input in this state, the upper address decoder 32 selects the word line WL _i corresponding to the address and activates the memory cells C _i1 to C _in . As a result, the memory cells C _i1 to C _in
Data is for the terminal 6c ₁ provided in the third port group 6c.
Through 6c _n , these data can be tested simultaneously.

After the measurement is completed for each word line WL _i , the address designation is repeated and the upper address decoder 3
Let 2 sequentially select all word lines WL ₁ to WL _m . As a result, the data of all the memory cells C _ij in the memory cell section 31 can be output from the third port group 6c and tested. As a result, if the number of bit lines BL is n, as in the ROM section 3 shown in FIG. 1, the ROM section 3a according to the present embodiment can reduce the test time to 1 / n.

In addition, the test amplifier 37 amplifies the data in the memory cell C _ij and outputs it from each terminal 6c _j . Therefore, unlike the ROM section 3, the minute current value flowing into the third port group 6c is not measured, and like the other port groups 6 of the one-chip microcomputer 1, the output voltage of the third port group 6c causes the memory The data in the cell part 31 can be tested. As a result, test equipment (not shown) connected to each port group 6 when testing the one-chip microcomputer 1
In, the circuit for testing the data in the memory cell portion 31 and the circuit for testing the data output in the normal state can be shared. Therefore, as compared with the ROM section 3, the ROM section 3
The configuration of the test device used when testing a can be simplified.

Also in this embodiment, the test amplifying section 3 is used.
The number of amplifiers A _j provided in 7 and the number of terminals 6c _j provided in the third port group 6c are equal to the number of bit lines BL.
It is set to the same as the number of _j , but it is not limited to this. For example, the outputs of the plurality of amplifiers A may be connected to one terminal via a selector, and the output of each amplifier A may be output sequentially from the terminals while sequentially switching. In this case, if the maximum value of the number of amplifiers A connected to each terminal is m, the test time can be shortened to m / n as compared with the conventional case. However, the terminal 6c _{j, the} amplifier A _j, and the bit line BL
_{By associating j} with one-to-one, all the memory cells C _ij on the same word line WL can be tested at the same time, the time required for the test can be further reduced, and a selector or the like becomes unnecessary. The configuration of the one-chip microcomputer 1 can be further simplified.

In each of the above embodiments, the case where the present invention is applied to a one-chip microcomputer has been described.
It is not limited to this. For example, a semiconductor integrated circuit including memory cells C _ij arranged in a matrix, such as ROM and RAM, can achieve the same effects as those of the above embodiments. However, like a one-chip microcomputer,
When the present invention is applied to a semiconductor integrated circuit having a sufficient number of terminals as compared with the number of terminals required for controlling a ROM or the like, it is not necessary to increase the number of terminals for testing, so that the effect is particularly great.

[0064]

As described above, the semiconductor integrated circuit according to the invention of claim 1 has a plurality of test terminals and a plurality of test terminals arranged on the same word line in the test mode for testing the contents of each memory cell. Activating means for simultaneously activating the memory cells, and interposed between the test terminals and the bit lines, and the test terminals and the activated memory cells are connected in the test mode. And a switching means for electrically connecting each to the bit line.

Therefore, the contents of multiple memory cells can be tested simultaneously. Further, it is possible to maintain the same test accuracy as that of a semiconductor integrated circuit in which an address is designated and a content is tested for each memory cell. As a result, the time required for the test can be significantly reduced without degrading the quality of the semiconductor integrated circuit.

A semiconductor integrated circuit according to the invention of claim 2 is
As described above, in the structure according to the first aspect of the present invention, the test terminals and the bit lines are in one-to-one correspondence, and the activation means are arranged on the same word line in the test mode. This is a configuration in which all the memory cells that have been activated are activated.

Therefore, the switching means can be easily realized by a switch or the like. As a result, there is an effect that the configuration can be simplified as compared with the conventional semiconductor integrated circuit having the compression circuit. In addition, the time required for the test can be further shortened as compared with the case where a part of the memory cells arranged on the word line is tested.

As described above, the semiconductor integrated circuit testing method according to the third aspect of the present invention is the semiconductor integrated circuit testing method according to the first aspect, wherein the semiconductor integrated circuits are arranged on the same word line in the test mode. A step of simultaneously activating a plurality of the memory cells, a step of conducting the switching means provided in the activated memory cells and the corresponding test terminals, and a predetermined voltage to each of the test terminals. And a step of simultaneously measuring the state of each memory cell connected to each test terminal by measuring the current flowing into each test terminal when a voltage is applied.

According to the above method, the content of the memory cell is tested by the value of the current flowing into each memory cell. Therefore, even if a memory cell with a low driving capability is used as in the prior art, each memory cell and test It is not necessary to provide an amplifier between the terminals. As a result, it is possible to achieve a semiconductor integrated circuit having a short test time and a simple structure.

A semiconductor integrated circuit according to the invention of claim 4 is
As described above, a plurality of test terminals, an activation means for simultaneously activating a plurality of memory cells arranged on the same word line in the test mode for testing the contents of each memory cell, and each of the above test An amplifying means which is interposed between the terminal and each bit line, individually amplifies the signal of the bit line connected to the activated memory cell in the test mode, and outputs the amplified signal to the corresponding test terminal. It is a configuration provided with.

Therefore, as compared with the conventional semiconductor integrated circuit in which an address is specified for each memory cell to test the contents, the time required for the test can be reduced without lowering the accuracy of the test. The effect of being able to greatly shorten is produced.

In addition, since each amplifying means amplifies the signal on the bit line, the contents of the memory cell can be tested in the same manner as the data output during normal use. As a result, as compared with the semiconductor integrated circuit according to the first aspect, there is an effect that the configuration of the test device for testing the semiconductor integrated circuit can be made easier.

[Brief description of drawings]

1 shows an embodiment of the present invention, a ROM
It is a circuit diagram which shows a part.

FIG. 2 is a block diagram showing a main part of a one-chip microcomputer incorporating the ROM section.

FIG. 3 shows another embodiment of the present invention, in which RO
It is a circuit diagram which shows the M section.

FIG. 4 illustrates a conventional example and is a circuit diagram illustrating a ROM unit.

[Explanation of symbols]

1 1-chip microcomputer (semiconductor integrated circuit) 6c Third port group (test terminal) 32 Upper address decoder (activating means) A _{1 to An} amplifier (amplifying means) BL _{1 to} BL _n Bit line BSW _{1 to} BSW _n Bit line switch (switching means) C _{11 to} C _mn memory cell WL _{1 to} WL _m word line

Claims (4)

[Claims] 1. A semiconductor integrated circuit having a plurality of bit lines and a plurality of word lines arranged orthogonal to each other, and a memory cell arranged at each intersection of the both lines and connected to the both lines. Of the test terminals and the activation means for simultaneously activating a plurality of memory cells arranged on the same word line in the test mode for testing the contents of each memory cell, the above-mentioned test terminals and each bit line, Intervenes between
A semiconductor integrated circuit comprising: each of the test terminals in the test mode and a switching means for electrically connecting the bit line to which the activated memory cell is connected. 2. The test terminals and the bit lines correspond to each other on a one-to-one basis, and the activation means activates all the memory cells arranged on the same word line in the test mode. The semiconductor integrated circuit according to claim 1, wherein: 3. A step of simultaneously activating a plurality of the memory cells arranged on the same word line in the test mode, and the test terminal provided corresponding to the activated memory cells. A step of conducting the switching means, a step of simultaneously applying a predetermined voltage to each of the test terminals, and a step of measuring a current flowing into each of the test terminals at the time of applying a voltage, and measuring each memory connected to each of the test terminals. 2. The method for testing a semiconductor integrated circuit according to claim 1, further comprising the step of simultaneously measuring the state of cells. 4. A semiconductor integrated circuit having a plurality of bit lines and a plurality of word lines arranged orthogonally to each other, and memory cells arranged at respective intersections of the both lines and connected to the both lines. Of the test terminals and the activation means for simultaneously activating a plurality of memory cells arranged on the same word line in the test mode for testing the contents of each memory cell, the above-mentioned test terminals and each bit line, Intervenes between
In the test mode, the semiconductor integrated circuit is provided with an amplifying unit that individually amplifies a signal of a bit line to which an activated memory cell is connected and outputs the amplified signal to each corresponding test terminal. .