JPH09251787A - Non-volatile semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten a reading time by providing two pairs of latch circuit group holding data read out from a memory cell and operating them for reading data and outputting data alter-nately. SOLUTION: When an EEPROM of power source voltage 3V is made four values system, threshold values of 0.5-0.8V, 1.5-1.8V, 2.5-2.8V are allotted to data '1', '2', '3' of negative threshold values for data '0'. At the time of read-out, a data circuit 6** tests continuity of a memory cell by applying three kinds of voltage values 1V, 2V, 0V in this order as read-out voltage, and discriminates stored data '0', '1', '2', '3'. Then, the result of sense by read-out voltage is held by using alternately a first and a second latch circuit group RT1**, RT2**, for example, the result is outputted to the outside from the other latch circuit group RT2** while the result is read in one side of latch circuit group RT1**.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrically rewritable non-volatile semiconductor memory device (EEPROM), and more particularly to a multi-value memory EEPROM for storing information of more than 1 bit in one memory cell.

[0002]

2. Description of the Related Art As one of methods for increasing the capacity of an EEPROM, a multi-value storage EEPROM is known in which information of n (n ≧ 3) values is stored in one memory cell. 7-93979, Japanese Patent Application No. 5-31
1732).

A conventional reading method will be described taking four values as an example.

FIG. 34 is a diagram for explaining a conventional read method. FIG. 34 (a) is a diagram showing a threshold distribution of a memory cell, and FIG. 34 (b) is a schematic diagram showing an outline of a conventional read method. Is.

First, the voltage Vt1 between the "1" state and the "2" state is applied to the word line of the memory cell to be read (see FIG. 34).
Is applied. When the memory cell is conductive, the memory cell is "0" or "1", and when the memory cell is non-conductive, the memory cell is "2" or "3".
Next, when Vt2 is applied to the selected word line, it is possible to know whether the memory cell is in the "3" state or the "0" or "1" or "2" state. Finally, when Vt3 is applied to the selected word line, it is possible to know whether the memory cell is in the "0" state, "1", "2" or "3". As a result, the 2-bit information (4 values) stored in the memory cell is read.

FIG. 35 is a diagram for explaining another conventional read method. FIG. 35A is a diagram showing the threshold distribution of the memory cell, and FIG. 35B is a schematic view of another conventional read method. FIG.

First, the voltage Vts1 (see FIG. 35) between the "0" state and the "1" state is applied to the word line of the memory cell to be read. When the memory cell is conductive, the memory cell is "0", and when the memory cell is non-conductive, the memory cell is "1" or "2" or "3". Next, when Vts2 is applied to the selected word line, it is possible to know whether the memory cell is in "0" or "1" or in "2" or "3" state. Finally, when Vts3 is applied to the selected word line, it is possible to know whether the memory cell is in the "3" state or "0" or "1" or "2". As a result, the 2-bit information stored in the memory cell is read.

[0008]

As described above, in the multi-valued memory, the number of times of checking the threshold value of the memory cell is larger than that of the normal memory, that is, the binary memory, and the read speed becomes slow. .

For example, in a 4-level memory, the word line voltage is set to 3
Since the threshold value of the memory cell is checked by changing the number of times, there is a circumstance in which the read time increases to about three times that in the binary memory.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a non-volatile semiconductor memory device which has a memory cell for storing multi-valued data and can shorten the data read time. To provide.

[0011]

In order to achieve the above object, in a nonvolatile semiconductor memory device according to the present invention, a memory cell for storing an electrically rewritable n value (n is a natural number of 3 or more). Includes a memory cell array arranged in a matrix and a data circuit composed of m latch circuits for holding the data read from the memory cells, and at the time of reading, the data is read and held by k latch circuits out of m. The data is the other m-k which constitutes the data circuit.
It is characterized in that the read data is output to the individual latch circuits before being held.

In the "1" state, the threshold voltage of the memory cell is higher than the first threshold voltage region, and in the "2" state, the threshold voltage of the memory cell is lower than the first threshold voltage region. In the large second threshold voltage region, ..., “2n (n is a natural number of 1 or more)” state, the threshold value of the memory cell is the second (2n−
Electrically rewritable 2n belonging to a 2nth threshold voltage region which is larger than the 1) threshold voltage region.
It includes a memory cell array in which memory cells for storing values are arranged in a matrix and a data circuit composed of m latch circuits for holding data read from the memory cells. The "state" and "threshold voltage are almost equal or small" or "n + 1" state and the threshold voltage are almost equal or large. It is characterized in that the read data is output to the other mk latch circuits constituting the circuit before being held.

In addition, a memory cell array in which memory cells for storing electrically rewritable n values (n is a natural number of 3 or more) are arranged in a matrix, and data to be written in the memory cells are held and stored from the memory cells. A data circuit composed of m latch circuits for holding the read data, and data read and held in k latch circuits out of m during reading are used in other m-k
It is characterized in that the read data is output to the individual latch circuits before being held.

Further, a memory cell array in which memory cells for storing electrically rewritable n values (n is a natural number of 3 or more) are arranged in a matrix, and data to be written in the memory cells are held and stored from the memory cells. A first latch circuit, a second latch circuit, ... Mth latch circuit for holding the read data
T composed of a latch circuit (m is a natural number of 2 or more)
Data to be written to the memory cell, first t pieces of data are loaded from the first address to the first latch circuit in each data circuit, and next t pieces of data are written to each data circuit. Loaded into the second latch circuit in
The (i × t + 1) th to tth data from the beginning are loaded into the (i + 1) th (1 ≦ i ≦ m−1; i is a natural number) latch circuit in each data circuit.

Further, a memory cell array in which memory cells for storing electrically rewritable n values (n is a natural number of 3 or more) are arranged in a matrix, and data to be written in the memory cells are held and stored from the memory cells. A first latch circuit, a second latch circuit, ... Mth latch circuit for holding the read data
T composed of a latch circuit (m is a natural number of 2 or more)
Data to be written to the memory cell, first t pieces of data are loaded from the first address to the first latch circuit in each data circuit, and next t pieces of data are written to each data circuit. Loaded into the second latch circuit in
The (i × t + 1) th to tth data from the beginning are loaded into the (i + 1) th (1 ≦ i ≦ m−1; i is a natural number) latch circuit in each data circuit, and out of the m data at the time of reading. The data read and held in the k latch circuits are output to the other mk latch circuits forming the data circuit before the read data is held.

Further, a memory cell array in which memory cells for storing electrically rewritable n values (n is a natural number of 3 or more) are arranged in a matrix, and data to be written in the memory cells are held and stored from the memory cells. A first latch circuit, a second latch circuit, ... Mth latch circuit for holding the read data
T composed of a latch circuit (m is a natural number of 2 or more)
Data to be written to the memory cell, first t pieces of data are loaded from the first address to the first latch circuit in each data circuit, and next t pieces of data are written to each data circuit. Loaded into the second latch circuit in
The (i × t + 1) th to tth data from the beginning are loaded into the (i + 1) th (1 ≦ i ≦ m−1; i is a natural number) latch circuit in each data circuit, and out of the m data at the time of reading. The data read and held in the k latch circuits is output to the other m−k latch circuits forming the data circuit before the read data is held, and then d out of m−k. The data read and held in each latch circuit is
It is characterized in that the read data is output to the other m-k-d latch circuits constituting the data circuit before being held.

Further, a memory cell array in which memory cells storing electrically rewritable n values (n is a natural number of 3 or more) are arranged in a matrix, and data to be written in the memory cells are held and stored from the memory cells. A first latch circuit, a second latch circuit, ... Mth latch circuit for holding the read data
T composed of a latch circuit (m is a natural number of 2 or more)
Data to be written to the memory cell, first t pieces of data are loaded from the first address to the first latch circuit in each data circuit, and next t pieces of data are written to each data circuit. Loaded into the second latch circuit in
The (i × t + 1) -th to t-th data from the beginning are loaded into the (i + 1) -th (1 ≦ i ≦ m−1; i is a natural number) latch circuit in each data circuit, and at the time of reading, first The data read and held by the first latch circuit is output to the other m-1 latch circuits forming the data circuit before the read data is held, and then read and held by the second latch circuit. The data is output to the other m−2 latch circuits forming the data circuit before the read data is held, and the j-th (1 ≦ j ≦ m; j is a natural number)
The data read out and held in the latch circuit is output to the other mj latch circuits forming the data circuit before the read data is held.

Further, a memory cell array in which memory cells for storing electrically rewritable n values (n is a natural number of 3 or more) are arranged in a matrix, and data to be written in the memory cells are held and stored from the memory cells. A first latch circuit, a second latch circuit, ... Mth latch circuit for holding the read data
T composed of a latch circuit (m is a natural number of 2 or more)
Data to be written to the memory cell, first t pieces of data are loaded from the first address to the first latch circuit in each data circuit, and next t pieces of data are written to each data circuit. Loaded into the second latch circuit in
The (i × t + 1) -th to t-th data from the beginning are loaded into the (i + 1) -th (1 ≦ i ≦ m−1; i is a natural number) latch circuit in each data circuit, and at the time of reading, first The data read and held in the m latch circuits are output to the other m-1 latch circuits forming the data circuit before the read data is held, and then the (m-1) th
The data read and held in the latch circuit of No. 2 is output to the other m−2 latch circuits forming the data circuit before the read data is held, and the p-th (1 ≦ p ≦ m; i is a natural number) The data read and held in the latch circuit of No. 1 is output to the other p-1 latch circuits forming the data circuit before the read data is held.

Further, a memory cell array in which memory cells for storing electrically rewritable n values (n is a natural number of 3 or more) are arranged in a matrix, and data to be written in the memory cells are held and stored from the memory cells. A first latch circuit, a second latch circuit, ... Mth latch circuit for holding the read data
T composed of a latch circuit (m is a natural number of 2 or more)
Data to be written to the memory cell, first t pieces of data are loaded from the first address to the first latch circuit in each data circuit, and next t pieces of data are written to each data circuit. Loaded into the second latch circuit in
The (i × t + 1) th to tth data from the beginning are loaded into the (i + 1) th (1 ≦ i ≦ m−1; i is a natural number) latch circuit in each data circuit, and m data in the data circuit are loaded. Data of the latch circuits to which the write data is not input from the outside, the write data based on the data of the f latch circuits from which the write data is not input from the outside is set so that the writing based on the data circuit becomes the shortest. It is characterized by setting.

Further, a memory cell array in which memory cells for storing electrically rewritable n values (n is a natural number of 3 or more) are arranged in a matrix, and data to be written in the memory cells are held and stored from the memory cells. And t data circuits composed of m latch circuits that hold the read data, and the data read and held in the k latch circuits out of the m latch circuits at the time of reading are stored in the other m circuits that form the data circuit. The read data is output to the -k latch circuits before being held, and the data read and held by the d latch circuits among the m-k latch circuits are then output to the other m-constituting data circuits. The read data is output to the kd latch circuits before being held.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

<First Embodiment> FIG. 1 shows a first embodiment of the present invention.
3 is a configuration diagram showing a configuration of a multi-value storage NAND flash memory according to the embodiment of FIG.

As shown in FIG. 1, in the first embodiment,
It has a configuration called an open bit type. The open bit type multi-value storage NAND flash memory is
Row-system circuits 2A and 2B provided for memory cell arrays 1A and 1B configured by arranging memory cells in a matrix, and column-system circuit 3 ^** commonly used in memory cell arrays 1A and 1B, respectively. And have.

The row circuits 2A and 2B receive the address signal output from the address input circuit (address buffer) 4 and select a row of the memory cell array based on the received address signal. A word line drive circuit for driving the word line of the memory cell array based on the output of the. NAND type EEPR
In the case of OM, the word line is a select gate SG (SGA, S
GB) and control gate CG (CGA, CGB). The word line drive circuit can be read as a control gate / select gate drive circuit.

Further, the column system circuit 3 ^** commonly used in each of the memory cell arrays 1A and 1B receives the address signal output from the address buffer 4 and, based on the received address signal, the column of the memory cell array. And a column select line drive circuit that drives a column select line that selects a column of the memory cell array based on the output of the column decoder.

Further, the column system circuit 3 ^** includes a data circuit (bit line control circuit) for temporarily holding the write data to the memory cell and reading the data of the memory cell. There is.

The bit line control circuit uses the data input / output line IO.
Through the data input / output circuit (data input / output buffer)
5 is connected. In addition, the bit line control circuit causes the memory cell of the memory cell array 1A via the bit line BLa and the memory cell array 1B via the bit line BLb.
Of memory cells.

When writing data, the bit line control circuit receives the write data from the data input / output buffer 5 and inputs the received write data to the memory cell. When reading data, the bit line control circuit receives the read data from the memory cell and outputs the received read data to the data input / output buffer 5.

The data input / output buffer 5 performs data input / output control and guides write data input from the outside of the EEPROM to the memory core, and reads data read from the memory core to the outside of the EEPROM. To output.

The write end detection circuit 18 detects whether or not the data write is completed based on the output of the bit line control circuit.

FIG. 2 is a configuration diagram showing the configurations of the memory cell array and column circuits shown in FIG.

As shown in FIG. 2, the memory cell array 1
Memory cells MC are arranged in a matrix in each of A and 1B.

Further, the column system circuit 3 ^** includes m data circuits (bit line control circuits) 6 ^** . The bit line control circuit 6 ^** includes one bit line BLa and one bit line BLa.
It is connected to the book bit line BLb.

FIG. 3 is a diagram showing the threshold distribution of the memory cell transistors in the case of 4-value storage.

When the EEPROM is of a four-value storage type, one memory cell transistor M is provided with four write states. The four write states are distinguished from each other by the threshold voltage of the memory cell transistor M.

As shown in FIG. 3, the power supply voltage VCC is 3V.
In the EEPROM, the state of data “0” is the same as the state after the data is erased, and has a negative threshold value, for example. Further, in the state of data “1”, for example, 0.5V
To have a threshold value between 0.8 V. Data “2”
The state of (1) has a threshold value between 1.5 V and 1.8 V, for example. In the state of data “3”, for example, 2.5
It has a threshold value between V and 2.8V.

When data is read from the memory cell transistor M, three read voltages VCG2R, VCG3R and VCG1R are applied to the control gate CG in this order.

First, the read voltage V is applied to the control gate CG.
Apply CG2R. As a result, depending on whether the memory cell transistor M is “ON” or “OFF”, the stored data is ““ 0 ”,“ 1 ””, “2”,
Whether "3""is detected. Next, read voltage VCG
When 3R is applied, the stored data is "2".
Or "3" is detected, and the read voltage V
When CG1R is applied, whether the data is ““ 0 ””,
Whether "" 1 "" is detected. Read voltage VCG1R,
One example of VCG2R, VCG3R is 0V,
It is 1V and 2V.

Further, the voltages VCG1V and VCG shown in FIG.
2V and VCG3V are called verify read voltages and are read voltages used when checking whether or not data has been sufficiently written (verify operation). The verify read voltage is applied to the control gate CG after writing the data. When the verify read voltage is applied to the control gate CG, the threshold value of the memory cell transistor M is shifted to a range according to the written data depending on whether the memory cell transistor M is “ON” or “OFF”. You can know whether or not. Utilizing this, it is checked whether or not sufficient writing has been performed. One example of the verify read voltages VCG1V, VCG2V, VCG3V is:
They are 0.5V, 1.5V, and 2.5V, respectively.

FIG. 4 is a block diagram of the data circuit shown in FIG.

As shown in FIG. 4, the data circuit 6 ^** has 2
Two latch circuits (first latch circuit and second latch circuit) are included. At the time of writing, 2-bit write data is stored in these two latch circuits. At the time of reading, the read four-valued data is stored in these two latch circuits, and then output to the outside of the chip via IO1 and IO2.

The operation will be described below by taking as an example the case where data of 512 bits (column addresses A0, A1, A2, ... A510, A511) are written and read.

<Write Operation> First, the start address A0
Write data is input to and held in the first latch circuit RT1-0. Then addresses A1, A2,
The write data of A254, A255 is the first latch circuits RT1-1, RT1-2, ..., RT1-254, RT1-255.
Input to and retained. And addresses A256, A
The write data of 257, ..., A510, A511 is the second latch circuits RT2-0, RT2-1, ..., RT2-254, RT.
Input to 2-255 and held. After that, writing is performed in the memory cell in accordance with the 2-bit write data held in the two latch circuits in the data circuit.

If the data is less than 512 bits, the write data is input to the first latch circuit in the data circuit, but the write data is not input to the second latch circuit. In this case, the writing state of the memory cell is "0" state or "1" with a low threshold value.
The data of the second latch circuit may be set so that the state is set.

<Read Operation> FIG. 5 shows the first operation of the present invention.
3A and 3B are diagrams for explaining a read procedure performed by the device according to the embodiment of the present invention. FIG. 6A is a diagram showing a threshold voltage distribution of a memory cell, and FIG. 6B is a schematic diagram showing a read procedure. is there.

As shown in FIG. 5, first, the voltage V between the "1" state and the "2" state is applied to the word line of the memory cell to be read.
Apply p1. When the memory cell is conductive, the memory cell is "0" or "1", and when the memory cell is non-conductive, the memory cell is "2" or "3". Column addresses A0, A1, A2, ..., A254, A
The read data corresponding to 255 is held in the first latch circuit.

Next, when Vp2 is applied to the selected word line,
It can be seen whether the memory cell is in the "3" state, or the "0" or "1" or "2" state. The read data is held in the second latch circuit. During this time,
The data held in the first latch circuit (corresponding to column addresses A0, A1, A2, ..., A254, A255) is IO.
1 to the outside of the chip.

Finally, when Vp3 is applied to the selected word line, the memory cell is in the "0" state or "1".
Alternatively, it can be known whether it is “2” or “3”. As a result, the 2-bit information stored in the memory cell is read. Column address A256, A257, ..., A510, A51
The read data corresponding to 1 is held in the second latch circuit. After outputting the data corresponding to the column addresses A0, A1, A2, ..., A254, A255 held in the first latch circuit to the outside of the chip, the column addresses A256, A257, ... Held in the second latch circuit. , A510, A
The data corresponding to 511 is output to the outside of the chip via IO2.

In this read system, the read data can be output to the outside immediately after the data is first held and held in the first latch circuit, so the read time is much shorter than that of the conventional multi-valued memory. That is, it is almost the same as the case of the binary memory cell. In other words, in the conventional multi-valued memory, the word line voltage was changed three times and sensed, and then the data was output to the outside of the chip. In this embodiment, first, a predetermined read voltage is applied to the word and the memory cell is Since the data is output to the outside of the chip after reading, the reading speed is increased.

FIG. 6 is a diagram for explaining another read procedure performed by the device according to the first embodiment of the present invention.
(A) is a diagram showing a threshold distribution of memory cells,
FIG. 6B is a schematic diagram showing the outline of another reading procedure.

As shown in FIG. 6, first, the voltage V between the "0" state and the "1" state is applied to the word line of the memory cell to be read.
Apply ps1. When the memory cell is conductive, the memory cell is "0", and when the memory cell is non-conductive, the memory cell is "1" or "2" or "3". The read data is held in the second latch circuit.

Next, when Vps2 is applied to the selected word line, it is possible to know whether the memory cell is in the "0" or "1" state or the "2" or "3" state. The read data corresponding to the column addresses A0, A1, A2, ..., A254, A255 are held in the first latch circuit. After this, the data held in the first latch circuit (column addresses A0, A1, A2, ..., A254, A25
(Corresponding to 5) is output to the outside of the chip via IO1.

Finally, when Vps3 is applied to the selected word line, the memory cell is in the "3" state or "0".
Alternatively, it can be known whether it is “1” or “2”. As a result, the 2-bit information stored in the memory cell is read. Column address A256, A257, ..., A510, A51
The read data corresponding to 1 is held in the second latch circuit. After outputting the data corresponding to the column addresses A0, A1, A2, ..., A254, A255 held in the first latch circuit to the outside of the chip, the column addresses A256, A257, ... Held in the second latch circuit. , A510, A
The data corresponding to 511 is output to the outside of the chip via IO2.

As described above, in the device according to the first embodiment, when the multi-valued information stored in the memory cell is read out,
After the read data of the first latch circuit in the data circuit is determined, the data of the first latch circuit can be output to the outside of the chip at the same time as the data is read to the second latch circuit. As a result, the reading speed becomes high.

<Second Embodiment> Next, a second embodiment of the present invention will be described.

The configuration of the multi-valued NAND flash memory of the second embodiment is similar to that of the first embodiment, and has the configuration shown in FIG. 1, for example. The relationship between the write state of the memory cell and the threshold value is as shown in FIG.

FIG. 7 shows a NAND according to the second embodiment.
2 is a circuit diagram of a data circuit included in the flash memory. The data circuit shown in FIG. 7 is configured with four-value storage as an example.

As shown in FIG. 7, the data circuit 6 ^** has n
Channel MOS transistors Qn21, Qn22, Qn
23 and p-channel MOS transistors Qp9, Qp1
0, Qp11 and a flip-flop F
F1 and n-channel MOS transistors Qn29 and Qn
30, Qn31 and p-channel MOS transistor Qp1
6, Qp17, Qp18, and FF2, to which write / read data is latched. These also operate as sense amplifiers.

The flip-flops FF1 and FF2 are
"Whether writing" 0 "or writing" 1 ",
"2" write or "3" write "is latched as write data information, and whether the memory cell holds" 0 "information or" 1 "information, "Whether information" 2 "is held or information" 3 "is held" is sensed and latched as read data information.

The data input / output lines IOA and IOB and the flip-flop FF1 are connected to the n-channel MOS transistor Q.
It is connected via n28 and Qn27. The data input / output lines IOC, IOD and the flip-flop FF2 are connected via n-channel MOS transistors Qn35, Qn36. Data input / output lines IOA, IOB, IOC, I
The OD is also connected to the data input / output buffer 5 shown in FIG. n-channel MOS transistors Qn27, Q
The gate of n28 is connected to the output of the column address decoder composed of the NAND logic circuit G3 and the inverter I5. The read data held in the flip-flop FF1 is I when the CENB1 is activated.
It is output to OA and IOB. The gates of the n-channel MOS transistors Qn35 and Qn36 are connected to the output of the column address decoder composed of the NAND logic circuit G2 and the inverter I4. Flip flop FF2
The read data held at is output to IOC and IOD when CENB2 is activated.

N-channel MOS transistor Qn26,
Qn34 is a flip-flop FF1 and FF, respectively.
The signals ECH1 and ECH2 are equalized to "H". n-channel MOS transistors Qn24, Qn
32 controls the connection between the flip-flops FF1 and FF2 and the MOS capacitor Qd1. The n-channel MOS transistors Qn25 and Qn33 control the connection between the flip-flops FF1 and FF2 and the MOS capacitor Qd2.

P-channel MOS transistor Qp12
The circuit composed of C and Qp13C has an activation signal VRF.
The YBAC changes the gate voltage of the MOS capacitor Qd1 according to the data of the flip-flop FF1. p-channel MOS transistors Qp14C, Qp
The circuit composed of 15C has an activation signal VRFYBBC.
Thus, the gate voltage of the MOS capacitor Qd2 is changed according to the data of the flip-flop FF1.
p-channel MOS transistors Qp12C, Qp19
The circuit composed of C and Qp20C has an activation signal VRF.
The YBA2C changes the gate voltage of the MOS capacitor Qd1 according to the data of the flip-flops FF1 and FF2. p channel MOS transistor Q
The circuit composed of p14C, Qp21C, and Qp22C is flipped by the activation signal VRFYBB2C.
Depending on the data of the flops FF1 and FF2, the MOS
The gate voltage of the capacitor Qd2 is changed. The circuit including the n-channel MOS transistors Qn1C and Qn2C changes the gate voltage of the MOS capacitor Qd1 according to the data of the flip-flop FF2 by the activation signal VRFYBA1C. The circuit composed of the n-channel MOS transistors Qn3C and Qn4C changes the gate voltage of the MOS capacitor Qd2 according to the data of the flip-flop FF2 by the activation signal VRFYBB1C.

The MOS capacitors Qd1 and Qd2 are composed of depletion type n-channel MOS transistors and are sufficiently smaller than the bit line capacitance. n channel M
The OS transistor Qn37 is set to M by the signal PREA.
The OS capacitor Qd1 is charged to the voltage VA. The n-channel MOS transistor Qn38 charges the MOS capacitor Qd2 to the voltage VB by the signal PREB. The n-channel MOS transistors Qn39 and Qn40 control the connection between the data circuit 3 and the bit lines BLa and BLb by the signals BLCA and BLCB, respectively. The circuit composed of the n-channel MOS transistors Qn37 and Qn38 also serves as the bit line voltage control circuit.

Next, the EEPROM configured as described above
Will be described with reference to a timing chart. Hereinafter, a case where the control gate CG2A is selected will be described.

<Read Operation> FIG. 8 is an operation waveform diagram showing a read operation.

As shown in FIG. 8, first, at time t1RC,
The voltages VA and VB are 1.8 V and 1.5 V, respectively, and the bit lines BLa and BLb are 1.8 V and 1.
It becomes 5V. The signals BLCA and BLCB become "L", the bit line BLa is disconnected from the MOS capacitor Qd1, the bit line BLb is disconnected from the MOS capacitor Qd2, and the bit lines BLa and BLb are floated. Signal PR
EA and PREB become "L", and MOS capacitor Q
The nodes N1 and N2 which are the gate electrodes of d1 and Qd2 are in a floating state. Subsequently, at time t2RC, the selected control gate CG2A of the block selected by the control gate / selection gate drive circuit is 0V, the non-selection control gates CG1A, CG3A, CG4A and the selection gate SG1.
A and SG2A are set to VCC. If the threshold value of the selected memory cell is 0V or less, the bit line voltage will be lower than 1.5V. If the threshold value of the selected memory cell is 0 V or more, the bit line voltage remains at 1.8 V. After that, at time t3RC, the signals BLCA and BLCB change to "H", and the data on the bit line is transferred to the MOS capacitors Qd1 and Qd2. After that, the signals BLCA and BLCB are again set to "L", and the bit line BLa and the MOS capacitor Q
The d1, bit line BLb and the MOS capacitor Qd2 are separated. Signals SAN1 and SAP1 are "L",
The signal becomes "H", the flip-flop FF1 is inactivated, and the signal ECH1 becomes "H" and equalized.
After that, the signals RV1A and RV1B become "H". At time t4RC, the signals SAN1 and SAP1 again become "H" and "L", respectively, so that the voltage of the node N1 is sensed and latched. With this, "whether the data of the memory cell is" 0 ", or" 1 "or" 2 "or" 3 ""
Is sensed by flip-flop FF1 and that information is latched.

Next, the selected control gate is set to 1V. If the threshold of the selected memory cell is less than 1V,
The bit line voltage will be lower than 1.5V. If the threshold voltage of the selected memory cell is 1 V or higher, the bit line voltage is 1.
It remains at 8V. Signals PREA, PRE at time t5RC
B becomes "H", and MOS capacitors Qd1 and Qd2
The gate electrodes of the nodes N1 and N2 are 1.8
It becomes V and 1.5V. Signals PREA and PREB are "L"
Then, the nodes N1 and N2, which are the gate electrodes of the MOS capacitors Qd1 and Qd2, are brought into a floating state. After that, the signals BLCA and BLCB are set to "H" at time t6RC. The signals BLCA and BLCB are again set to "L", and the bit line BLa and the MOS capacitor Q
The d1, bit line BLb and the MOS capacitor Qd2 are separated. The signals SAN2 and SAP2 are "L",
The signal becomes "H", the flip-flop FF2 is inactivated, and the signal ECH2 becomes "H" and is equalized.
After that, the signals RV2A and RV2B become "H". At time t7RC, the signals SAN2 and SAP2 again become "H" and "L", respectively, so that the voltage of the node N1 is sensed and latched. In this way, "the data of the memory cell is" 0 "or" 1 ", or" 2 "or" 3 "
Is sensed by the flip-flop FF2,
That information is latched.

FIG. 9 is a diagram showing read data sensed and latched by the flip-flops FF1 and FF2 at time t7RC. At this time, the potentials of the nodes N3C and N5C of the flip-flops FF1 and FF2 are as shown in FIG.

The data held in the flip-flop FF2 is output to the outside of the chip by activating CENB2 at time tCB1.

Finally, whether the data written in the memory cell is "2" or "3" is sensed. The selected control gate is brought to 2V. If the threshold of the selected memory cell is less than 2V, the bit line voltage will be less than 1.5V. If the threshold voltage of the selected memory cell is 2V or higher, the bit line voltage remains 1.8V. Time t8R
When the signals PREA and PREB become "H" at C, the MOS
Node N, which is the gate electrode of capacitors Qd1 and Qd2
1 and N2 are 1.8V and 1.5V, respectively. Signal P
REA and PREB are set to "L", and the nodes N1 and N2 which are the gate electrodes of the MOS capacitors Qd1 and Qd2 are brought into a floating state. After that, the signals BLCA and BLCB are set to "H" at time t10RC. Then again
The signals BLCA and BLCB become "L", and the bit line B
La and MOS capacitor Qd1, bit line BLb and MO
The S capacitor Qd2 is disconnected. Before sensing the data of MOS capacitor, VRFYB at time t11RC
A2C becomes 0V. As can be seen from FIG. 9, node N
5C is "Low level" and node N3C is "High level"
l "(that is, the node N4C becomes" Low level ") only in the case of" 1 "data. Therefore, only in the case of" 1 "data, the p-channel MOS transistors Qp12C, Qp are provided.
p19C and Qp20C are turned on, and the node N1 becomes VCC. After that, the signals SAN1 and SAP1 become "L" and "H", respectively, and the flip-flop FF1 is deactivated, and the signal ECH1 becomes "H" and is equalized. After that, the signals RV1A and RV1B become "H". At time t12RC, the signals SAN1 and SAP1 again become "H" and "L", respectively, so that the voltage of the node N1 is sensed and latched. Thus, "whether the data in the memory cell is" 2 "or" 3 "" is sensed by the flip-flop FF1 and the information is latched.

After the data held in the flip-flop FF2 is output to the outside, the data held in the flip-flop FF1 is output to the outside of the chip by activating CENB1 at time tCB2.

FIG. 10 shows flip-flops FF1 and F.
FIG. 9 is a diagram showing read data which F2 senses and latches.

As a result of the above read operation, 4-level data is latched in the flip-flops FF1 and FF2 as shown in FIG.

The threshold distribution of each data in the figure is a number.

Data “0” ... Threshold value: 0V or less Data “1” ... Threshold value 0.5V or more and 0.8V or less Data “2” ... Threshold value 1.5V or more and 1.8V or less Data “ 3 "... Threshold value 2.5V or more and 2.8V or less During reading, the signals VRFYBAC and VRFYBBC are" H ", and the signals VRFYBA1C and VRFYBB1C are" L ". The voltage Vs is 0V.

Data stored in memory cells, threshold values, data input / output lines IOA, IOB, IOC, IOD
The relationship of the levels output after the reading is as shown in FIG.

<Write Operation> First, write data is loaded into the flip-flops FF1 and FF2. After that, "1" data, "2" data and "3" data are written almost simultaneously. And "1" data, "2"
Verify read is performed to check whether the data and "3" data have been sufficiently written, and if there is a memory cell that has not been sufficiently written, rewriting is performed. Writing is completed when the write completion detection circuit detects that all memory cells are sufficiently programmed.

The program will be described below, and then the verify read will be described.

(1) Program Before the writing operation, the input data is converted by the data input / output buffer 5 and input to the data circuit 3.

FIG. 11 is a diagram showing write data input to the data circuit 6 ^** and latched by the flip-flop circuits FF1 and FF2. The relationship between the 4-value data and the data input / output lines IOA, IOB, IOC, and IOD is as shown in FIG.

At that time, as in the first embodiment, assuming that there are 256 data circuits 6 ^** (that is, assuming that the page length is 256), the first two input data are input.
The 56-bit write data is the column activation signal CE.
When NB1 is "H", flip through IOA and IOB.
It is input to the flop FF1. Then, the write data of 256 bits or more input from the outside is input to the flip-flop FF2 via the IOC and IOD when the column activation signal CENB2 is “H”.

As can be seen from FIGS. 10 and 11, IO
Input to the flip-flop 1 via A and IOB,
Regarding the written data, the read data is output to the flip-flop 2 at the time of reading, and then,
It is output to the outside of the chip via IOC and IOD. That is, as for the data to which the write data is input from the IOA, the data input / output buffer may control the data so that the read data is output from the IOD. Similarly, I
Regarding the data to which the write data is input from the OB, the data input / output buffer may control the data so that the IOC outputs the read data.

On the other hand, flip through the IOC and IOD.
The data input to the flop 2 and written is
At the time of reading, read data is output to the flip-flop 1, and then output to the outside of the chip via the IOC and IOD. That is, for the data to which the write data is input from the IOC, the data control may be performed by the data input / output buffer so that the read data is output from the IOB. Similarly, for the data to which the write data is input from the IOD, the data input / output buffer may control the data so that the read data is output from the IOA.

FIG. 12 is an operation waveform diagram showing a write operation.

As shown in FIG. 12, the voltage VA is applied at time t1s.
Becomes the bit line write control voltage of 1 V, and the bit line B
La is set to 1V. n channel MOS transistor Q
When the voltage drop corresponding to the threshold value of n39 becomes a problem,
The signal BLCA may be boosted. Then, the signal PRE becomes "L" and the bit line is floated. Next, at time t2s, the signal RV2A is set to 1.5V. As a result, since the data "1" or "3" is held, the bit line control voltage 0V is applied to the bit line. n
Set the threshold of the channel MOS transistor Qn32 to 1V
Then, the n-channel MOS transistor Qn32 is "OFF" when writing "0" or "2", and is "ON" when writing "1" or "3". After that, at time t3s, VRFYBAC becomes 0V, and the bit line write control voltage VCC is output to the bit line from the data circuit holding the data "0" or the data "1".

Then, at time t4s, VRFYBA2C becomes 0.
The voltage V becomes V, and the data line holding the data “1” outputs the bit line “1” write potential 2V to the bit line via V1.

As a result, the bit line for writing "0" becomes VCC, the bit line for writing "1" becomes 2V, the bit line for writing "2" becomes 1V, and the bit line for writing "3" becomes 0V.

At time t1s, the select gate SG1 of the block selected by the control gate / select gate drive circuit is selected.
A, the control gates CG1A to CG4A become VCC. The selection gate SG2A is at 0V. Next, the selected control gate CG2A becomes the high voltage VPP (for example, 20V), and the non-selected control gates CG1A, CG3A, and CG4A become VM (for example, 10V). In the memory cell corresponding to the data circuit holding the data “3”, electrons are injected into the floating gate due to the potential difference between the channel potential of 0 V and VPP of the control gate, and the threshold value rises. In the memory cell corresponding to the data circuit holding the data “2”,
Due to the potential difference between the channel potential of 1 V and the VPP of the control gate, electrons are injected into the floating gate and the threshold value rises. In the memory cell corresponding to the data circuit holding the data “1”, electrons are injected into the floating gate and the threshold value rises due to the potential difference between the channel potential of 2V and VPP of the control gate. The channel potential in the case of writing "2" is set to 1 V, and the channel potential in the case of writing "1" is set to 2 V because the injection amount of electrons is "3" when writing data, when "2" writing is set to "2". This is to reduce the number in the order of 1 ”writing. In the memory cell corresponding to the data circuit in which the data “0” is held, since the potential difference between the channel potential and VPP of the control gate is small, electrons are not effectively injected into the floating gate. Therefore, the threshold value of the memory cell does not change. During writing operation, signal S
AN1, SAN2, PREB, BLCB are "H", signals SAP1, SAP2, VRFYBA1C, RV1A, R
V1B, RV2B, ECH1 and ECH2 are "L", and the voltage VB is 0V.

(2) Verify Read After the write operation, it is detected whether or not the write is sufficiently performed (write verify). If the desired threshold value is reached, the data in the data circuit is changed to "0".
If the desired threshold value has not been reached, the data in the data circuit is held and the write operation is performed again. The write operation and the write verify are repeated until all the memory cells for "1" write, the memory cells for "2" write and the memory cells for "3" write reach the desired threshold value.

13 and 14 are operation waveform diagrams showing the verify operation.

The write verify operation will be described below with reference to FIGS. 13 and 14.

First, it is detected whether the memory cell in which "1" is written has reached a predetermined threshold value.

First, at time t1yc, the voltages VA and VB become 1.8V and 1.5V, respectively, and the bit lines BLa and
BLb becomes 1.8V and 1.5V, respectively. Signal BL
CA and BLCB become "L", and bit lines BLa and M
The OS capacitor Qd1 and the bit line BLb are disconnected from the MOS capacitor Qd2, and the bit lines BLa and BLb become floating. Signals PREA and PREB are "L"
Then, the nodes N1 and N2, which are the gate electrodes of the MOS capacitors Qd1 and Qd2, are brought into a floating state. Then, at time t2yc, the selected control gate CG2A of the block selected by the control gate / selection gate drive circuit is 0.5V, and the non-selected control gates CG1A, C are selected.
G3A, CG4A and select gates SG1A, SG2A are V
It will be CC. The threshold value of the selected memory cell is 0.
Below 5V, the bit line voltage will be below 1.5V.
If the threshold value of the selected memory cell is 0.5 V or higher,
The bit line voltage remains 1.8V. At time t3yc,
The signals BLCA and BLCB are set to "H", and the potentials of the bit lines are transferred to N1 and N2. After that, the signal BLCA,
BLCB becomes "L", and the bit line BLa and the MOS capacitor Qd1, the bit line BLb and the MOS capacitor Q.
d2 is separated. After that, RV1A becomes 1.5V at time t4yc, and the node N1 is discharged to 0V in the case of "2" write and "3" write. When the signal VRFYBA1C becomes "H" at time t5yc,
In the data circuit in which "0" or "2" write data is held, the n-channel MOS transistor Qn2 is "ON" and the node N1 is at VCC. As a result, the node N1 becomes VCC when writing "0" or "2", and becomes 0 V when writing "3".

The signals SAN2 and SAP2 are set to "L" and "H", respectively, to inactivate the flip-flop FF2, and the signal ECH2 is set to "H" and equalized. After that, the signals RV2A and RV2B become "H". Again, the signals SAN2 and SAP2 are "H",
When it becomes "L", the voltage of the node N1 is sensed and latched at time t6yc. Thus, only the data circuit holding the "1" write data detects whether or not the data of the corresponding memory cell is sufficiently in the "1" write state. If the data in the memory cell is "1", the write data is changed to "0" by sensing and latching the voltage of the node N1 by the flip-flop FF2. If the data in the memory cell is not "1", the write data is held at "1" by sensing and latching the voltage of the node N2 by the flip-flop FF1. The write data of the data circuit holding the "0", "2" or "3" write data is not changed.

Next, the selected control gate is set to 1.5V. If the threshold of the selected memory cell is less than 1.5V, the bit line voltage will be less than 1.5V. If the threshold value of the selected memory cell is 1.5 V or more, the bit line voltage remains at 1.8 V. PRE at time t7yc
A and PREB are set to VCC, and the nodes N1 and N2 are 1.8.
Floating after V and 1.5V. Thereafter, at time t8yc, the signals BLCA and BLCB are set to "H", and the potentials of the bit lines are transferred to N1 and N2. After that, the signals BLCA and BLCB become "L", and the bit line BLa and the MOS capacitor Qd1 are separated from the bit line BLb and the MOS capacitor Qd2. After this time t
At 9yc, the signal RV2A is set to 1.5V, which is lower than VCC, for example. When the threshold value of the n-channel MOS transistor Qn32 is 1 V, the n-channel MOS transistor Qn is used in the data circuit holding the "3" write data.
32 is “ON”, and the node N1 becomes 0V. In the data circuit holding the "2" write data, when the memory cell is sufficiently written "2", the n-channel MOS transistor Qn 32 is "OFF" and the node N1 is kept at 1.5V or higher. Be drunk When the "2" write is insufficient, the voltage at the node N1 is 1.5 V or less. Time t
When the signal VRFYBAC becomes "L" at 10yc, the p-channel MOS transistor Qp13 becomes "ON" in the data circuit in which "0" or "1" write data is held.
Therefore, the node N1 becomes VCC.

The signals SAN1 and SAP1 become "L" and "H", respectively, to inactivate the flip-flop FF1, and the signal ECH1 becomes "H" and is equalized. After that, the signals RV1A and RV1B become "H". Again, the signals SAN1 and SAP1 are "H",
When it becomes "L", the voltage of the node N1 is sensed and latched at time t11yc. With this, only the data circuit holding the "2" write data detects whether or not the data of the corresponding memory cell is sufficiently in the "2" write state. If the data in the memory cell is "2", the write data is changed to "0" by sensing and latching the voltage of the node N1 by the flip-flop FF1. If the data of the memory cell is not “2”, the write data is held at “2” by sensing and latching the voltage of the node N1 with the flip-flop FF1. The write data of the data circuit holding the "0", "1" or "3" write data is not changed.

Next, the selected control gate is brought to 2.5V. If the threshold of the selected memory cell is less than 2.5V, the bit line voltage will be less than 1.5V. If the threshold value of the selected memory cell is 2.5 V or more, the bit line voltage remains at 1.8 V. After this, at time t12yc,
The signals BLCA and BLCB are set to "H", and the potentials of the bit lines are transferred to N1 and N2. Again, the signals BLCA, B
LCB becomes "L", and the bit line BLa and the MOS capacitor Qd1 and the bit line BLb and the MOS capacitor Qd.
2 is separated. After this, at time t13yc, the signal VRFY
When BAC becomes “L”, in the data circuit in which “0” or “1” write data is held and in the data circuit in which “2” write is sufficiently performed, p channel MO
The S transistor Qp13 is "ON", and the node N1 becomes VCC. The signals SAN1 and SAP1 become "L" and "H", respectively, and the flip-flop FF1 is inactivated, and the signal ECH1 becomes "H" and is equalized. After that, the signals RV1A and RV1B become "H". After that, at time t14yc, the signals SAN1 and SAP1 become "H" and "L", respectively, so that the voltage of the node N1 is sensed and latched.

After this, as shown in FIG. 14, conversion of write data is further performed. At time t15yc, signal B
LCA and BLCB are set to "H", and the potential of the bit line is N
1 is transferred to N2. Again, the signals BLCA, BLCB
Becomes "L", and the bit line BLa is disconnected from the MOS capacitor Qd1, and the bit line BLb is disconnected from the MOS capacitor Qd2. After this, at time t16yc, the signal VRFYBA1
When C becomes "H", in the data circuit holding the "0" or "2" write data and the data circuit sufficiently writing "1", the n-channel MOS transistor Q
Since n2C is "ON", the node N1 becomes VCC. The signals SAN2 and SAP2 are set to "L" and "H", respectively, and the flip-flop FF2 is deactivated, and the signal EC
H2 becomes "H" and is equalized. After that, the signals RV2A and RV2B become "H". After that, time t17yc
The signals SAN2 and SAP2 are "H" and "L", respectively.
As a result, the voltage of the node N1 is sensed and latched.

In the second embodiment, VRFYBA1C is set to VCC at time t16yc so that the node N1 of the MOS capacitor Qd1 in the case where "0" write, "2" write and "1" write are sufficient is changed to the node. Charging is performed so as to be higher than the potential of N2 (1.5 V). For example, RV2B may be set to 1.5V at t16yc. In this case, if "0" write, "2" write, or "1" write is sufficient, the node N6C becomes 0.
Since it is V, the n-channel MOS transistor Qn33 is turned on and N2 becomes 0V.

On the other hand, insufficient writing of "1" or "3"
In the case of writing, since the node N6C is VCC and N2 is 1.5V, the n-channel MOS transistor Qn33 is turned off and N2 is kept at 1.5V. VR at time t16yc
When the FYBA1C is set to VCC, the “0” write, the “2” write, and the “1” write insufficiency may be charged to N1 as long as it is higher than the potential (0V) of N2. A voltage as low as 0.5 V is sufficient.

As described above, only the data circuit holding the "3" write data detects whether or not the data in the corresponding memory cell is sufficiently in the "3" write state. If the data in the memory cell is "3", the write data is changed to "0" by sensing and latching the voltage of the node N1 by the flip-flops FF1 and FF2. If the data in the memory cell is not "3", the write data is held at "3" by sensing and latching the voltage of the node N1 by the flip-flops FF1 and FF2. The write data of the data circuit holding the "0" or "1" or "2" write data is not changed.

During write verify, signal VRFYBB
C is "H", signal VRFYBB1C is "L", voltage Vs
Is 0V.

When all the selected memory cells have reached the desired threshold value, the data of the data circuit becomes "0" data. That is, when the writing is completed, the node N4
C and N6C become "L". By detecting this, it is possible to know whether or not all the selected memory cells have reached the desired threshold value. The end of writing is detected, for example, as shown in FIG.
C and Qn6C may be used. After the verify read, VRTC is first precharged to VCC, for example. If there is even one memory cell in which writing is insufficient, at least one of the nodes N4C or N6C of the data circuit is "H", so at least one of the n-channel MOS transistors Qn5C and Qn6C is turned on, and VRTC is precharged Lowers. When all memory cells are written to enough, the data circuit 6 ^** -0,6 ^** -1, ..., 6 ^**
The nodes N4C and N6C of -m-1, 6 ^**- m become "L".
As a result, since the n-channel MOS transistors Qn5C and Qn6C in all the data circuits are turned off, VRT
C maintains the precharge potential.

Although the multi-value storage NAND flash memory according to the second embodiment of the present invention has been described above, various operations such as verify reading, writing, and reading are possible.

FIG. 15 is an operation waveform diagram showing another verify operation.

For example, the verify read may be operated as shown in the operation waveform diagram of FIG.

In the verify read shown in FIG. 15,
The operation up to time t12yc is similar to the verify read in FIG. 14, but the operation after time t12yc is different.

As shown in FIG. 15, signal B is output at time t12yc.
LCA and BLCB are set to "H", and the potential of the bit line is N
1 is transferred to N2. Memory cell threshold is 2.5
If V or more, the bit line BLa is 1.5 V or more,
If the voltage is 2.5 V or less, the bit line BLb is 1.5 V
It is as follows. After that, the signals BLCA and BLCB are "L".
Then, the bit line BLa and the MOS capacitor Qd1,
The bit line BLb and the MOS capacitor Qd2 are separated. After that, when the signal VRFYBA1C becomes "H" at time t13zc, the n-channel MOS transistor Qn2 turns "ON" in the data circuit holding the "0" or "2" write data and the data circuit sufficiently writing "1". , And the node N1 becomes 1.5V or higher. The signals SAN2 and SAP2 are set to "L" and "H", respectively, and the flip-flop FF2 is deactivated, and the signal EC
H2 becomes "H" and is equalized. After that, the signals RV2A and RV2B become "H". After that, time t14zc
The signals SAN2 and SAP2 are "H" and "L", respectively.
As a result, the voltage of the node N1 is sensed and latched.

After this, as shown in FIG. 15, conversion of write data is further performed. At time t15zc, signal B
LCA and BLCB are set to "H", and the potential of the bit line is N
1 is transferred to N2. Again, the signals BLCA, BLCB
Becomes "L", and the bit line BLa is disconnected from the MOS capacitor Qd1, and the bit line BLb is disconnected from the MOS capacitor Qd2. After this, at time t16zc, the signal VRFYBAC
Becomes "L", in the data circuit in which "0" or "1" write data is held and in the data circuit in which "2" write is sufficiently performed, p channel MOS
The transistor Qp13 is "ON" and the node N1 is at V
CC. The signals SAN1 and SAP1 become "L" and "H", respectively, and the flip-flop FF1 is inactivated, and the signal ECH1 becomes "H" and is equalized. After that, the signals RV1A and RV1B become "H". After that, at time t17zc, the signals SAN1 and SAP1 become "H" and "L", respectively, so that the voltage of the node N1 is sensed and latched.

Further, the structure of the data circuit is not limited to the circuit structure shown in FIG. 7, but may be another circuit structure.

16 and 17 are other circuit diagrams of the data circuit, respectively.

The data circuit shown in FIG. 16 is VRFYBA.
The operation timings of 1C and VRFYBB1C are the same as those of the data circuit of FIG. 7 (operation waveform diagram; FIG. 8, FIG. 12, FIG. 13, FIG. 14, FIG. 15), VC
C may be 0V and 0V may be VCC. In addition, VRFY
BAC, VRFYBBC, VRFYBA2C, VRFY
The timing of BB2C is the same as when the data circuit of FIG. 7 is used.

In addition, the data circuit shown in FIG.
YBAC, VRFYBBC, VRFYBA2C, VRF
The operation timing of YBB2C is the same as that of the data circuit of FIG. 7 (operation waveform diagram; FIG. 8,
(FIG. 12, FIG. 13, FIG. 14, FIG. 15), VCC is 0V, 0
V may be set to VCC. In addition, VRFYBA1C, V
The timing of RFYBB1C is the same as when the data circuit of FIG. 7 is used. <Third Embodiment> Next, a third embodiment of the present invention will be described.

In the present invention, the data circuit is, for example, the first
In the case of the second latch circuit and the second latch circuit, the second latch circuit reads the second latch circuit, and the second latch circuit reads the second latch circuit while the second latch circuit reads the second latch circuit.
The data is output to the outside of the chip from the latch circuit. That is, when reading out the 2-bit data stored in the 4-level memory cell, if one of the 1-bit data is read out, the fixed 1-bit data is immediately read even before the other 1-bit data is read out. The output is speeded up by outputting to the outside. Therefore, the reading method is highly optional in addition to the second embodiment.

Here, another embodiment will be described in the case where the data circuit of FIG. 7 is used.

FIG. 18 is an operation waveform diagram for explaining the reading method according to the third embodiment of the present invention.

As shown in FIG. 18, first, at time tw1, the voltages VA and VB are 1.8 V and 1.5 V, respectively.
Bit lines BLa and BLb are 1.8V and 1.5V, respectively
become. Next, the signals PREA and PREB become "L", and the bit lines BLa and BLb become floating.
Then, at time tw2, the selected control gate CG of the block selected by the control gate / selection gate drive circuit
2A is 1V, non-selection control gates CG1A, CG3A, C
G4A and select gates SG1A and SG2A are set to VCC. If the threshold of the selected memory cell is less than 1V,
The bit line voltage will be lower than 1.5V. If the threshold voltage of the selected memory cell is 1 V or higher, the bit line voltage is 1.
It remains at 8V. After that, the signals SAN2 and SAP2 become "L" and "H", respectively, and the flip-flop F
F2 is inactivated, the signal ECH2 becomes "H" and equalized. After this, at time t3w, the signals RV2A, R
V2B becomes "H". Signal SAN again at time tw4
2 and SAP2 become "H" and "L" respectively,
The voltage of the node N1 is sensed and latched. with this,
"Whether the data in the memory cell is" 0 "or" 1 "or" 2 "or" 3 "" is flip-flop FF2.
Sensed and the information is latched.

The data held in the flip-flop FF2 is output to the outside of the chip by activating CENB2 at time tw5.

Next, it is determined whether the threshold voltage of the memory cell is 0 V or higher or 0 V or lower. At time tw5, the bit line BLa is set to 1.8 V, and the dummy bit line BLb is set to 1.
It is precharged to 5V and then left floating. After that, the control gate selected at time tw6 is set to 0V. If the threshold value of the selected memory cell is 0V or less, the bit line voltage will be lower than 1.5V. If the threshold value of the selected memory cell is 0 V or more, the bit line voltage remains at 1.8 V. The signals SAN1 and SAP1 become "L" and "H", respectively, and the flip-flop FF1.
Are deactivated and the signal ECH1 becomes "H" and is equalized. After this, at time tw7, the signals RV1A and RV1
B becomes "H". Signals SAN1 and SAP1 at time tw8
Becomes "H" and "L" respectively, the voltage of the node N1 is sensed and latched. Then, "whether the data in the memory cell is" 0 ", or" 1 "or" 2 "or" 3 "" is sensed by the flip-flop FF1 and the information is latched. The potentials of the nodes N3C and N5C of the flip-flops FF1 and FF2 at this time are as shown in FIG.

Finally, the data written in the memory cell is "0", "1", "2", or "3".
Is it sensed? At time tw9, the bit line BLa is 1.
The dummy bit line BLb is precharged to 8V at 1.5V, and then floated. After that, the control gate selected at time tw10 is set to 2V. If the threshold of the selected memory cell is less than 2V, the bit line voltage will be less than 1.5V. If the threshold voltage of the selected memory cell is 2V or higher, the bit line voltage remains 1.8V. VRFYBA2C becomes 0V at time tw11.
As can be seen from FIG. 9, the node N5C is "Low level".
And the node N3C is at "High level" (that is, the node N3
4C becomes "Low level") only in the case of "1" data. Therefore, only in case of "1" data, p channel
MOS transistors Qp12C, Qp19C, Qp20C
Turns on, and the node N1 becomes VCC. Then the signal S
AN1 and SAP1 become "L" and "H", respectively, and the flip-flop FF1 is deactivated, and the signal ECH1
Becomes "H" and is equalized. After this time tw12
Then, the signals RV1A and RV1B become "H". Time tw1
3 again, the signals SAN1 and SAP1 are "H",
When it goes to "L", the voltage of the node N1 is sensed and latched. Then, "whether the data in the memory cell is" 0 "or" 1 "or" 2 "or" 3 "" is sensed by the flip-flop FF1 and the information is latched.

The data held in the flip-flop FF1 is output to the outside of the chip by activating CENB1 at time tw14.

As a result of the above read operation, 4-level data is latched in the flip-flops FF1 and FF2 as shown in FIG.

The write operation and the write verify read operation may be performed in substantially the same manner as in the second embodiment.

In addition, in the third embodiment, the bit line and the dummy bit line are precharged every time before a predetermined read voltage is applied to the word line.

On the other hand, in the second embodiment, at the time of read and verify read, the bit line and the dummy bit line are first precharged, and thereafter the precharge is not performed, and the read voltage of the word line is changed (for example, 0 V). From 1V to 2V).

Each time a read voltage (for example, 0V, 1V, 2V) is applied to the word line during the read or verify read of the second embodiment, as in the third embodiment, the bit line and the dummy are read. The bit line may be precharged.

<Fourth Embodiment> Next, a fourth embodiment of the present invention will be described.

FIG. 19 is a diagram for explaining the fourth embodiment of the present invention, and FIGS. 19 (a) to 19 (c) respectively show
It is a figure which shows the output state of data.

Multi-valued storage EEPR according to the fourth embodiment
The OM is a memory cell array in which memory cells that store electrically rewritable n values (n is a natural number of 3 or more) are arranged in a matrix, and m latch circuits that hold data read from the memory cells. And a data circuit composed of.

As shown in FIGS. 19A to 19C, when reading data, the read data from the memory cell is first read to the k latch circuits. Then, the data read and held in the k latches is output to the outside of the chip before the read data is held in the other m−k latch circuits forming the data circuit. To be done.

At this time, the number of latch circuits which are first read and hold data may be two as shown in FIG. 19A or one as shown in FIG. 19B. The number may be three as shown in FIG.

Each of the m latch circuits may hold the data read from the memory cell when reading the data, and may hold the data to be written in the memory cell when writing the data.

Also in this case, the first read
The number of latch circuits for holding data may be two as shown in FIG. 19A, one as shown in FIG. 19B, or three as shown in FIG. 19C. good.

<Fifth Embodiment> Next, a fifth embodiment of the present invention will be described.

FIG. 20 is a diagram for explaining the fifth embodiment of the present invention. FIGS. 20 (a) to 20 (c) respectively show
It is a figure which shows the distribution of the threshold value of the memory cell according to multi-value data.

Multi-valued storage EEPR according to the fifth embodiment
The OM is a memory cell array in which memory cells that store electrically rewritable n values (n is a natural number of 3 or more) are arranged in a matrix, and m latch circuits that hold data read from the memory cells. And a data circuit composed of.

In the memory cell, the threshold voltage of the memory cell is the first threshold voltage region in the "1" state, and the threshold voltage of the memory cell is the first threshold voltage in the "2" state. Second threshold voltage region larger than the region, ..., “2n
(N is a natural number greater than or equal to 1) "is the second state in which the threshold value of the memory cell is larger than the (2n-1) th threshold voltage region.
An electrically rewritable 2n value that belongs to the n threshold voltage region is stored.

When reading data, it is first determined whether the memory cell is in the "n" state and the threshold voltage is substantially equal to or smaller than the memory cell, or in the "n + 1" state and the threshold voltage is substantially the same or large. The data read and held by the k latch circuits are output to the other mk latch circuits that form the data circuit before the read data is held.

Therefore, as shown in FIG.
When it is a value memory cell, first, in the first read,
In the word line (control gate) of the selected memory cell,
The voltage Vg1 between the "2" state and the "3" state is applied,
It suffices to read out whether it is the “1” or “2” state, or the “3” state or the “4” state.

In the case of the 8-value memory cell as shown in FIG. 20B, first, in the first read, the word line (control gate) of the selected memory cell
The voltage Vg2 between the "4" state and the "5" state is applied,
It suffices to read out whether it is the "1" or "2" or "3" or "4" state, or the "5" state, the "6" state, the "7" state or the "8" state.

Further, even in the case of a (2n + 1) value (n is a natural number) memory cell, a voltage such as Vg3 or Vg4 may be applied in the first reading as shown in FIG. That is, it is only necessary to apply a voltage for discriminating between n states and (n + 1) states out of 2n + 1 states.

Each of the m latch circuits may hold the data read from the memory cell when reading the data, and may hold the data to be written in the memory cell when writing the data.

<Sixth Embodiment> Next, a sixth embodiment of the present invention will be described.

FIG. 21 is a diagram for explaining the sixth embodiment of the present invention.

Multi-valued memory EEPR according to the sixth embodiment
The OM holds a memory cell array in which memory cells storing electrically rewritable n values (n is a natural number of 3 or more) are arranged in a matrix, and data to be written in the memory cells, and is read from the memory cells. First latch circuit for holding data, second latch circuit ... mth (m is 2
It includes t number of data circuits composed of latch circuits of the above natural numbers.

In the sixth embodiment, as shown in FIG. 21, the data to be written in the memory cell is first stored in the first latch circuit in each data circuit from the first t pieces of data. Loaded. The next t data are
It is loaded into the second latch circuit in each data circuit. The (i × t + 1) th to tth data from the beginning are loaded into the (i + 1) th (1 ≦ i ≦ m−1; i is a natural number) latch circuit in each data circuit.

The m latch circuits may hold the data to be written in the memory cell when writing the data, and may hold the data read from the memory cell when reading the data. And in this case, it may be combined with the fourth embodiment.

That is, as shown in FIG. 21, the data to be written in the memory cell is first transferred from the start address to the first t.
Data is loaded into the first latch circuit in each data circuit, the next t data is loaded into the second latch circuit in each data circuit, and from the beginning (i × t + 1) The t pieces of data are transferred to the (i + 1) (1
≦ i ≦ m−1; i is a natural number) and is loaded into the latch circuit. Then, as shown in FIG. 19, the data read from the memory cell is first read to k latch circuits, and the data read and held in the k latches are stored in the data circuit. The read data is output to the outside of the chip before the read data is held in the other m-k latch circuits.

Further, the following may be carried out.

As the data to be written in the memory cell, first t pieces of data from the head address are loaded into the first latch circuit in each data circuit, and the next t pieces of data are written.
The data is loaded into the second latch circuit in each data circuit, and the (i × t + 1) th to tth data from the first is (i + 1) th (1 ≦ i ≦ m−1; i is a natural number). ) Latch circuit. Then, at the time of reading, the data read and held in the k latch circuits out of m is output to the other m−k latch circuits forming the data circuit before the read data is held, Then m
The data read and held by the d latch circuits of the -k latch circuits are used by other mk-
The read data is output to the outside of the chip before being held in the d latch circuits.

<Seventh Embodiment> Next, a seventh embodiment of the present invention will be described.

FIG. 22 is a diagram for explaining the seventh embodiment of the present invention.

Multi-valued storage EEPR according to the seventh embodiment
The OM includes a memory cell array in which memory cells that store electrically rewritable n values (n is a natural number of 3 or more) are arranged in a matrix, and electrically rewritable n values (n is 3 or more). Memory cell array in which memory cells for storing the memory cell number) are arranged in a matrix, and a first latch circuit for holding data to be written in the memory cell and a second latch circuit for holding data read from the memory cell.
.., and t data circuits composed of the m-th (m is a natural number of 2 or more) latch circuit.

As shown in FIG. 22, the data to be written in the memory cell is first loaded into the first latch circuit in each data circuit from the first t pieces of data from the start address.
The next t pieces of data are loaded into the second latch circuit in each data circuit, and t pieces of data from the (i × t + 1) th to (i + 1) th (1 ≦ i) in each data circuit are loaded. ≤m
−1; i is a natural number) and is loaded into the latch circuit. Then, at the time of reading, the data first read and held in the first latch circuit is output to the other m-1 latch circuits forming the data circuit before the read data is held, and then the The data read and held by the second latch circuit is output to the other m-2 latch circuits forming the data circuit before the read data is held, and
The data read and held in the j-th (1 ≦ j ≦ m; j is a natural number) latch circuit is used as another m−j component of the data circuit.
The read data is output to the individual latch circuits before being held.

<Eighth Embodiment> Next, an eighth embodiment of the present invention will be described.

FIG. 23 is a diagram for explaining the eighth embodiment of the present invention.

Multi-valued memory EEPR according to the eighth embodiment
The OM includes a memory cell array in which memory cells that store electrically rewritable n values (n is a natural number of 3 or more) are arranged in a matrix, and electrically rewritable n values (n is 3 or more). Memory cell array in which memory cells for storing the memory cell number) are arranged in a matrix, and a first latch circuit for holding data to be written in the memory cell and a second latch circuit for holding data read from the memory cell.
.., and t data circuits composed of the m-th (m is a natural number of 2 or more) latch circuit.

As shown in FIG. 23, as the data to be written in the memory cell, first t pieces of data from the head address are loaded into the first latch circuit in each data circuit,
The next t pieces of data are loaded into the second latch circuit in each data circuit, and t pieces of data from the (i × t + 1) th to (i + 1) th (1 ≦ i) in each data circuit are loaded. ≤m
−1; i is a natural number) and is loaded into the latch circuit.

Then, as shown in FIG. 23, at the time of reading,
First, the data read and held in the m-th latch circuit is
The read data is output to the other m-1 latch circuits constituting the data circuit before being held, and then the (m-th)
The data read and held by the latch circuit of 1) is output to the other m−2 latch circuits forming the data circuit before the read data is held, and the p-th (1 ≦ p ≦ m; i
Is a natural number) and the data read and held in the latch circuit is
The read data is held in the other p-1 latch circuits that form the data circuit.

<Ninth Embodiment> Next, a ninth embodiment of the present invention will be described.

FIG. 24 is a diagram for explaining the ninth embodiment of the present invention.

Multi-valued memory EEPR according to the ninth embodiment
The OM includes a memory cell array in which memory cells that store electrically rewritable n values (n is a natural number of 3 or more) are arranged in a matrix, and electrically rewritable n values (n is 3 or more). Memory cell array in which memory cells for storing the memory cell number) are arranged in a matrix, and a first latch circuit for holding data to be written in the memory cell and a second latch circuit for holding data read from the memory cell.
.., and t data circuits composed of the m-th (m is a natural number of 2 or more) latch circuit.

As shown in FIG. 24, as the data to be written in the memory cell, first t pieces of data from the head address are loaded into the first latch circuit in each data circuit,
The next t pieces of data are loaded into the second latch circuit in each data circuit, and t pieces of data from the (i × t + 1) th to (i + 1) th (1 ≦ i) in each data circuit are loaded. ≤m
−1; i is a natural number) and is loaded into the latch circuit.

The size of write data may be smaller than the number of latch circuits in all the data circuits. In this case, as shown in FIG. 24, there is a data non-input area where write data is not input in the latch circuit. Out of the m latch circuits in the data circuit, the write data is not input from the outside to the f latch circuits in the data non-input area from the outside so that writing based on the data circuit becomes the shortest. Data of f latch circuits to which write data is not input is set.

For example, if the memory cells are "0", "1",
In a four-valued memory cell that can be in four states of "2" and "3", when the amount of data is small, some latch circuits do not receive write data. In this case, the memory cell to be written may be "0" write or "1" write.

Alternatively, when there is a small amount of data and some of the latch circuits do not receive the write data, the memory cell to be written is "0" write or
It suffices to write "1" or "2".

In any of the EEPROMs according to the fourth to ninth embodiments, the read operation can be speeded up as described in the first to third embodiments.

It is also possible to arbitrarily combine the first to ninth embodiments.

Although the present invention has been described above with reference to the first to ninth embodiments, the following further modifications are possible in these first to ninth embodiments.

FIG. 25 is a block diagram of an EEPROM having a modified column structure.

In the first to fourth embodiments, one data circuit 6 ^** corresponds to one bit line BL on the left and one bit line BL on the left and right.
One data circuit 6 ^** can be changed to a corresponding form.

As shown in FIG. 25, in an EEPROM having a modified column structure, four bit lines BLai are used.
-1~BLai-4 or for BLbi-1~BLbi-4 (i 0-3), one of the data circuit 6 ^** -0~6 ^** -m is provided.

The memory cell array 1A side will be described below as an example.

When selecting, for example, BLai-1 from the four bit lines BLai-1 to BLai-4, the signal BLC1 of the drive signals BLC1 to BLC4 for driving the transfer gate circuit 7 ^* A on the data circuit side is selected. Is set to the “H” level, and the other signals BLC2 to BLC4 are set to the “L” level.

At the same time, a drive signal B for driving the transfer gate circuit 7 ^** A on the non-selected bit line control circuit side.
Of LC1D to BLC4D, signal BLC1D is set to "L"
And set the other signals BLC2D to 4D,
Set to "H" level. Thus, only the bit lines BLi-1, which is selected is connected to the data circuit 6 ^** -0~6 ^** -m.

Thus, the selected bit line BLai is selected.
Only -1 it is connected to the data circuit 6 ^** -0~6 ^** -m, respectively the bit line BLai-2~BLai-4 that have not been selected, the unselected bit line control circuit 20-0A~20-mA Connected to. Non-selected bit line control circuit 20-0A to 20-mA
Are the unselected bit lines BLai-2 to BLai-4.
Is controlled.

The memory cells integrated in the memory cell arrays 1A and 1B are not limited to the NAND type cells, and the present invention can be implemented by the cells described below.

FIG. 26 is a diagram showing a memory cell array in which NOR type cells are integrated. The NOR type cell shown in FIG. 26 is connected to the bit line BL via a select gate.

FIG. 27 is a diagram showing a memory cell array in which other NOR type cells are integrated. NO shown in FIG. 27
The R-type cell is directly connected to the bit line BL.

FIG. 28 shows a memory cell array in which ground array type cells are integrated. As shown in FIG. 28, the ground array type cell has bit lines BL and source lines VS arranged in parallel. The ground array type cell is one of NOR type memories.

FIG. 29 is a diagram showing a memory cell array in which other ground array type cells are integrated. The ground array type cell shown in FIG. 29 has an erase gate EG used when data is erased. Further, a part of the control gate CG is of a so-called split channel type in which the channel of the memory cell transistor is overlapped.

FIG. 30 shows a memory cell array in which alternating ground array type cells are integrated. As shown in FIG. 30, the alternate ground array type cell matches the ground array type cell in that the bit line BL and the source line VS are arranged in parallel, but the bit line BL and the source line V are different from each other.
The difference is that S and S can be switched alternately.

FIG. 31 is a diagram showing a memory cell array in which other alternate ground array type cells are integrated. FIG.
The alternate ground array type cell shown in FIG. 1 has the same configuration as the ground array type cell shown in FIG.

FIG. 32 is a diagram showing a memory cell array in which DINOR (DIvided NOR) type cells are integrated.
As shown in FIG. 32, the DINOR type cell is configured by connecting, for example, four memory cell transistors in parallel between the bit line BL and the source line VS via a bit line side selection transistor.

FIG. 33 is a diagram showing a memory cell array in which AND type cells are integrated. As shown in FIG. 33,
The AND-type cell is configured by connecting, for example, four memory cell transistors in parallel between the bit line BL and the source line VS via the bit line side selection transistor and the source line side selection transistor.

In the first to ninth embodiments, multilevel data is given from the memory cell, and among the m latch circuits for identifying multilevel data, the level of multilevel data is identified. When the level of multi-valued data is determined and the level of multi-valued data is confirmed, the output operation can be performed even if the identification of the level of other multi-valued data is not completed. Then, during this output operation, the identification of the levels of other multi-valued data can be continued. When the identification of the level of the other multi-valued data is completed and the level of the multi-valued data is confirmed, the output operation can be started. of course,
Even during this output operation, it is possible to continue the identification of other multi-valued data (or the previously output multi-valued data) whose level identification has not been completed.

By doing so, multivalued data can be output to the outside of the device without waiting for completion of identification of all multivalued levels, and a memory cell for storing multivalued data is provided. However, it is possible to obtain a nonvolatile semiconductor memory device that can shorten the data read time.

[0188]

As described above, according to the present invention, it is possible to provide a non-volatile semiconductor memory device which has a memory cell for storing multi-valued data and can shorten the data read time.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a configuration of a multi-value storage NAND flash memory according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram showing configurations of a memory cell array and a column system circuit shown in FIG.

FIG. 3 is a diagram showing a threshold distribution of a memory cell transistor in 4-value storage.

FIG. 4 is a block diagram of the data circuit shown in FIG.

5A and 5B are views for explaining a read procedure performed by the device according to the first embodiment of the present invention. FIG. 5A is a diagram showing a threshold distribution of memory cells, and FIG. 5B is a diagram. Schematic which shows the outline of a read-out procedure.

6A and 6B are diagrams for explaining another read procedure performed by the device according to the first embodiment of the present invention, FIG. 6A is a diagram showing threshold distribution of memory cells, and FIG. The figure is a schematic view showing the outline of another reading procedure.

FIG. 7 is a circuit diagram of a data circuit included in a NAND flash memory according to a second embodiment.

FIG. 8 is an operation waveform diagram showing a read operation.

FIG. 9 is a diagram showing read data sensed and latched by a flip-flop.

FIG. 10 is a diagram showing read data sensed and latched by a flip-flop.

FIG. 11 is a diagram showing write data latched by a flip-flop.

FIG. 12 is an operation waveform diagram showing a write operation.

FIG. 13 is an operation waveform diagram showing a verify operation.

FIG. 14 is an operation waveform diagram showing a verify operation.

FIG. 15 is an operation waveform diagram showing another verify operation.

FIG. 16 is another circuit diagram of the data circuit.

FIG. 17 is another circuit diagram of the data circuit.

FIG. 18 is an operation waveform diagram for explaining a reading method according to the third embodiment of the present invention.

FIG. 19 is a diagram for explaining the fourth embodiment of the present invention, and FIGS. 19A to 19C are diagrams showing data output states.

FIG. 20 is a diagram for explaining the fifth embodiment of the present invention, and FIGS. 20A to 20C are diagrams showing threshold voltage distributions of memory cells.

FIG. 21 is a view for explaining the sixth embodiment of the present invention.

FIG. 22 is a view for explaining the seventh embodiment of the present invention.

FIG. 23 is a view for explaining the eighth embodiment of the present invention.

FIG. 24 is a view for explaining the ninth embodiment of the present invention.

FIG. 25 is an EE with a modified column configuration.
The block diagram of PROM.

FIG. 26 is a diagram showing a memory cell array in which NOR type cells are integrated.

FIG. 27 is a diagram showing a memory cell array in which other NOR type cells are integrated.

FIG. 28 is a diagram showing a memory cell array in which ground array type cells are integrated.

FIG. 29 is a diagram showing a memory cell array in which other ground array type cells are integrated.

FIG. 30 is a diagram showing a memory cell array in which alternating ground array type cells are integrated.

FIG. 31 is a diagram showing a memory cell array in which other alternate ground array type cells are integrated.

FIG. 32 is a diagram showing a memory cell array in which DINOR type cells are integrated.

FIG. 33 is a diagram showing a memory cell array in which AND cells are integrated.

FIG. 34 is a diagram for explaining a conventional read method, and FIG. 34 (a) is a diagram showing a threshold distribution of memory cells (b).
The figure is a schematic view showing an outline of a conventional reading method.

FIG. 35 is a diagram for explaining another conventional read method. FIG. 35 (a) is a diagram showing a threshold distribution of a memory cell. FIG. 35 (b) is a schematic view showing another conventional read method. Fig.

[Explanation of symbols]

1 ... Memory cell array, 2 ... Row related circuit, 3 ... Column related circuit, 4 ... Address buffer, 5 ... Data input / output circuit 6 ^** ... Data circuit, 7 ... Transfer gate circuit, MC ... Memory cell, M ... Memory cell Transistor, S ... Select transistor, SG ... Select gate, CG ... Control gate, BL ... Bit line. FF ... Flip-flop circuit.

Claims (10)

[Claims] 1. A memory cell array in which memory cells that store electrically rewritable n values (n is a natural number of 3 or more) are arranged in a matrix, and m memory cells that hold data read from the memory cells. Including a data circuit including a latch circuit, the data read and held in k latch circuits out of m during reading is held in the other mk latch circuits forming the data circuit. A non-volatile semiconductor memory device characterized by being output before being written. 2. The "1" state has a threshold voltage of the memory cell in a first threshold voltage region, and the "2" state has a threshold voltage of the memory cell less than the first threshold voltage region. A large second threshold voltage region, ..., “2n (n is a natural number greater than or equal to 1)” state means that the threshold value of the memory cell is 2n which is larger than the (2n−1) th threshold voltage region. A memory cell array in which memory cells that store electrically rewritable 2n values that belong to a threshold voltage region are arranged in a matrix, and m latch circuits that hold data read from the memory cells In the read operation, the memory cell is in a state in which the threshold voltage is substantially equal to or smaller than that in the “n” state, or “n” in the read operation.
Whether the +1 ″ state and the threshold voltage are substantially equal or large is read and held by the k latch circuits, and the read data is read by the other m−k latch circuits forming the data circuit. A non-volatile semiconductor memory device characterized by being output before being held. 3. A memory cell array in which memory cells that store electrically rewritable n values (n is a natural number of 3 or more) are arranged in a matrix, and data to be written in the memory cells is held and stored from the memory cells. A data circuit composed of m latch circuits that holds the read data, and the data read and held by the k latch circuits out of the m latch circuits at the time of reading are the other m−k latches that form the data circuit. A nonvolatile semiconductor memory device, wherein read data is output to a circuit before being held. 4. A memory cell array in which memory cells that store electrically rewritable n values (n is a natural number of 3 or more) are arranged in a matrix, and data to be written in the memory cells is held and stored from the memory cells. A first latch circuit that holds the read data, a second latch circuit, and t data circuits that are composed of m-th (m is a natural number of 2 or more) latch circuits, and write data to the memory cells. First, the first t pieces of data from the start address are loaded into the first latch circuit in each data circuit, the next t pieces of data are loaded into the second latch circuit in each data circuit, and from the beginning (( The (i × t + 1) th to tth data are the (i + 1) th data in each data circuit.
A nonvolatile semiconductor memory device, wherein the nonvolatile semiconductor memory device is loaded into a latch circuit of (1 ≦ i ≦ m−1; i is a natural number). 5. A memory cell array in which memory cells that store electrically rewritable n values (n is a natural number of 3 or more) are arranged in a matrix, and data to be written in the memory cells is held and stored from the memory cells. A first latch circuit that holds the read data, a second latch circuit, and t data circuits that are composed of m-th (m is a natural number of 2 or more) latch circuits, and write data to the memory cells. First, the first t pieces of data from the start address are loaded into the first latch circuit in each data circuit, the next t pieces of data are loaded into the second latch circuit in each data circuit, and from the beginning (( The (i × t + 1) th to tth data are the (i + 1) th data in each data circuit.
(1 ≦ i ≦ m−1; i is a natural number), and the data read and held in the k latch circuits out of m are read out and stored in the other m−k number of the data circuits. A nonvolatile semiconductor memory device, wherein read data is output to a latch circuit before being held. 6. A memory cell array in which memory cells for storing electrically rewritable n values (n is a natural number of 3 or more) are arranged in a matrix, and data to be written in the memory cells is held and stored from the memory cells. A first latch circuit that holds the read data, a second latch circuit, and t data circuits that are composed of m-th (m is a natural number of 2 or more) latch circuits, and write data to the memory cells. First, the first t pieces of data from the start address are loaded into the first latch circuit in each data circuit, the next t pieces of data are loaded into the second latch circuit in each data circuit, and from the beginning (( The (i × t + 1) th to tth data are the (i + 1) th data in each data circuit.
(1 ≦ i ≦ m−1; i is a natural number), and the data read and held in the k latch circuits out of m are read out and stored in the other m−k number of the data circuits. The read data is output to the latch circuit before being held, and then the data read and held by the d latch circuits out of the m-k pieces is read by the other m-k-d pieces forming the data circuit.
A nonvolatile semiconductor memory device, wherein read data is output to each latch circuit before being held. 7. A memory cell array in which memory cells that store electrically rewritable n values (n is a natural number of 3 or more) are arranged in a matrix, and data to be written in the memory cells is held and stored from the memory cells. A first latch circuit that holds the read data, a second latch circuit, and t data circuits that are composed of m-th (m is a natural number of 2 or more) latch circuits, and write data to the memory cells. First, the first t pieces of data from the start address are loaded into the first latch circuit in each data circuit, the next t pieces of data are loaded into the second latch circuit in each data circuit, and from the beginning (( The (i × t + 1) th to tth data are the (i + 1) th data in each data circuit.
(1 ≦ i ≦ m−1; i is a natural number), and the data read and held in the first latch circuit at the time of reading is the other m−1 latches forming the data circuit. The read data is output to the circuit before being held, and next, the data read and held in the second latch circuit is
The read data is output before being held by the other m−2 latch circuits that configure the data circuit, and the data read and held by the j-th (1 ≦ j ≦ m; j is a natural number) latch circuit is Other mj forming the data circuit
A nonvolatile semiconductor memory device, wherein read data is output to each latch circuit before being held. 8. A memory cell array in which memory cells that store electrically rewritable n values (n is a natural number of 3 or more) are arranged in a matrix, and data to be written in the memory cells is held and stored from the memory cells. A first latch circuit that holds the read data, a second latch circuit, and t data circuits that are composed of m-th (m is a natural number of 2 or more) latch circuits, and write data to the memory cells. First, the first t pieces of data from the start address are loaded into the first latch circuit in each data circuit, the next t pieces of data are loaded into the second latch circuit in each data circuit, and from the beginning (( The (i × t + 1) th to tth data are the (i + 1) th data in each data circuit.
(1 ≦ i ≦ m−1; i is a natural number), and when read, the data first read and held in the m-th latch circuit is the other m−1 latches constituting the data circuit. The read data is output to the circuit before being held, and then the data read and held by the (m−1) th latch circuit is read by the other m−2 latch circuits included in the data circuit. The data output before the data is held and read and held by the p-th (1 ≦ p ≦ m; i is a natural number) latch circuit is the other p−1 of the data circuit.
A nonvolatile semiconductor memory device, wherein read data is output to each latch circuit before being held. 9. A memory cell array in which memory cells that store electrically rewritable n values (n is a natural number of 3 or more) are arranged in a matrix, and data to be written in the memory cells is held and stored from the memory cells. A first latch circuit that holds the read data, a second latch circuit, and t data circuits that are composed of m-th (m is a natural number of 2 or more) latch circuits, and write data to the memory cells. First, the first t pieces of data from the start address are loaded into the first latch circuit in each data circuit, the next t pieces of data are loaded into the second latch circuit in each data circuit, and from the beginning (( The (i × t + 1) th to tth data are the (i + 1) th data in each data circuit.
(1 ≦ i ≦ m−1; i is a natural number), and among the m latch circuits in the data circuit, the f latch circuits to which write data is not input from the outside are the data circuits. So that writing based on
A non-volatile semiconductor memory device characterized by setting data of f latch circuits to which write data is not inputted from the outside. 10. An electrically rewritable n value (n is 3)
Memory cell array in which memory cells that store the above natural numbers) are arranged in a matrix, and t latch circuits that are configured by m latch circuits that hold data to be written in the memory cells and hold data read from the memory cells. The data read out and held in the k latch circuits out of the m latch circuits including the data circuit are output to the other mk latch circuits constituting the data circuit before the read data is held. Next, the data read and held in the d latch circuits out of the m-k pieces are read by other m-k-d pieces constituting the data circuit.
A nonvolatile semiconductor memory device, wherein read data is output to each latch circuit before being held.