JPH09251447A - Microcomputer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To speedily correspond to the change of a data rewrite method and to reduce a chip area by allocating the specified address area of a non-volatile memory to a program area for rewriting data on a remaining address area in the non-volatile memory. SOLUTION: The address area A of EEPROM (flash memory) 1 being the non-volatile memory where data can repetitively be written/read and written data can electrically be deleted is allocated to a program area for data rewriting in the remaining address area B and the address area B is allocated to a data area for the operation control of a one chip microcomputer. In such a case, the program of the address area A of EEPROM 1 can easily be changed by supplying data to EEPROM 1 from an external PROM writer and it can speedily correspond to the program change.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer incorporating a flash memory (EEPROM).

[0002]

2. Description of the Related Art A one-chip microcomputer is a program memory (nonvolatile memory) integrated on the same chip. A mask ROM, EPROM, EEPROM or the like is used as the program memory. (1) Built-in mask ROM If a plurality of masks are manufactured once, there is an advantage that mass production efficiency can be improved and a chip area can be reduced. However, when a program change is required, it is necessary to manufacture a plurality of masks again, which requires a lot of manufacturing time and cannot meet the request promptly. (2) Built-in EPROM There is an advantage that the program change can be promptly dealt with by writing the new data after erasing the current data with ultraviolet rays. However, all of the current data is erased by ultraviolet rays, and the same data that did not need to be erased must be rewritten. (3) Built-in EEPROM By electrically erasing the current data and then writing new data, there is an advantage that the program can be promptly changed. Moreover, since the current data can be partially erased, the data that does not need to be erased can be left as it is.

Now, the recent one-chip microcomputer utilizes the advantages of the above-mentioned non-volatile memories and uses the EEPR.
It contains OM and mask ROM. The EEPRO
M is used as a program memory for controlling the operation of the one-chip microcomputer, and is the mask ROM.
Is used as a program memory for rewriting the data in the EEPROM.

As a result, the one-chip microcomputer can rewrite the data in the EEPROM by itself, and the versatility is improved.

[0005]

However, the above E
When it is desired to change the data rewriting method of the EPROM, it is necessary to remanufacture a mask for the mask ROM, which causes a problem that the program change of the mask ROM cannot be promptly dealt with. Further, since the EEPROM and the mask ROM must be independently arranged on one chip via wiring, there is a problem that the chip area becomes large.

Therefore, the present invention, in a microcomputer having a built-in non-volatile memory capable of repeatedly writing and reading data and electrically erasing written data, quickly responds to a change in the data rewriting method of the non-volatile memory. An object of the present invention is to provide a microcomputer that can be manufactured and can reduce the chip area.

[0007]

The present invention has been made to solve the above problems, and provides a nonvolatile memory capable of repeatedly writing and reading data and electrically erasing written data. In the built-in microcomputer, a specific address area of the non-volatile memory is assigned to a program area for rewriting data in the remaining address area of the non-volatile memory.

Further, it is a memory capable of repeatedly writing and reading data and electrically erasing the written data, wherein a specific address area is assigned to a program area for rewriting data in the remaining address area. Memory and a CPU that performs rewriting processing of the remaining address area of the non-volatile memory based on an instruction read from a specific address area of the non-volatile memory, and rewriting of the remaining address area of the non-volatile memory. And a prohibition unit that prohibits the next instruction from being read from a specific address area of the non-volatile memory while the processing is being performed.

Furthermore, it is a memory that can repeatedly write and read data and can electrically erase the written data, and a specific address area is assigned to a program area for rewriting data in the remaining address area. Memory and a program counter, and a CPU that operates based on a program instruction read from a specific address area of the nonvolatile memory,
An address holding circuit for supplying and holding address data to be rewritten in the non-volatile memory from the CPU, a data holding circuit for supplying and holding rewriting data in the non-volatile memory from the CPU, and a non-volatile memory When a program command to start rewriting data in the remaining address area is read from a specific address area, the nonvolatile memory is set to the write mode for the time required for data rewriting, and the program counter A memory control circuit that invalidates the output and writes the data of the data holding circuit to a specified address of the non-volatile memory by the address holding circuit; and the non-volatile memory when the non-volatile memory is set to the write mode. Output of static memory in indefinite state A CPU control circuit for prohibiting the affected, with a.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of the present invention will be specifically described with reference to the drawings. FIG. 1 is a circuit block diagram showing a microcomputer of the present invention, which is integrated on one chip. FIG. 2 is a time chart for explaining the operation of FIG. In FIG. 1, (1) is an EEPROM. E
The EPROM (1) is a non-volatile memory capable of repeatedly writing and reading data and electrically erasing written data. The address area A of the EEPROM (1) is allocated to the program area for data rewriting of the remaining address area B, and the address area B
Is assigned to a data area for controlling operation of the one-chip microcomputer. EEPROM (1) is
It has a terminal AD to which address data is applied, a terminal DIN to which write data is applied, a terminal DOUT to which read data is output, and a terminal WE to which a write mode setting signal is applied. The program in the address area A of the EEPROM (1) can be easily changed by supplying data from the external PROM writer (not shown) to the EEPROM (1), and the program can be quickly changed.

(2) is a CPU, which is an EEPROM
It operates based on the read data from the terminal DOUT in (1). The CPU (2) is assumed to include a program counter (3), an instruction register, an instruction decoder, an arithmetic logic unit, and the like, which are necessary for executing a logical operation. (4) is a latch circuit (address holding circuit according to claim 3),
A number equal to the bit number m of the address data of the EPROM (1) is provided. The L terminal of the latch circuit (4) is connected in parallel to the address terminal of the CPU (2) via the m address buses (5), and the C terminal is commonly connected to the clock terminal of the CPU (2). That is, the latch circuit (4) latches the address data in synchronization with the clock CK0.

Reference numeral (6) is a latch circuit (a data holding circuit according to claim 3), which is provided in the same number as the bit number n of 1 byte of the EEPROM (1). The L terminal of the latch circuit (6) is connected to the CPU via the data bus (7) n
It is connected in parallel with the data terminal of (2), and the C terminal is the CPU
Commonly connected to the other clock terminals of (2), and the Q terminal is E
It is connected to the terminal DIN of the EPROM (1). That is, the latch circuit (6) latches the write data in synchronization with the clock CK1 and supplies the write data to the EEPROM (1).

The AND gates (8) and (9) and the OR gate (10) form a switching circuit. The switching circuits are provided by the same number m as the latch circuits (4). One input terminal of the AND gate (8) is a program counter (3)
Of the AND gate (9), one input terminal of the AND gate (9) is connected to the Q terminal of the latch circuit (4), and the output terminal of the OR gate (10) is the terminal A of the EEPROM (1).
Connected with D. That is, the switching circuit EE sets the address data of either the program counter (3) or the latch circuit (4) according to the selection signal SELECT which will be described later.
Supply to PROM (1).

(11) is a memory control circuit. EEP
When the program instruction for starting the data rewriting of the address area B is read from the ROM (1), the CPU (2)
Decodes the program command to start pulse STAR
Output T. The memory control circuit (11) detects the trailing edge of the start pulse START, and the time T
A mode control signal MODE that becomes low level for a time T1 after 0 has passed is output and supplied to the terminal WE of the EEPROM (1). Therefore, the EEPROM (1) is set to the write mode only during the period T1 when the mode control signal MODE is at the low level. The period T1 is E
The EPROM (1) is set to a time necessary and sufficient for writing data to the specified address. The memory control circuit (11) detects the rising edge of the mode control signal MODE and outputs an end pulse END. The memory control circuit (11) outputs the selection signal SELECT that becomes a low level only during the period from the fall of the start pulse START to the fall of the end pulse END. Therefore, the switching circuit has the program counter (3) only while the selection signal SELECT is at a low level.
The output of the latch circuit (4) and the output of the latch circuit (4) is EEPRO.
It is supplied to the terminal AD of M (1).

(12) is a CPU control circuit. EEP
The execution time of one instruction of the ROM (1) is a unit of μsec, but the data writing time of the EEPROM (1) is mse.
Very long with c units. Therefore, during the period T1 when the EEPROM (1) is in the write mode, the CPU (2) is in the EEP.
It is necessary to prohibit the influence of the indefinite output of the terminal DOUT of the ROM (1) and stop the value of the program counter (3) as it is. The CPU control circuit (12)
Only during the period from the fall of the start pulse START to the fall of the end pulse END, the inhibit signal INH
Is output. The CPU (2) detects the prohibition signal INH and performs the prohibition operation.

The operation of FIG. 1 will be described below with reference to the time chart of FIG. In the initial state, the mode control signal M
ODE and the selection signal SELECT are high level,
It is assumed that the EEPROM (1) is set to the read mode addressed by the program counter (3). The program command X is a command for causing the latch circuit (4) to latch the address data, and the program command X.
+1 is an instruction to latch the write data in the latch circuit (6), and program instruction X + 2 is an instruction to write the data in the EEPROM (1).

When the program command X is read from the terminal DOUT of the EEPROM (1), the program command X
Is decoded by the CPU (2), and the address data is latched in the latch circuit (4) in synchronization with the clock CK0. The program counter (3) is incremented by +1 and E
Program command X from terminal DOUT of EPROM (1)
When +1 is read, the program instruction X + 1 is CP
It is decoded by U (2) and the write data is clocked by CK1.
It is latched by the latch circuit (6) in synchronization with.

When the program counter (3) is incremented by +1 and the program command X + 2 is read from the terminal DOUT of the EEPROM (1), the program command X + 2 is decoded by the CPU (2). Then, the start pulse START is generated. Select signal SELECT
Changes to low level in response to the fall of the start pulse START. The mode selection signal MODE changes to the low level for the time T1 after the time T0 has elapsed from the fall of the start pulse START, and then returns to the high level. The end pulse END is generated in response to the return of the mode control signal MODE to the high level. The selection signal SELECT changes to high level in response to the fall of the end pulse END.

Therefore, the inhibit signal INH is generated during the period in which the data in the address area B of the EEPROM (1) is rewritten, so that the CPU (2) can ignore the influence of the undefined output of the terminal DOUT of the EEPROM (1). , And the value of the program counter (3) to the start pulse START
Can be retained as is. As a result, EEPRO
The malfunction of the CPU (2) at the time of rewriting the data of M (1) can be prevented.

As a measure for preventing malfunction of the CPU (2) when rewriting data in the address area B of the EEPROM (1), the CPU (2) is in a standby state (HALT).
Means for stopping the system clock of the CPU (2), a means for returning the value of the program counter (3) to the state when the start pulse START is generated by using a jump instruction, and the like.

FIG. 3 is a circuit block diagram showing a concrete example of stopping the system clock of the CPU (2).
Built into U (2). In FIG. 3, reference numeral (13) is a latch circuit, an inhibition signal INH having the same waveform as the selection signal SELECT is applied to the L terminal, and a system clock generated from the clock generator (14) is applied to the inverter C (15) at the C terminal. Is applied via. That is, the latch circuit (13) latches the inhibit signal INH in synchronization with the fall of the system clock. The AND gate (16) calculates the logical product of the Q terminal output of the latch circuit (13) and the system clock. Therefore, when the EEPROM (1) is writing data, the system clock is stopped and the CPU (2)
The operation can be stopped to prevent the malfunction.

FIG. 4 is a block diagram showing a specific example of returning the value of the program counter (3) to the state when the start pulse START is generated by using the jump instruction.
Built in (2). In FIG. 4, (17) is a D-type flip-flop, the inhibit signal INH is applied to the D terminal, and the clock CK2 generated for each instruction unit of the CPU (2) is applied to the C terminal. The clock CK
0, CK1 and CK2 are generated based on the system clock of the clock generator (14). Therefore,
The D-type flip-flop (17) outputs the inhibition signal INH to C
It is synchronized with the operation timing of PU (2). Reference numeral (18) is a selection circuit, and jump instruction data fixedly generated by using a logic circuit inside the CPU (2) and an EEPROM.
The command data read from the terminal DOUT of (1) is selectively output by the Q terminal output of the D-type flip-flop (17). The selection circuit (18) selectively outputs jump instruction data when the Q terminal output of the D-type flip-flop (17) is at low level. Reference numeral (19) is an instruction decoder which returns the value of the program counter (3) to the state when the start pulse START was generated by decoding the jump instruction data. Therefore, E
When EPROM (1) is rewriting data, E
The read data from the terminal DOUT of the EPROM (1) can be ignored, and the value of the program counter (3) can always be held at the value when the start pulse START was generated. Therefore, E
When the EPROM (1) returns from the write mode to the read mode, the read operation can be executed from the address when the start pulse START is generated.

From the above, by assigning the address area A of the EEPROM (1) to the program area for rewriting the data of the remaining address area B, the conventional 1
The chip area can be reduced as compared with the case where the EEPROM and the mask ROM are integrated on the chip. Also, EE
It is possible to reliably prevent malfunction of the CPU (2) when rewriting data in the address area B of the PROM (1).

[0024]

According to the present invention, in a microcomputer having a built-in nonvolatile memory capable of repeatedly writing and reading data and electrically erasing written data, a specific address area of the nonvolatile memory is Since the data in the remaining address area of the non-volatile memory is allocated to the program area for rewriting, the chip area can be reduced. Further, there is an advantage that the malfunction of the CPU can be surely prevented when the data in the remaining address area of the nonvolatile memory is rewritten.

[Brief description of drawings]

FIG. 1 is a circuit block diagram showing a microcomputer of the present invention.

FIG. 2 is a time chart for explaining the operation of FIG.

FIG. 3 is a diagram showing an embodiment of a prohibition unit of the present invention.

FIG. 4 is a diagram showing another embodiment of the prohibition means of the present invention.

[Explanation of symbols]

 (1) EEPROM (2) CPU (3) Program counter (4) (6) Latch circuit (11) Memory control circuit (12) CPU control circuit

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Toshikazu Abe 2-5-5 Keihan Hondori, Moriguchi City, Osaka Sanyo Electric Co., Ltd.

Claims (6)

[Claims] 1. A microcomputer including a non-volatile memory capable of repeatedly writing and reading data and electrically erasing written data, wherein a specific address area of the non-volatile memory is the remaining portion of the non-volatile memory. A microcomputer characterized by being assigned to a program area for rewriting the data in the address area of. 2. A memory capable of repeatedly writing and reading data and electrically erasing written data, wherein a specific address area is allocated to a program area for rewriting data in the remaining address area. Memory, a CPU that performs rewriting processing of the remaining address area of the non-volatile memory based on an instruction read from a specific address area of the non-volatile memory, and rewriting of the remaining address area of the non-volatile memory A microcomputer comprising: a prohibition unit that prohibits a next instruction from being read from a specific address area of the nonvolatile memory while processing is being performed. 3. A non-volatile memory, which is capable of repeatedly writing and reading data and electrically erasing written data, wherein a specific address area is assigned to a program area for rewriting data in the remaining address area. A non-volatile memory and a program counter, which operates based on a program command read from a specific address area of the non-volatile memory, and the CPU supplies address data to be rewritten to the non-volatile memory. An address holding circuit for holding, a data holding circuit for supplying and holding rewriting data of the non-volatile memory from the CPU, and starting rewriting of data in the remaining address area from a specific address area of the non-volatile memory When the program instruction is read, A memory that sets the non-volatile memory to a write mode only for the time required for rewriting, and disables the output of the program counter to write the data of the data holding circuit to a specified address of the non-volatile memory by the address holding circuit. A control circuit, and a CPU control circuit that inhibits the CPU from being affected by a read output in an indefinite state of the nonvolatile memory when the nonvolatile memory is set to a write mode. Characteristic microcomputer. 4. The microcomputer according to claim 3, wherein the CPU control circuit puts the CPU in a standby state. 5. The microcomputer according to claim 3, wherein the CPU control circuit stops an operation clock of the CPU. 6. The microcomputer according to claim 3, wherein the CPU control circuit repeats a jump instruction in which the value of the program counter is used as an address when the nonvolatile memory is set to the write mode. .