JPH09293063A - Microcomputer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To cancel incomvenience to rewrite data already written in an address by inhibiting the data rewriting operation of a non-volatile memory unless the size of an address area in the non-volatile memory is established. SOLUTION: An external equipment is connected to a one-chip microcomputer. When address data of the address area A of EEPROM 1 is supplied from the external equipment to the one-chip microcomputer and latched by a latch circuit 4, fear that the program of the address area A is rewritten exists. Then, an address detecting circuit 18 detects that address data outputted from the latch circuit 4 belongs to the address area A of EEPROM 1, keeps a mode control signal MODE to be in a high level and inhibits that EEPROM 1 becomes the writing mode. Thus, incomvenience that data of the address area A of EEPROM 1 is rewritten is eliminated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer incorporating a flash memory (EEPROM).

[0002]

2. Description of the Related Art A one-chip microcomputer is a program memory (nonvolatile memory) integrated on the same chip. A mask ROM, EPROM, EEPROM or the like is used as the program memory. (1) Built-in mask ROM If a plurality of masks are manufactured once, there is an advantage that mass production efficiency can be improved and a chip area can be reduced. However, when a program change is required, it is necessary to manufacture a plurality of masks again, which requires a lot of manufacturing time and cannot meet the request promptly. (2) Built-in EPROM There is an advantage that the program change can be promptly dealt with by writing the new data after erasing the current data with ultraviolet rays. However, all of the current data is erased by ultraviolet rays, and the same data that did not need to be erased must be rewritten. (3) Built-in EEPROM By electrically erasing the current data and then writing new data, there is an advantage that the program can be promptly changed. Moreover, since the current data can be partially erased, the data that does not need to be erased can be left as it is.

Now, the recent one-chip microcomputer utilizes the advantages of the above-mentioned non-volatile memories and uses the EEPR.
There is a high tendency to incorporate OM. The EEPROM is used as a program memory for controlling the operation of the one-chip microcomputer. Here, of the address areas of the EEPROM, the first address area is an area which is treated in the same manner as a mask ROM in which data is not rewritten,
The remaining second address area is an area where data is rewritten as necessary.

[0004]

By the way, the above-mentioned EEP
The ROM has a characteristic that the written data can be electrically erased. However, since the first address area is handled in the same manner as the mask ROM, it is necessary to prohibit the malfunction such that the data in the first address area is erased. There is. However,
When an external device is connected to the 1-chip microcomputer and the address data of the first address area of the EEPROM is supplied from the external device to the 1-chip microcomputer, rewriting of data in the first address area of the EEPROM is prohibited. Because there is no way to do it, EE
There is a problem that the program in the first address area of the PROM is partially changed, and as a result, the one-chip microcomputer malfunctions.

In order to solve this problem, means for detecting whether the address data supplied from the external device to the one-chip microcomputer belongs to the first or second address area of the EEPROM is provided. If the address data belongs to the first address area,
It may be operated so as to prohibit the rewriting of data in the EEPROM.

On the other hand, even if the detecting means is provided, the number of addresses in the first address area of the EEPROM remains fixed and varies according to the type of external equipment connected to the one-chip microcomputer. I can't. In particular, depending on the type of external device, the EE
The 1-chip microcomputer may not be applicable unless the first address area of the PROM is expanded.
Therefore, there is a problem that the applicable range of the one-chip microcomputer is limited.

In order to solve this problem, when the one-chip microcomputer is released from reset, the first and second EEPROMs of the EEPROM are transferred from the register to the detection means.
It may be configured to set an address that should be the boundary of the address area. However, when the one-chip microcomputer is released from the reset state, an address which should be the boundary between the first and second address areas of the EEPROM may not be set in the register due to some factors.
In this case, an indeterminate address that the user does not want is set in the detection means. Therefore, the EEPR
There is a problem that the write data of the address that does not need to be rewritten in the OM is rewritten.

Therefore, the present invention provides a microcomputer for prohibiting the data rewriting operation of the non-volatile memory when the size of the first address area of the non-volatile memory is not fixed after reset release of the microcomputer. With the goal.

[0009]

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and provides a memory capable of repeatedly writing and reading data and electrically erasing written data. , A non-volatile memory in which the first address area is assigned to a program area for rewriting data of the remaining second address area, and which of the first address area and the second address area of the non-volatile memory is designated And a first address area of the non-volatile memory is designated, an address detection circuit for prohibiting the data rewriting operation of the non-volatile memory and a reset of the non-volatile memory when the microcomputer is released from reset. A setting time that causes the address detection circuit to set an address that should be the boundary between the first address area and the second address area. When the address which should be the boundary between the first address area and the second address area of the non-volatile memory is not set from the setting circuit to the address detection circuit for some reason after the reset release of the microcomputer, the non-volatile It is provided with a prohibition circuit for prohibiting the data rewriting operation of the non-volatile memory regardless of which address area of the memory is designated.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of the present invention will be specifically described with reference to the drawings. FIG. 1 is a circuit block diagram showing a microcomputer of the present invention, which is integrated on one chip. FIG. 2 is a time chart for explaining the operation of FIG. In FIG. 1, (1) is an EEPROM. E
The EPROM (1) is a non-volatile memory capable of repeatedly writing and reading data and electrically erasing written data. The address area A of the EEPROM (1) is allocated to the program area for data rewriting of the remaining address area B, and the address area B
Is assigned to a data area for controlling operation of the one-chip microcomputer. EEPROM (1) is
It has a terminal AD to which address data is applied, a terminal DIN to which write data is applied, a terminal DOUT to which read data is output, and a terminal WE to which a write mode setting signal is applied. The program in the address area A of the EEPROM (1) can be easily changed by supplying data from the external PROM writer (not shown) to the EEPROM (1), and the program can be quickly changed.

(2) is a CPU, which is an EEPROM
It operates based on the read data from the terminal DOUT in (1). The CPU (2) is assumed to include a program counter (3), an instruction register, an instruction decoder, an arithmetic logic unit, and the like, which are necessary for executing a logical operation. Reference numeral (4) is a latch circuit, which is provided in a number equal to the number of bits m of the address data of the EEPROM (1). The L terminal of the latch circuit (4) is CP via the address bus (5) m lines.
U (2) address terminal is connected in parallel, C terminal is CP
It is commonly connected to the clock terminal of U (2). That is, the latch circuit (4) latches the address data in synchronization with the clock CK0.

(6) is a latch circuit, which is an EEPROM
A number equal to the bit number n of 1 byte in (1) is provided. The L terminal of the latch circuit (6) is the data bus (7) n
Connected in parallel with the data terminal of the CPU (2) via a book,
The C terminal is commonly connected to the other clock terminal of the CPU (2), and the Q terminal is connected to the terminal DIN of the EEPROM (1). That is, the latch circuit (6) latches the write data in synchronization with the clock CK1 and the EEPROM
Supply to (1).

The AND gates (8) and (9) and the OR gate (10) form a switching circuit. The switching circuits are provided by the same number m as the latch circuits (4). One input terminal of the AND gate (8) is a program counter (3)
Of the AND gate (9), one input terminal of the AND gate (9) is connected to the Q terminal of the latch circuit (4), and the output terminal of the OR gate (10) is the terminal A of the EEPROM (1).
Connected with D. That is, the switching circuit EE sets the address data of either the program counter (3) or the latch circuit (4) according to the selection signal SELECT which will be described later.
Supply to PROM (1).

(11) is a memory control circuit. EEP
When the program instruction for starting the data rewriting of the address area B is read from the ROM (1), the CPU (2)
Decodes the program command to start pulse STAR
Output T. The memory control circuit (11) detects the trailing edge of the start pulse START, and the time T
A mode control signal MODE that goes low for a time T2 after a lapse of 1 is output and supplied to the terminal WE of the EEPROM (1). Therefore, the EEPROM (1) is set to the write mode only during the period T2 when the mode control signal MODE is at the low level. The period T2 is E
The EPROM (1) is set to a time necessary and sufficient for writing data to the specified address. The memory control circuit (11) detects the rising edge of the mode control signal MODE and outputs an end pulse END. The memory control circuit (11) outputs the selection signal SELECT that becomes a low level only during the period from the fall of the start pulse START to the fall of the end pulse END. Therefore, the switching circuit has the program counter (3) only while the selection signal SELECT is at a low level.
The output of the latch circuit (4) and the output of the latch circuit (4) is EEPRO.
It is supplied to the terminal AD of M (1).

(12) is a CPU control circuit. EEP
The execution time of one instruction of the ROM (1) is a unit of μsec, but the data writing time of the EEPROM (1) is mse.
Very long with c units. Therefore, during the period T2 when the EEPROM (1) is in the write mode, the CPU (2) is in the EEP.
It is necessary to prohibit the influence of the indefinite output of the terminal DOUT of the ROM (1) and stop the value of the program counter (3) as it is. The CPU control circuit (12)
Only during the period from the fall of the start pulse START to the fall of the end pulse END, the inhibit signal INH
Is output. The CPU (2) detects the prohibition signal INH and performs the prohibition operation.

(13) is a clock generator,
The clock CK is supplied to the CPU (2). CPU (2)
Creates a system clock for operating the one-chip microcomputer based on the clock CK. Hereinafter, the operation of FIG. 1 will be described based on the time chart of FIG. In the initial state, the mode control signal MODE and the selection signal SELECT are high level, and the EEPROM
It is assumed that (1) is set to the read mode addressed by the program counter (3). A program instruction X is an instruction to cause the latch circuit (4) to latch the address data, and a program instruction X + 1 is an instruction to cause the latch circuit (6) to latch the write data.
The program command X + 2 is a command for writing data in the EEPROM (1).

When the program command X is read from the terminal DOUT of the EEPROM (1), the program command X
Is decoded by the CPU (2), and the address data is latched in the latch circuit (4) in synchronization with the clock CK0. The program counter (3) is incremented by a predetermined value,
When the program instruction X + 1 is read from the terminal DOUT of the EEPROM (1), the program instruction X + 1 is C
The data is decoded by PU (2) and the write data is clocked by CK.
It is latched by the latch circuit (6) in synchronization with 1.

When the program counter (3) is incremented by a predetermined value and the program instruction X + 2 is read from the terminal DOUT of the EEPROM (1), the program instruction X + 2 is decoded by the CPU (2). Then, the start pulse START is generated. Selection signal SELECT
T changes to low level in response to the fall of the start pulse START. The mode selection signal MODE changes to the low level for the time T1 after the time T0 has elapsed from the fall of the start pulse START, and then returns to the high level. The end pulse END is generated in response to the return of the mode control signal MODE to the high level.
The selection signal SELECT changes to high level in response to the fall of the end pulse END.

Therefore, the inhibit signal INH is generated during the period in which the data in the address area B of the EEPROM (1) is rewritten, so that the CPU (2) can ignore the influence of the undefined output of the terminal DOUT of the EEPROM (1). Moreover, the value of the program counter (3) can be held as it is when the start pulse START is generated by stopping the system clock. As a result, malfunction of the CPU (2) at the time of rewriting the data of the EEPROM (1) can be prevented.

Now, in FIG. 1, (14) is an RS flip-flop, a reset signal RESET (high active) for a one-chip microcomputer is applied to the S terminal, and a falling detection circuit ( 1
A write pulse WRITE (high active) is applied via 5). That is, the RS flip-flop (1
4) is set when the one-chip microcomputer is reset, and the write pulse WR is set after the one-chip microcomputer is released from reset.
It is reset when ITE falls. (16) is an AND gate, the output STOP of the Q terminal of the RS flip-flop (14) is applied to one input terminal,
The write pulse WRITE is applied to the other input terminal. That is, from the AND gate (16), the write pulse WRITE is passed only once, no matter how many times it is generated after the reset of the one-chip microcomputer is released. Reference numeral (17) is a register for setting the final address data of the address area A of the EEPROM (1) in synchronization with the write pulse WRITE output from the AND gate (16). That is, in the register (17), the final address data of the address area A of the EEPROM (1) is set only once by executing the program instruction after the reset of the one-chip microcomputer is released.

Reference numeral (18) is an address detection circuit, which outputs the final address data of the address area A of the EEPROM (1) output from the register (17) and the latch circuit (4).
The memory control circuit (11) is controlled based on the comparison result with the address data output from the memory. Since the address area A of the EEPROM (1) is a program area for rewriting the data of the address area B, the problem that the data of the address area A is rewritten should not occur. When the data in the address area B of the EEPROM (1) is rewritten inside the one-chip microcomputer, the problem that the data in the address area A is rewritten does not occur. However, connecting an external device to the 1-chip microcomputer,
When the address data of the address area A of the EEPROM (1) is supplied from the external device to the one-chip microcomputer and latched by the latch circuit (4), the program of the address area A may be rewritten. Therefore, the address detection circuit (18) outputs the address data output from the latch circuit (4) to the EEPROM.
Detecting that it belongs to the address area A of (1), the mode control signal MODE is kept at the high level, and the EEP
The ROM (1) is prohibited from entering the write mode. As a result, it is possible to solve the problem that the data in the address area A of the EEPROM (1) is rewritten.

Since any address data can be set in the register (17), the data rewrite prohibited area of the EEPROM (1), that is, the address area A can be enlarged or reduced. For example, when the external device is a personal computer, the personal computer is an EEPROM (1).
It operates based on the program in address area B of
Since the personal computer performs complicated and many operations, it is necessary to enlarge the address area A of the EEPROM (1). As a result, the address area A of the EEPROM (1) is changed according to the type of external device to be interfaced.
, The range of application of the one-chip microcomputer is expanded and versatility is improved.

Further, (19) is an AND gate, to which a start pulse START is applied to one input terminal and a signal STOP is inverted and applied to the other input terminal. Normally, after the reset release of the one-chip microcomputer, a write pulse WRITE is generated.
The output STOP of the Q terminal of the S flip-flop (14) has a logical value "0". Therefore, the AND gate (19) is opened and the CPU (3) causes the memory control circuit (11) and C
The start pulse START is constantly supplied to the PU control circuit (12), and the data rewriting operation of the EEPROM (1) is executed without any inconvenience.

However, after the reset release of the one-chip microcomputer, if the write pulse WRITE is not generated for some reason, the output STOP of the Q terminal of the RS flip-flop (14) remains the logical value "1". Become. Therefore, the AND gate (19) is closed and the memory control circuit (11) receives the start pulse STA.
Since RT is no longer supplied, the data rewriting operation of the EEPROM (1) is prohibited. That is, the EEPROM (1)
It is possible to solve the inconvenience of rewriting the written data of the address that does not require rewriting.

[0025]

According to the present invention, if the address which should be the boundary between the first and second address areas of the non-volatile memory is not set in the address detection circuit for some reason after the reset release of the microcomputer, the non-volatile There is an advantage that the data rewriting operation of the memory can be prohibited, that is, the inconvenience of rewriting the written data of the address of the non-volatile memory where rewriting is unnecessary.

[Brief description of drawings]

FIG. 1 is a circuit block diagram showing a microcomputer of the present invention.

FIG. 2 is a time chart for explaining the operation of FIG.

[Explanation of symbols]

 (1) EEPROM (11) Memory control circuit (14) RS flip-flop (15) Fall detection circuit (16) (19) AND gate (17) Register (18) Address detection circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Noriyuki Kogata 2-5-5 Keihan Hon-dori, Moriguchi-shi, Osaka Sanyo Electric Co., Ltd. (72) Masanori Okubayashi 2-chome, Keihan-hondori, Moriguchi-shi, Osaka No. 5-5 Sanyo Electric Co., Ltd.

Claims (3)

[Claims] 1. A memory capable of repeatedly writing and reading data and electrically erasing written data, wherein a first address area is assigned to a program area for rewriting data of a remaining second address area. The non-volatile memory and whether the first address area or the second address area of the non-volatile memory is designated, and when the first address area of the non-volatile memory is designated, the non-volatile memory And an address detection circuit that prohibits the data rewriting operation of the microcomputer, and causes the address detection circuit to set an address that should be a boundary between the first address area and the second address area of the nonvolatile memory when the microcomputer is released from reset. After the resetting of the setting circuit and the microcomputer, When an address to be used as a boundary between the first address area and the second address area of the nonvolatile memory is not set in the address detection circuit by the setting circuit, any address area of the nonvolatile memory is designated. And a prohibition circuit for prohibiting a data rewriting operation of the non-volatile memory. 2. The setting circuit generates a write pulse only when the microcomputer is released from reset, and the address data to be the boundary between the first address area and the second address area of the nonvolatile memory. 2. The microcomputer according to claim 1, further comprising: a register which is set by the write pulse and which is output to the address detection circuit. 3. The data rewriting of the non-volatile memory is prohibited by the output of the generation circuit when the output of the generation circuit is the same during and after resetting of the microcomputer. The microcomputer according to Item 2.