JPH09247001A - Acs arithmetic unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a circuit scale by providing a decode circuit decoding the comparison result and an overflow detection signal and a selection circuit with clip processing conducting altogether the selection of sum results and clip processing based on a control signal outputted from the decode circuit. SOLUTION: An adder 101 executes the calculation of PMA[4:0]+BMA[4:0] and an adder 102 executes the calculation of PMB[4:0]+BMB[4:0]. Then an overflow detection circuit 104 detects an overflow at the addition and a comparator 103 compares the quantity of the addition results. Succeedingly a decoder circuit 105 decodes overflow detection signals OA, OB and a comparison result CP and a clip processing including selection circuit 106 selects the result of sum which is smaller in the results. In the case that the selected sum result is overflow data, clip processing is applied to the data. Then the clip processing including selection circuit 106 is controlled by the decoder circuit 105 to conduct selection of the sum result and the clip processing altogether.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ACS arithmetic unit for calculating a path metric in Viterbi decoding which is a kind of error correction.

[0002]

2. Description of the Related Art In recent years, a method of processing and transmitting video and audio signals as digital signals has become mainstream. Error correction technology is an important technology in these digital signal processing. Various error correction methods have been proposed up to now, and one of them is Viterbi decoding using a convolutional code. Viterbi decoding is maximum likelihood decoding that decodes to a most probable value, and a code that is closest to the received code is selected from among possible codes and decoded as information. The difference between a code that can occur at present and the received code is called a branch metric, and the sum of branch metrics is called a path metric. The closest code is selected by calculating the path metric and selecting the smallest one. The calculation of the path metric is performed by ACS (Add Compare Select) calculation.

An example of the above-mentioned conventional Viterbi decoder is the Viterbi decoder disclosed in Japanese Patent Laid-Open No. 7-202724. The ACS unit that performs the ACS operation performs addition (Add) of the path metric and branch metric for each of the two types of data, compares the addition results (Compare),
An ACS arithmetic unit for selecting the smaller one is used as a basic element. In addition, since the ACS arithmetic unit performs branch metric accumulation, it performs two types of overflow processing as processing for overflow due to accumulation. The first type of overflow processing is performed by the ACS arithmetic unit itself, and is limiter processing (hereinafter referred to as clip processing in the present specification) that sets the upper limit of the result after addition to a specific value. The second is performed by input data given to the ACS arithmetic unit, and is a normalization process by giving a negative value to the branch metric when the value of the path metric exceeds a specific value.

The ACS unit occupies a large part of the Viterbi decoder, and providing a small-scale apparatus for the ACS arithmetic unit as a basic element leads to reduction in the circuit scale of the Viterbi decoder.

[0005]

However, in the configuration of the ACS arithmetic unit as described above, clip processing is performed after addition as overflow processing, and then selection is performed, and two clips corresponding to two addition results are obtained. A processing circuit and a selection circuit are required. Also, if clip processing is performed after addition and selection, a single clip processing circuit corresponding to one selected addition result can be configured. However, the addition result including overflow data is compared in magnitude, and overflow detection is performed after selection. To perform the above, an adder and a comparator having a bit width obtained by adding 1 to the bit width of the input data are required. Therefore, there is a problem that the scale of the ACS arithmetic unit, which is a basic element, is increased, and the scale of the Viterbi decoder is increased.

Therefore, the present invention newly focuses on the point that the selection circuit and the clip processing circuit can be shared by controlling the selection circuit using the overflow detection signal and the comparison result, and the overflow detection signal and the comparison result are compared. It is obtained by including a decoding circuit for decoding and a selection circuit with clip processing which is controlled by the decoding circuit and performs selection and clip processing collectively. Further, focusing on the fact that the path metric of the ACS arithmetic unit is positive number data, the branch metric is two's complement data, and the sum of the path metric and the branch metric is positive number data, the bit width of the adder and the comparator is Is obtained by reducing.

SUMMARY OF THE INVENTION Therefore, in view of the above problems, an object of the present invention is to provide a small-scale ACS arithmetic unit for reducing the circuit scale of a Viterbi decoder.

[0008]

In order to solve the above problems, the ACS arithmetic unit of the present invention performs addition of two data, and outputs a sum and a carry to a higher order, that is, a first and a second addition. Detector, an overflow detection circuit for detecting an overflow due to addition of the first and second adders, a comparator for comparing the magnitudes of the sums output by the first and second adders, and an overflow detection circuit A decoder circuit for decoding the overflow detection signal and the comparison result output by the comparator, and a sum of the first and second adders controlled by the decoder circuit are selected. If the sum of the selected adders is overflow data, the clip is clipped. It is provided with a selection circuit with clip processing for processing.

According to the present invention, with the above-described configuration, the decoding circuit decodes the overflow detection signal and the comparison result, and controls the selection circuit with clip processing to select the addition result and clip processing at once. By making the selection circuit and the clip processing circuit common, the circuit scale can be reduced.

The ACS arithmetic unit of the present invention adds the two's complement data and the positive number data, and outputs the sum and the carry to the higher order, and the first and second adders. An overflow detection circuit for detecting an overflow due to addition of the 2 adder is provided, and the 1st and 2nd adders respectively add a bit width equal to the larger bit width of 2's complement data and positive number data. The overflow detection circuit detects overflow from the carry to the upper order and the most significant bit of the two's complement data output from the first and second adders. Further, a comparator for comparing the magnitudes of the sums output from the first and second adders is provided, and the comparator is a subtractor having a bit width equal to the bit width of the first and second adders. The carry to the higher order output by is used as the comparison result.

According to the present invention, due to the above-described structure, the carry to the upper side of each adder and the overflow from the most significant bit of the branch metric which is 2's complement data are detected, and the comparison result is not taken into consideration at the time of overflow. Since the clipping process is performed, the bit width of the adder and the comparator can be made equal to the bit width of the input data, and the circuit scale can be reduced.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION AC according to one embodiment of the present invention
The S arithmetic unit will be described with reference to the drawings.

FIG. 1 is a block diagram of an ACS arithmetic unit according to the first embodiment of the present invention. The ACS calculation device shown in the figure performs ACS calculation by inputting path metrics PMA [4: 0], PMB [4: 0], branch metrics BMA [4: 0], BMB [4: 0], and path metrics. Outputs PM [4: 0].

In FIG. 1, reference numerals 101 and 102 denote adders for adding a path metric and a branch metric, respectively, and outputting the addition result and the carry to the higher order. The adder 101 receives the path metric PMA [4: 0] and the branch metric BMA [4: 0] as inputs, executes PMA [4: 0] + BMA [4: 0], and then adds the result AA [4: 0]. And carry CA to the higher order, and the adder 102 inputs PMB [4: 0] + BMB [4: 0] with the path metric PMB [4: 0] and branch metric BMB [4: 0] as inputs. After execution, the addition result AB [4: 0] and the carry CB to the higher order are output.

Reference numeral 103 is a comparator which compares the addition results AA [4: 0] and AB [4: 0] and outputs the comparison result CP. 104
Is an overflow detection circuit that detects an overflow at the time of addition of the adders 101 and 102, and PMA [4: 0] + BMA
Overflow detection signal OA, PMB [4: 0] + BM when [4: 0] is executed
Outputs overflow detection signal OB when B [4: 0] is executed.

Reference numeral 105 is an overflow detection signal OA, OB,
A decoder circuit that decodes the comparison result CP and outputs the control signals SA, SB, and PS. 106 is controlled by the control signals SA and SB, and selects the smaller one of the addition results AA [4: 0] and AB [4: 0]. However, if the addition result to be selected is overflow data, the clip to be clipped is clipped. This is a selection circuit with processing, and outputs the path metric PM [4: 0] after ACS calculation. The control signal PS output from the decoder circuit 105 is a signal indicating which addition result is selected by the selection circuit with clipping process.

In this specification, n is used as a signal notation method.
The bit bus is shown as a signal name [n-1: 0], and the i-th bit from the LSB of the n-bit bus is shown as a signal name [i] (0≤i≤n-1).

The operation of the ACS arithmetic unit configured as described above will be described below. In the ACS arithmetic unit of FIG. 1, first, addition (Add) of a path metric and a branch metric is performed on two types of data.
01 for PMA [4: 0] + BMA [4: 0], adder 102 for PMB [4: 0] + BM
Execute B [4: 0]. Next, the overflow detection device 10
4 detects an overflow at the time of addition, and the comparator 103 compares the result of addition (Compare). Then, the decoder circuit 105 causes the overflow detection signal O
A, OB and the comparison result CP are decoded, and the selection circuit with clip processing 106 selects the smaller one of the addition results (Sel
If the addition result to be selected is overflow data, clipping processing is performed and the path metric PM [4: 0] after ACS calculation is output.

The selection circuit with clip processing 106 is controlled by the decoder circuit 105 to collectively select the addition result and perform the clip processing. FIG. 2 shows a truth table for explaining the operations of the decoder circuit 105 and the clipping circuit-equipped selection circuit 106. OA, OB, and CP are input signals of the decoder circuit 105, SA, SB, and PS are output signals of the decoder circuit 105, and PM [4: 0] are after the ACS calculation output by the selection circuit with clip processing 106. It is a path metric. As shown in the figure, when the selection circuit with clipping process 106 selects PMA [4: 0] + BMA [4: 0] as PM [4: 0], the decoder circuit 105 sets SA to logical value 1 , SB is set to a logical value of 0, and PMB [4:
When selecting [0] + BMB [4: 0], set SA to logical value 0, SB to logical value 1, and perform clip processing to the maximum value (all 1)
In this case, both SA and SB have a logical value of 0. As shown in FIG. 1, the clip processing selection circuit 106 is composed of a composite logic gate using two logical products, one logical sum, and logical negation of input and output, and the control signals SA and SB shown in FIG. The selection of the addition result and the clip processing are collectively performed by.

As described above, according to the present embodiment, the selection of the addition result and the clip processing are collectively performed by the decoding circuit 105 for decoding the overflow detection signals OA and OB and the comparison result CP and the control signal output from the decoding circuit 105. By providing the selection circuit with clip processing 106 that is performed later, the selection circuit and the clip processing circuit can be shared, and the circuit scale can be reduced.

The second embodiment of the present invention will be described below.
This will be described with reference to the drawings. FIG. 1 is a block diagram of an ACS arithmetic unit showing a second embodiment of the present invention. The configuration is the same as that of the first embodiment, and the same reference numerals are given and a detailed description thereof is partially omitted. In the second embodiment,
Adders 101 and 102, overflow detection circuit 10
4. The configuration of the comparator 103 will be described.

The ACS arithmetic unit shown in the figure has path metrics PMA [4: 0], PMB [4: 0], branch metrics BMA [4: 0],
ACS calculation is performed using BMB [4: 0] as an input, and path metric PM [4: 0] is output. Path metric PMA [4: 0], PMB
[4: 0] and PM [4: 0] are positive number data, and branch metrics BMA [4: 0] and BMB [4: 0] are 2's complement data. Also,
Sum of path metric and branch metric AA [4: 0], AB
[4: 0] is positive number data. In the ACS operation, as overflow processing, there is normalization processing by giving a negative value to the branch metric when the value of the path metric exceeds a specific value, in addition to clipping processing performed by detecting the overflow at the time of addition. . Therefore, the branch metrics BMA [4: 0] and BMB [4: 0] become 2's complement data for the normalization process.

FIG. 3 shows the configuration of the 5-bit adder used in the adders 101 and 102. The adder shown in the figure uses A [4: 0] + B [4: 0] + CIN as input with 5-bit data A [4: 0], B [4: 0] and carry CIN from the lower order. Is added, and the 5-bit sum SUM [4: 0] and carry COUT to the higher order are output. In FIG. 3, reference numerals 301 to 305 denote full adders (1-bit adders), which form a ripple carry adder. A [4: 0], B [4: 0], CIN, and COUT of the adder shown in the figure are PMA [4: 0], BMA [4: 0], logical value 0, and CA in the adder 101, respectively. , Adder 102 uses PMB [4: 0], BMB [4: 0], logical value 0, and CB, respectively.

FIG. 1 shows the configuration of the overflow detection circuit 104. The overflow detection circuit 104 detects an overflow at the time of addition of the adders 101 and 102 from the most significant bits BMA [4] and BMB [4] of the branch metric and the carry outputs CA and CB to the upper side. BMA [4] and BMB [4] are code bits of the branch metrics BMA [4: 0] and BMB [4: 0], respectively. 4 and 5 show truth table for explaining the operation of the overflow detection circuit 104. In FIG. 4, OA is an overflow detection signal of the adder 101, and in FIG. 5, OB is an overflow detection signal of the adder 102. Overflow cannot occur if the branch metric is negative (sign bit is a logical 1). Therefore, the overflow detection circuit detects an overflow when the branch metric is positive (the sign bit is a logical value 0) and the carry to the upper rank of each adder is a logical value 1.

FIG. 6 shows the structure of the comparator 103. The comparator shown in the figure subtracts the addition results AB [4: 0] and AA [4: 0],
It is a comparator that judges the magnitude based on the sign bit of the subtraction result, and outputs a logical value 0 when AB [4: 0] is smaller than AA [4: 0] in the comparison result CP, and outputs a logical value 1 otherwise. . In FIG. 6, 201 is an adder similar to that shown in FIG. 3, and 202 is a logical NOT gate that logically inverts all bits of AA [4: 0]. In the adder 201, A [4: 0], B [4: 0], CIN, and COUT of the adder shown in FIG. 3 are respectively the logic inversion of AA [4: 0], AB [4: 0], and logic. Use as value 1, CP.

Normally, the addition result of two 5-bit data is 6-bit data when it is expressed including overflow data, and a 6-bit adder is required to perform magnitude comparison. However, the addition result AA [4: 0], AB [4: 0], which is the sum of the path metric and the branch metric of the adders 101, 102, is positive number data, and the addition results of the adders 101, 102 When an overflow is detected, the decoder circuit 105 and the clip processing selection circuit 106 perform clip processing regardless of the comparison result.
It can be configured by a 5-bit adder.

As described above, in consideration of the fact that the path metric of the ACS arithmetic unit is positive data and the branch metric is 2's complement data, the overflow detection circuit 104 is considered.
Takes into account that the sum of the path metric and the branch metric is positive number data, the comparator 103 compares the addition result with the sign bit of the branch metric and the carry to the upper part by addition. By doing so, the bit width of the adder and the comparator can be made equal to the bit width of the input data, and the circuit scale can be reduced.

In the first and second embodiments of the present invention, when the overflow due to the addition of the adder 101 and the adder 102 is not detected and the addition results are the same, the selection circuit with clipping process 106 Adder 101
However, the addition result of the adder 102 may be selected.

Further, in the second embodiment of the present invention, the ripple carry adder is used as the 5-bit adder used in the adder 201 of the adders 101 and 102 and the comparator 103, but CLA (Carry Look Ahead) is used. ) A high-speed adder such as an adder may be used.

[0030]

As described above, according to the present invention, the overflow detection signal and the decoding circuit for decoding the comparison result by the magnitude comparison and the control signal output from the decoding circuit are provided with the clip processing for collectively selecting and clipping the addition result. By providing the selection circuit, the selection circuit and the clip processing circuit can be shared, and the circuit scale can be reduced.

Considering that the path metric is positive number data, the branch metric is two's complement data, and the sum of the path metric and the branch metric is positive number data,
The overflow detection circuit detects an overflow, and the comparator compares the addition results to make the bit width of the adder and comparator equal to the bit width of the input data, thus reducing the circuit scale. can do.

The ACS arithmetic unit is a basic element of the ACS unit that occupies a large part of the Viterbi decoder, and it is possible to provide a small-scale Viterbi decoder by reducing the circuit scale.

[Brief description of drawings]

FIG. 1 is an AC in the first and second embodiments of the present invention.
Block diagram of S arithmetic unit

FIG. 2 is a diagram showing a truth table for explaining the operation of the decoder circuit and the clipping circuit with clipping process in the first embodiment.

FIG. 3 is a configuration diagram of a 5-bit adder according to a second embodiment of the present invention.

FIG. 4 is a diagram showing a truth table for explaining the operation of the overflow detection circuit according to the second embodiment of the present invention.

FIG. 5 is a diagram showing a truth table for explaining the operation of the overflow detection circuit according to the second embodiment of the present invention.

FIG. 6 is a configuration diagram of a comparator according to a second embodiment of the present invention.

[Explanation of symbols]

 101, 102, 201 Adder 103 Comparator 104 Overflow detection circuit 105 Decoder circuit 106 Selection circuit with clip processing 202 Logical NOT gate 301 to 305 Full adder (1 bit adder)

Claims (5)

[Claims] 1. A first and a second adder for adding two data and outputting a sum and a carry to a higher order, and an overflow for detecting an overflow due to the addition of the first and the second adder. A detection circuit, a comparator for comparing the magnitudes of the sums output by the first and second adders, and a decoder circuit for decoding the overflow detection signal output by the overflow detection circuit and the comparison result output by the comparator. When,
A selection circuit with clip processing is provided, which is controlled by the decoder circuit, selects the sum of the first and second adders, and performs clip processing when the sum of the selected adders is overflow data. ACS arithmetic unit. 2. A control signal for controlling three states, wherein the decoder circuit selects three sums of the first adder, two sums of the second adder and clip processing. 2. The AC according to claim 1, wherein the selection circuit with clip processing sets the result to a maximum value that can be represented by an output bit width when the clip processing is performed.
S computing device. 3. A first and a second adder for adding two's complement data and a positive number data and outputting a sum and a carry to a higher order, and the addition of the first and second adders. An overflow detection circuit for detecting overflow;
And the second adder are bit adders each having a bit width equal to the larger one of the two's complement data and the positive number data, and the overflow detection circuit includes the first and second adders. Carry to higher order and the above 2
An ACS arithmetic unit, wherein overflow is detected from the most significant bit of the complement data of the. 4. A comparator for comparing the magnitudes of the sums output from the first and second adders, wherein the comparator subtracts a bit width equal to the bit widths of the first and second adders. 4. The ACS arithmetic unit according to claim 3, wherein the carry is output to the higher order and the comparison result is output from the subtracter. 5. The first and second aspects of claim 3 and claim 4.
3. The ACS arithmetic unit according to claim 1, further comprising the adder, the overflow detection circuit, and the comparator.