JPH09246374A - Multilayer interconnection structure and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form a multilayer interlayer insulating film where a wiring is restrained from being exposed at a raised part in an SOG etch-back process keeping a gap between micro wirings wide enough for letting SOG flow into it. SOLUTION: An insulating film 303 is formed only on the upside of a lower wiring 302 before three-layer interlayer insulating film layers which comprise an organic application glass SOG layer 305 are formed. An SOG etch-back process is carried out to remove SOG so as not to make the SOG film exposed at a joint between the lower wiring 302 and an upper wiring 307. At this point, an etch-back margin is ensured by the insulating film 303 so as to prevent the lower wiring 302 from being exposed at a raised part. As mentioned above, an interlayer insulating film for a micro wiring of pitch 0.35μm or below can be flattened by taking advantage of an SOG etch-back method, so that an ULSI of high reliability can be manufactured at a low cost.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer wiring structure and a manufacturing method thereof, and more particularly to a multilayer wiring structure suitable for a multilayer wiring of a semiconductor device and a manufacturing method thereof.

[0002]

2. Description of the Related Art A dynamic random access memory (DRAM) using a 0.5 μm processing process, which is currently the mainstream.
Then, as an interlayer insulating film for multilayer wiring, P-TEOS /
SOG (Spin on glass) / P-TEOS
The insulating film between the three layers is used. Here, P-TE
OS is a silicon oxide film formed by plasma CVD using tetraethyl orthosilicate (TEOS) as a source. This three-layer insulating film is formed by processing metal wiring, then depositing the first layer of P-TEOS, and then forming the second layer of organic SOG film. It is formed by etching back the portion and then depositing a third layer of P-TEOS.

A parallel plate type single frequency plasma CVD apparatus is used for forming P-TEOS. Since the covering state of the step portion of the P-TEOS becomes an overhang shape, it is formed under the condition that the overhang portion does not contact with a fine inter-wiring space.
Therefore, due to the constraint of this condition, P- that can be formed on the wiring is
The maximum film thickness of TEOS is fixed.

Further, the film thickness of the organic SOG film is designed based on the filling and flattening characteristics and the accuracy of the etch back. Normally,
A film thickness of about 250 nm is applied in the flat portion. The quality of this organic SOG film deteriorates in the resist removal process, and it is not reliable enough to be used as an interlayer insulating film due to problems such as degassing and film quality stability. The via holes are removed by etching back so that it is not exposed. A multilayer wiring technique using such an insulating film between three layers is described in, for example, the fourth edition of a collection of papers of the 1986 V-MIC Society.
74-483 (June 9-10, 1986 V-MIC Conf., P
p.474-483).

By the way, D having a stack type capacitor
In a memory integrated circuit such as a RAM, there is a difference in elevation between the memory section and the peripheral driving circuit section. The organic SOG film becomes thicker on a portion having a lower altitude and on a wiring having a wider pattern width.
Generally, the thickness of the peripheral circuit portion is widest on the wiring having a wide pattern width, and the etch back amount is determined so as to remove this thickness.

[0006]

However, according to the above-mentioned multilayer wiring technique, the organic SOG film thickness is extremely thin on the fine wiring of the memory portion having a high altitude, and the film thickness is about 10% of the flat portion film thickness. Since the thickness is thick, the thin organic SOG film is removed in the initial stage of the etch-back process, and then P-TEOS is continuously etched. When the P-TEOS is thin, the wiring layer is exposed and exposed to plasma, and as a result, there is a problem in that the wiring is thinned by etching and characteristic deterioration due to charge-up occurs. Therefore, in this etch-back process, it is necessary to leave the P-TEOS on the wiring so as not to expose the wiring layer having a high altitude and to remove the organic SOG film of the P-TEOS on the wiring having a low altitude. For this purpose, P-TEO
It is desired to form S thinly in the inter-wiring space portion and thickly on the wiring. In particular, it is necessary to form a thick P-TEOS on the wiring while securing the inflow region of the organic SOG so that voids (spaces with defective embedding) are not formed in the space between the fine wirings.

However, in the conventional plasma CVD method, the overhang portion inevitably exists in the step portion, and the ratio of the overhang portion to the flat portion film thickness is the conventional parallel plate single frequency plasma. It is about 0.6 by CVD and about 0.53 by two-frequency excitation plasma CVD. Therefore, practically, the limit was to form P-TEOS having a thickness corresponding to a space between wirings of about 0.35 μm.

Further, regarding the embedding of a silicon oxide film in a space between fine wirings, for example, p. 69 to p. 75 (June 27-29, 1995 VMI of the 1995 VMIC Society papers).
As described in C Conference, pp.69-75), there is a method of applying a bias high-density plasma CVD,
Since the stability of silicon oxide film formation, the cost increase, and the planarization process such as chemical mechanical polishing (CMP) are essential, they are not accepted in the mass production process of memory products.

Therefore, an object of the present invention is to make it possible to embed an insulating film in a space between fine wiring lines of 0.35 μm or less and to flatten the insulating film formed by etching back an organic SOG film applicable to a mass production process at low cost. It is an object of the present invention to provide a multilayer wiring structure using a film as an interlayer insulating film and a method for manufacturing the same.

[0010]

In order to achieve the above object, a multilayer wiring structure according to the present invention has a first insulating film disposed in contact with the upper surface of a lower wiring, and a first insulating film. And a second insulating film arranged to cover the lower wiring,
To cover at least the coated glass film located at the low altitude part of the insulating film surface, the coated glass film located at the low altitude part and the exposed coated glass film and the film insulating film at the high altitude part. It is characterized in that a multi-layered insulating film composed of the arranged third insulating film is provided as an interlayer insulating film between the lower wiring and the upper wiring.

Further, the method for manufacturing a multilayer wiring structure according to the present invention comprises: a step of depositing a lower wiring layer; a step of depositing a first insulating film on the lower wiring layer; and a step of depositing a first insulating film on the first insulating film. A step of forming a photoresist pattern, a step of forming a lower wiring having a first insulating film deposited on its upper surface, a step of depositing a second insulating film, a step of forming a coated glass film, and a step of forming a coated glass film. The method is characterized by including a step of removing a part, a step of depositing a third insulating film, and a step of depositing an upper wiring layer.

In this case, the step of forming the lower wiring may be a step of etching the first insulating film and the lower wiring layer by using the photoresist pattern as a mask, or by using the photoresist pattern as a mask. After the first insulating film is etched by the above method, the photoresist may be removed, and the lower wiring layer may be etched using the first insulating film as a mask.

Further, in the above-mentioned multilayer wiring structure,
It is preferable that the first to third insulating films are silicon oxide films formed by the plasma chemical vapor deposition method. Further, it is preferable that the coated glass film is an organic SOG film. Furthermore, it is preferable that the first to third insulating films are fluorine-containing low dielectric constant silicon oxide films.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION A preferred embodiment of a multilayer wiring structure according to the present invention is, for example, as shown in FIG. 4C, a first insulating film, that is, a P-TEOS film 303 is a lower wiring. The second insulating film (P-TEOS film 304) is provided so as to contact only the upper surface of the (metal wiring 302), and covers the side surfaces of the first insulating film and the exposed lower wiring layer, and At least the SOG film 305 exists on the wide wiring portion having a low altitude, and at least the first insulating film (P-TEOS film 303, on the upper surface portion of the fine wiring having a high altitude).
Depending on the location, the second insulating film PTEOS 304 is also included), and an exposed SOG film and an insulating film having a multilayer structure in which a third insulating film (P-TEOS film 306) is provided on the upper surface of the insulating film. The multilayer wiring structure has a structure provided as an interlayer insulating film between a lower wiring (metal wiring 302) and an upper wiring (metal wiring 307).

The method of manufacturing the above-mentioned multilayer wiring structure is
For example, the process flow diagram of FIG. 1 and (a) to FIG.
After depositing a metal wiring layer (step S10), a P-TEOS film 303 serving as a first insulating film is deposited thereon (step S11) as shown in the cross-sectional structure diagram of the main part shown in FIG.
P-TEOS using well-known photolithography technology.
A photoresist pattern is formed on the film 303 (step S
12). Next, the P-TEOS film 303 (step S13) is processed by using this photoresist pattern as a mask,
Further, the metal wiring layer is processed by using the same photoresist pattern as a mask to form the metal wiring 302 serving as a lower wiring (step S14), and then the photoresist pattern is removed (step S15). After depositing the P-TEOS film 304 to be the second insulating film (step S16), organic S is formed on the surface.
The OG film 305 is applied (step S17; FIG. 4).
(A)). At this time, the thickness of the organic SOG film becomes thicker on a portion having a lower altitude and on a wiring having a wider pattern width. continue,
Etch back the organic SOG film 305 (step S18;
As shown in FIG. 4B, the surface is flattened. At this time, although the P-TEOS film 303 on the metal wiring 302 at a high altitude is exposed, the metal wiring 302 below it is not exposed, and
The P-TEOS film 30 of the metal wiring 302 in the low altitude portion
The organic SOG film 305 on 4 is etched back so as to be removed. The P-TEOS in step S11
The thickness of the film 303 is set by etching back the metal wiring 30.
Needless to say, it is deposited in advance to a thickness such that 2 is not exposed. The second insulating film (P-TEOS film 304) may be exposed depending on the locations of the high altitude portion and the low altitude portion. Next, P-TE to be the third insulating film
The OS film 306 may be deposited (step S19), and finally the metal layer 307 to be the upper wiring layer may be deposited (step S20; FIG. 4C). Further, in order to reduce the parasitic capacitance between the wiring layers in order to reduce the wiring delay which is a problem in the LSI and the like, a fluorine-based gas is mixed when depositing the first to third insulating films by the plasma CVD method. Then, a low dielectric constant silicon oxide film containing fluorine may be formed.

After forming the lower wiring in which the first insulating film is previously deposited in this way, a three-layer insulating film composed of the second insulating film, the coated glass film and the third insulating film is formed. Thus, the multilayer wiring structure according to the present invention can be obtained.

[0017]

Next, more specific embodiments of the multilayer wiring structure and the method for manufacturing the same according to the present invention will be described in detail below with reference to the accompanying drawings.

<Embodiment 1> FIG. 1 is a process diagram of a flattening process flow for showing an embodiment of a method for manufacturing a multilayer wiring structure according to the present invention. FIGS. It is the figure which showed the principal part cross-section structure of the main processes of the processes shown in order. In this embodiment, the embedding flattening is severe 1000
A twin wiring portion having a wiring width and a space of about nm will be described as an example.

First, step S10 of the process shown in FIG.
In, the substrate 201 on which the insulating film was deposited was used, and the metal wiring layer 202 serving as the lower wiring layer was formed on the substrate 201. Although the metal wiring layer 202 is shown in a simplified manner in the drawing, W (100 nm) / Al-Si (3
(00 nm) / TiN (100 nm) is a metal wiring layer having a three-layer laminated structure.

Next, in step S11, an insulating film 203 was formed on the metal wiring layer 202. This insulating film 20
Reference numeral 3 is a plasma silicon oxide film (P-TEOS) having a thickness of 200 nm formed by a parallel plate type single frequency CVD apparatus.
It is.

Then, in step S12, a photoresist pattern 204 was formed on the insulating film 203 (FIG. 2A). In step S13, the insulating film 203 is dry-etched using the photoresist pattern 204 as a mask, and in step S14, the metal wiring layer 202 is dry-etched to form the metal wiring 202.
After forming, the photoresist pattern 204 was removed in step S15 (FIG. 2B).

Next, in step S16, the insulating film (P-TEOS) 205 is formed on the dual frequency excitation parallel plate type CVD.
It was formed using the apparatus. At this time, organic SO in the next step
In order to secure the G inflow region, the P-TEOS film thickness of the flat portion is set to 300 in consideration of the overhang of the P-TEOS film.
nm (FIG. 2 (c)). Here, the reason why the dual frequency excitation parallel plate type CVD device is used is that since this CVD device has high directivity, it has a small overhang with respect to a fine pattern width and a gap of a wiring width and a space of around 1000 nm. This is because it is easy to form a TEOS film.

Subsequently, in step S17, the organic SOG film 206 is formed so that the flat portion has a thickness of 250 nm. Here, the organic SOG was spin-coated and then baked on a hot plate at 80 ° C., 150 ° C. and 250 ° C. for 3 minutes each in order, and then cured at 450 ° C. for 30 minutes in nitrogen (film modification by heat treatment). Quality). The shape of the obtained cross section is shown in FIG.

In step S18, etchback was performed to remove the organic SOG on the wide wiring in the low altitude portion (FIG. 3B). At this time, the organic SOG in the wiring portion having a high altitude is removed because it has a small film thickness. Next, with respect to the sample in this state, in step S19, PT
The EOS film 207 is formed, and the organic SOG 20 is formed on the wiring connection portion.
A flattening interlayer insulating film having a structure in which 6 was not exposed was formed. Finally, in step S20, a metal wiring layer 208 serving as an upper wiring layer is deposited on the planarized interlayer insulating film (FIG. 3).
(C)). After that, although not shown, the metal wiring layer 208 may be processed by a photoetching technique to form a wiring pattern, and a passivation film may be formed on the surface. If necessary, step S11 and subsequent steps may be repeated to form a multilayer. Wiring may be formed.

In this embodiment, the insulating layer 203 on the metal wiring is used.
Although an example in which a P-TEOS film is applied is shown in FIG. 1, if dry etching conditions are adjusted in the insulating layer processing step of step S13 shown in FIG. 1, an insulating film other than P-TEOS, such as monosilane or alkoxysilane, is used. It is also applicable to a plasma silicon oxide film (P-SiO) formed by the above method.

In the flattening process flow of FIG. 1, the metal wiring layer forming step of step S14 and the step S
Replacing the photoresist pattern removing step of 15, the metal wiring layer 202 is processed by using the processed insulating film after removing the photoresist pattern as a mask, and the insulating layer 2 is formed only on the upper surface.
You may form the metal wiring layer 202 which has 03.

<Embodiment 2> FIG. 4 illustrates a multilayer wiring structure according to the present invention as a dynamic random access memory (DR).
1) is an example in the case of being applied to a multi-layered wiring of FIG.
According to the process flow shown in, the cross section of the main part of the element surface in the main process in the state from the metal layer deposition process for the lower wiring in step S10 to the metal layer (2) deposition process for the upper wiring in step S20 It is a structure. The memory mat portion is on the left side of the drawing and the peripheral circuit portion is on the right side, and FIGS. 4A to 4C show the vicinity of the boundary between them. Since attention is paid to the portion of the multi-layer wiring structure formed on the surface here, the element forming portion in the semiconductor layer such as the diffusion layer constituting the DRAM element is omitted in the drawing.

In FIG. 4A, reference numeral 301 indicates boron phosphorus glass (BPSG), and the BPSG 301 has a higher altitude on the memory mat portion than on the peripheral circuit portion. This FIG. 4A shows a metal layer deposition process (step S1).
0) to the organic SOG coating step (step S17) are shown. That is, BPS
On the G301, the metal wiring layer 302 and the insulating film PT
After depositing EOS303, a photoresist pattern is formed, and P-TEOS3 is used with the photoresist pattern as a mask.
03 and the metal wiring layer 302 are dry-etched to remove the photoresist pattern, and then P-TEO is further covered so as to cover the metal wiring layer 302 and P-TEOS 303.
The state where S304 is deposited and the organic SOG film 305 is applied to the entire surface is shown. As shown in FIG. 4A, the organic SOG film 305 is thin in the memory mat portion and thick in the peripheral circuit portion. Here, the metal wiring layer 302 is, for example, W
(100 nm) / Al-Si (300 nm) / TiN
(100 nm) is a metal wiring layer having a three-layer laminated structure.

Next, in step S18, organic SOG is performed.
FIG. 4B shows the cross-sectional structure of the device in the state where the film 305 is etched back. As the etch back amount of the organic SOG film, a condition for completely removing the thick organic SOG film 305 on the wide wiring of the peripheral circuit portion was adopted, and the over etch amount was set to 15% to avoid the etch back residue. It was confirmed that the use of this processing condition can be applied to a manufacturing process of a semiconductor device having a wiring width of 0.36 μm and a space between wirings in a memory mat portion. The organic SOG film 404 was spin-coated and then baked in the same manner as in the above-mentioned embodiment,
Curing is performed for 30 minutes in a nitrogen atmosphere at 450 ° C. After that, as shown in FIG.
And step 20 are performed, and P-TEOS306 of the insulating film is performed.
And the upper wiring layer 307 was formed. Here, the upper wiring layer 3
07 is, for example, TiN / Al (containing 0.5% Cu) /
It is a metal wiring layer made of TiN.

Here, the results of examining the margin of the planarization process using organic SOG will be described. FIG.
FIG. 6A is a cross-sectional view of a memory device to which a conventional planarization process is applied, in the vicinity of a boundary between a memory mat portion and a peripheral circuit portion. A first inter-layer insulating film is formed on the metal wiring layer 402.
After forming the layer P-TEOS film 403, the organic SOG 404 of the intermediate second layer is formed. It is a condition that the sample in this state is subjected to an etch back treatment so that only the P-TEOS film remains on the metal wiring layer 402 to remove the organic SOG film 404.

This organic SOG film thickness is determined depending on the level difference of the base and the width of the wiring pattern. That is, organic SOG
The film is applied thicker in a portion lower than a wiring portion with a high altitude and thicker on a wide wiring than on a fine wiring. 0.4 μm
In the DRAM using the processing rule, the organic SOG film thickness on the wide wiring of the peripheral circuit portion is the maximum, so this is the organic SOG film thickness to be removed. Here, the thickness of the organic SOG film 404 in the flat portion where the pattern is not formed is set to 250.
nm.

Next, the thicker the P-TEOS film 403 on the metal wiring 402, the better. However, this maximum film thickness has a limit value that can cover the space between the minimum wirings without voids. That is, the maximum film thickness of the P-TEOS film 403 is determined by the step coverage (step coverage) of the P-TEOS given the dimensions of the wiring and the wiring space.

In the organic SOG etch-back process, the characteristics shown in FIG. 6 must be taken into consideration. This figure shows the characteristics of the etching rate of the organic SOG film and the P-TEOS film when the composition ratio of the etching gas is changed. The vertical axis represents the etching rate and the horizontal axis represents the etching gas CF.
₄ / CHF ₃ composition ratio (the composition ratio is proportional to the flow rate ratio)
And the characteristic line A is the organic S in the case where the P-TEOS film is present.
OG etching rate characteristics, characteristic line B is P-TEOS
The characteristic of the etching rate of only the organic SOG without the film and the characteristic line C are the characteristics of the etching rate of only the P-TEOS film. From the characteristic lines B and C, the P-TEOS film slightly increases as the gas composition ratio increases.
G greatly increases. Also, from the characteristic line A, P-TEOS
It can be seen that the exposure rate of organic SOG increases when exposed. This phenomenon is called a loading effect, and it is considered that oxygen is supplied to the etching gas. The etching gas composition ratio r ₀ used in the etch back process is the organic SOG when the P-TEOS film is exposed.
Of the P-TEOS film are equal to the etching rate of the P-TEOS film.

Here, the P-TEOS film thickness at the time of etch back in the conventional planarization process shown in FIG.
Calculate by formula. The target portion is a wiring portion having the smallest dimension of the memory mat portion where the remaining film thickness of the organic SOG is the smallest. In equation (1), the coefficient 0.5 is the minimum space of 1
/ 2, a is the minimum inter-wiring space, b is P-TEO
Step coverage of the S film, c is the film thickness of the organic SOG on the wide wiring having a low altitude, d is the remaining film thickness of the organic SOG on the fine wiring, e is the etching rate of the organic SOG without P-TEOS, and f is It is an etching rate of organic SOG when P-TEOS is exposed (P-TEOS is the same). Here, the minimum processing rule for fine wiring is 0.35 μm.
The case of, that is, the case of a = 0.35 μm is considered.
Regarding each value of b, c, d, e / f, b = 0.53 (value of dual frequency excitation CVD) based on experimental data,
c = 0.22 μm, d = 0.04 μm, and e / f (selection ratio) = 0.55 are adopted. Using these values, P-
The TEOS residual film thickness t (μm) is obtained as follows.

[0035]

## EQU00001 ## t = 0.5.times.a / b- (cd) / (e / f) (1) = 0.5.times.0.35 / 0.53- (0.22-0.04) ) /0.55=0.003 (μm) This value is extremely small, and it is not allowed to change the etchback amount in the slightly larger direction. Therefore, it is understood that the minimum space (processing rule) of about 0.35 μm is the limit in the conventional planarization process.

On the other hand, according to the method of manufacturing a multilayer wiring structure of the present invention using the process flow of FIG.
Before forming the conventional three-layer insulating film, the insulating film is previously arranged only on the upper surface of the lower wiring. When the thickness of this insulating film is G, the equation (1) is corrected to the equation (2).

[0037]

## EQU00002 ## t = 0.5.times.a / b- (cd) / (e / f) + G (2) Here, the insulating film previously arranged on the lower wiring layer is P-TE.
Assuming that the thickness G of the OS is 0.2 μm, (2)
From the formula, the residual film thickness t (μm) of P-TEOS is t = 0.2
It becomes 03 μm. As can be seen from this result, the film thickness (here, 0.2 μm) of the insulating film (P-TEOS) previously arranged on the lower wiring layer has an effect of directly expanding the etchback margin.

When the method of manufacturing a multilayer wiring structure according to the present invention having such an effect is applied to a multilayer wiring having a minimum processing dimension of 0.25 μm rule, the P-TEOS residual film thickness t is expressed by the equation (2). a = 0.25 μm, and the other values are applied as they are, b = 0.53, c = 0.
22 μm, d = 0.04 μm, e / f (selection ratio) = 0.
55 and G = 0.20 μm, t = 0.109 μ
m is obtained. The thickness of the remaining film thickness t corresponds to the amount of overetching of 10% in this etchback step (0.
04 μm) gives a sufficient processing margin.
Therefore, it can be seen that the multilayer wiring structure according to the present invention can cope with at least the multilayer wiring of the processing rule of 0.25 μm, which exceeds the limit of 0.35 μm which is the limit of the conventional planarization process.

Although the preferred embodiment of the present invention has been described above, the present invention is not limited to the above-described embodiment, and various design changes can be made without departing from the spirit of the present invention. It is. For example, although only the two-layer wiring is shown in the embodiment, it is clear that the present invention can be applied to the multi-layer wiring such as the three-layer wiring and the four-layer wiring. SRAM, ferroelectric memory, microcomputer, which requires wiring structure
It goes without saying that it is also applicable to logic devices and the like.

[0040]

As is apparent from the above-described embodiments, according to the multi-layer wiring structure of the present invention, the lower wiring layer having the first insulating film only on the upper surface excluding the side surface is used to form the conventional three-layer wiring structure. 0.25 μm due to the structure covered with an insulating film
It was possible to obtain a multi-layer wiring structure in which an insulating material having a fine wiring space was buried.

In addition, according to the method of manufacturing a multilayer wiring structure of the present invention, before the conventional three-layer insulating film is formed,
By forming the first insulating film only on the upper surface of the lower wiring layer in advance, the flattening of the interlayer insulating film applicable to the fine multilayer wiring with the minimum processing dimension of about 0.25 μm is performed by using the organic SOG etch back method. Since it can be manufactured, a ULSI product maintaining high reliability can be realized at low cost.

[Brief description of drawings]

FIG. 1 is a flow chart of a planarization process showing an embodiment of a method for manufacturing a multilayer wiring structure according to the present invention.

FIG. 2 is a diagram sequentially showing a cross-sectional structure of a main part of a main process of the processes shown in FIG.

FIG. 3 is a diagram sequentially showing a cross-sectional structure of a main part of a main step following FIG.

FIG. 4 is a view showing another embodiment of the method for manufacturing a multilayer wiring structure according to the present invention and sequentially showing cross-sectional structures of main steps.

FIG. 5 is a cross-sectional structure diagram of an essential part showing a planarization process in a conventional method for manufacturing a multilayer wiring structure.

FIG. 6 is a characteristic diagram illustrating a relationship between an etching rate of organic SOG and P-TEOS and an etching gas composition ratio.

[Explanation of symbols]

201 ... Substrate, 202 ... Metal wiring layer (lower wiring layer), 2
03 ... Insulating film (P-TEOS), 204 ... Photoresist, 205 ... DFP-TEOS (P-TEOS by dual frequency excitation parallel plate type CVD device), 206 ... Organic SO
G, 207 ... Insulating film (P-TEOS), 208 ... Metal wiring layer (upper wiring layer), 301 ... BPSG-formed substrate, 302 ... Metal wiring, 303 ... Insulating film (P-TEO)
S), 304 ... DFP-TEOS, 305 ... Organic SO
G, 306 ... Insulating film (P-TEOS), 307 ... Metal wiring layer (upper wiring layer), 401 ... BPSG formed substrate, 402 ... Metal wiring, 403 ... Insulating film (P-TEO)
S), 404 ... Organic SOG.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Seitaka Kato 5-20-1, Josuihonmachi, Kodaira-shi, Tokyo Inside the Semiconductor Business Division, Hitachi, Ltd. (72) Inventor, Masayuki Kojima 5-20-1 Incorporated company Hitachi, Ltd. Semiconductor Division (72) Inventor Nobuyoshi Kobayashi 5-20-1 Kamisuihonmachi, Kodaira-shi, Tokyo Hitachi Ltd. Semiconductor Division (72) Inventor Katsuhiko Hotta 5-22-1, Kamisuihonmachi, Kodaira-shi, Tokyo Inside Hitachi Microcomputer System Co., Ltd.

Claims (10)

[Claims] 1. A first device arranged in contact with an upper surface of a lower wiring.
Insulating film and a second insulating film that is arranged to cover the first insulating film and the lower wiring.
Insulating film, the coated glass film which is arranged at least in the low altitude portion of the surface of the second insulating film, and the coated glass film which is exposed on the coated glass film and the high altitude portion which are arranged in the low altitude portion. A third wiring film arranged so as to cover the insulation film, and a multi-layered insulation film including the third insulation film as an interlayer insulation film between the lower wiring and the upper wiring. 2. The first to third insulating films are silicon oxide films formed by a plasma chemical vapor deposition method.
The multilayer wiring structure described. 3. The multilayer wiring structure according to claim 1, wherein the coated glass film is an organic SOG film. 4. The multilayer wiring structure according to claim 2, wherein the first to third insulating films are low dielectric constant silicon oxide films containing fluorine. 5. A step of depositing a lower wiring layer, a step of depositing a first insulating film on the lower wiring layer, a step of forming a photoresist pattern on the first insulating film, and a first step on the upper surface. A step of forming a lower wiring having an insulating film deposited thereon, a step of depositing a second insulating film, a step of forming a coated glass film, a step of removing a part of the coated glass film, and a third insulating film And a step of depositing an upper wiring layer, the method for manufacturing a multilayer wiring structure. 6. The multilayer wiring structure according to claim 5, wherein the step of forming the lower wiring is a step of etching the first insulating film and the lower wiring layer using the photoresist pattern as a mask. 7. In the step of forming the lower wiring, the first insulating film is etched by using the photoresist pattern as a mask, the photoresist is removed, and the lower wiring layer is etched by using the first insulating film as a mask. It is a step 5.
The multilayer wiring structure described. 8. The first to third insulating films are silicon oxide films formed by a plasma chemical vapor deposition method.
A method for manufacturing the multilayer wiring structure described. 9. The method for manufacturing a multilayer wiring structure according to claim 5, wherein the coated glass film is an organic SOG film. 10. The method of manufacturing a multilayer wiring structure according to claim 8, wherein the first to third insulating films are low dielectric constant silicon oxide films containing fluorine.