JPH09246201A - Semiconductor integrated circuit device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress generation of a damage at the time of distribution of impurities as well as to control concentration distraction of impurities by forming a diffusion layer by making use of solid diffusion of impurities from an insulating film. SOLUTION: To make a diffusion layer 9 to be formed in a semiconductor region 1 being in contact with an insulating film 8 as well as the diffusion layer 9 is made to be formed in the semiconductor region 1 due to solid diffusion of impurities from the insulating film 8. For instance, a groove for a field insulating film is formed on a semiconductor substrate by using a selective etching technique and a silicon oxide film containing boron is formed by a CVD method so as to bury the insulating film 8 inside the groove. Next, the surface of the semiconductor substrate 1 in the region except the groove is made to be in an exposed state by using a CMP method. Next, heat treatment is performed so as to diffuse the impurities inside the insulating film 8 as the field insulating film sop as to form the diffusion layer 9 with a prescribed impurity concentration to become a channel stopper layer.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and its manufacturing method.

[0002]

2. Description of the Related Art In semiconductor integrated circuit devices, higher integration and higher performance have been promoted.

By the way, the present inventor has studied a method of manufacturing a semiconductor integrated circuit device. The following is a technique studied by the present inventors, and the outline is as follows.

That is, as the performance of a semiconductor integrated circuit device has recently been improved, an ion implantation technique using an impurity ion implantation method is used in the manufacturing process of the diffusion layer.

In particular, a MOS in a semiconductor integrated circuit device
When forming a semiconductor region to be a source / drain of an FET on a semiconductor substrate by a diffusion layer, an impurity having a high concentration equal to or higher than a solid solubility limit is ion-implanted into the semiconductor substrate, and then an annealing process is performed to remove the impurity. It is formed by diffusing into.

As a method of forming a shallow pn junction,
Short-time annealing technology is being studied.

Further, accurate prediction of impurity concentration distribution has become an extremely important technique in predicting device characteristics.

As a reference of the ion implantation technique for forming the diffusion layer, for example, December 10, 1988.
Some are described in "Electronic Materials, December 1988, Supplement," p56-p66, published by Japan Industrial Research Association.

[0009]

However, the present inventor has found that the above-described method for manufacturing a semiconductor integrated circuit device has various problems.

That is, in the diffusion process including the oxidation step, it is difficult to accurately estimate the impurity distribution at the interface between the silicon oxide film and the diffusion layer due to the segregation phenomenon of impurities.

Further, when an impurity is implanted into the semiconductor substrate by an ion implantation method, the crystal of the semiconductor substrate is damaged, and the crystal damage causes the impurity concentration distribution to be controlled by accelerated diffusion. There is a problem that it is difficult and a leak current is generated in the pn junction region.

An object of the present invention is to provide a semiconductor integrated circuit device capable of suppressing the occurrence of damage during diffusion of impurities and controlling the concentration distribution of impurities with high accuracy, and a method of manufacturing the same.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0014]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, according to the method of manufacturing a semiconductor integrated circuit device of the present invention, an insulating film such as a silicon oxide film is formed on the surface of a semiconductor region such as a semiconductor substrate, and then boron or the like is formed on the insulating film by an ion implantation method or the like. The method includes a step of adding impurities and a step of diffusing the impurities added to the insulating film into the semiconductor region by heat treatment to form a diffusion layer in the semiconductor region.

[0016]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and redundant description will be omitted.

(Embodiment 1) FIGS. 1 to 4 are sectional views showing a process of manufacturing a diffusion layer in a semiconductor integrated circuit device according to an embodiment of the present invention. The semiconductor integrated circuit device and the manufacturing method thereof according to the present invention will be specifically described with reference to FIG.

First, as shown in FIG. 1, a semiconductor substrate 1 such as p-type single crystal silicon is prepared, and an insulating film 2 is formed on the surface of the semiconductor substrate 1 as shown in FIG.

As the insulating film 2, for example, a silicon oxide film is CV.
It is formed by the D (Chemical Vapor Deposition) method.

Next, as shown in FIG. 3, an impurity 3 such as boron (B) is added (doping) to the insulating film 2 by an ion implantation technique using an ion implantation method. In this case, impurities 3 such as boron are added to the insulating film 2.
Forming a doped region 4 of
The impurity 3 in the doping region 4 is used to form a diffusion layer, which will be described later, on the semiconductor substrate 1 below the insulating film 2.

Therefore, when the diffusion layer is formed by the impurities 3 of the doping region 4, the doping region 4 may be formed in the region of the insulating film 2, but the doping region 4 is subject to the condition of the ion implantation technique. By controlling the film formation in the region of the insulating film 2 close to the interface between the semiconductor substrate 1 and the insulating film 2, an excellent diffusion layer can be formed.

When the doping region 4 is formed inside the insulating film 2 by controlling the conditions of the ion implantation technique,
By setting the condition of the ion implantation technique so that the impurity 3 is not doped inside the semiconductor substrate 1, it is possible to prevent the semiconductor substrate 1 from being damaged due to the ion implantation of the impurity 3.

Thereafter, as shown in FIG. 4, heat treatment is performed to diffuse the impurities 3 inside the insulating film 2 into the semiconductor substrate 1 to form a diffusion layer 5 having a predetermined impurity concentration. In this case, the heat treatment for diffusing the impurities 3 can be performed using an annealing device or the like,
In order to control the impurity concentration and shape of the diffusion layer 5 with high accuracy, RTA (Rapid Thermal Annealing) that can perform diffusion processing at high temperature and in a short time is used, and the impurity concentration and shape of the diffusion layer 5 can be adjusted with high accuracy. The predetermined diffusion layer 5 is formed under the control.

The diffusion layer 5 described above can be used in various regions of the semiconductor region such as the source and drain of the MOSFET or the base of the bipolar transistor in the semiconductor integrated circuit device.

According to the method of manufacturing the diffusion layer in the semiconductor integrated circuit device of the present embodiment described above, the impurities 3 inside the insulating film 2 formed on the surface of the semiconductor substrate 1 are solid-phase diffused to the semiconductor substrate. By forming the diffusion layer 5 by diffusing into 1, the segregation phenomenon of the impurities 3 can be prevented. Therefore, the diffusion layer 5 can be formed by controlling the impurity concentration and the concentration distribution according to the design specifications with high accuracy. it can.

Further, according to the method of manufacturing the diffusion layer in the semiconductor integrated circuit device of the present embodiment, the impurity 3 such as boron inside the insulating film 2 is diffused into the semiconductor substrate 1 by the solid phase diffusion method. By using RTA when forming the layer 5, the impurity concentration and shape of the diffusion layer 5 can be controlled with high accuracy and the diffusion layer 5 can be formed in a short time.

Further, according to the method of manufacturing the diffusion layer in the semiconductor integrated circuit device of the present embodiment, the impurities 3 inside the insulating film 2 formed on the surface of the semiconductor substrate 1 are solid-phase diffused to the semiconductor substrate. Since the diffusion layer 5 is formed by diffusing to 1, the impurities 3 are not ion-implanted into the semiconductor substrate 1 when forming the diffusion layer 5. As a result, damage to the crystal of the semiconductor substrate 1 due to the implantation of the impurities 3 can be prevented, and the enhanced diffusion phenomenon can be prevented. Therefore, the impurity concentration distribution of the diffusion layer 5 can be controlled with high accuracy and at the pn junction. Leakage current can be prevented.

Further, according to the method of manufacturing the diffusion layer in the semiconductor integrated circuit device of the present embodiment, the impurities 3 in the inside of the insulating film 2 formed on the surface of the semiconductor substrate 1 are solid-phase diffused to the semiconductor substrate. Since the diffusion layer 5 is formed by diffusing into 1, the various modes described below can be applied.

That is, as the semiconductor substrate 1, not only a semiconductor substrate made of p-type single crystal silicon but also a semiconductor substrate made of n-type single crystal silicon can be applied. In addition to the aspect in which the diffusion layer 5 is formed on the semiconductor substrate 1, the SOI (Silicon
Diffusion layer 5 in the semiconductor region of the substrate
It is possible to apply a mode of forming the. As the insulating film 2,
Other than the silicon oxide film, an insulating film such as a silicon nitride film can be applied.

Impurities 3 added to the inside of the insulating film 2
Can be a p-type impurity such as boron or an n-type impurity such as phosphorus (P). Impurities 3 inside the insulating film 2
In addition to the impurity 3 ion implantation method, 2B
By utilizing a chemical reaction such as H ₃ = 2B + 3H ₂ or 2PH ₃ = 2P + 3H ₂ , impurities 3 such as boron or phosphorus are removed while insulating film 2 is formed while forming a silicon oxide film.
Or a silicon oxide film containing boron or a silicon oxide film containing phosphorus, etc.
A mode in which impurities are added to the insulating film 2 formed by the D method can be applied.

Further, in order to add the impurity 3 into the insulating film 2, the ion implantation method, the addition of the impurity 3 such as boron or phosphorus to the insulating film 2 while forming the silicon oxide film, and the like are independently performed. It is possible to select and perform a mode in which they are combined in accordance with design specifications.

The method of forming the insulating film 2 is different from the mode of forming the insulating film 2 such as a silicon oxide film by using the CVD method which can be formed in a low temperature state where the characteristics of the semiconductor substrate 1 are not changed. Alternatively, a mode in which a thermal silicon oxide film is formed by thermal oxidation of the semiconductor substrate 1 can be applied.

(Embodiment 2) FIGS. 5 to 8 are sectional views showing the steps of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention. The semiconductor integrated circuit device and the manufacturing method thereof according to the present invention will be specifically described with reference to FIG.

First, as shown in FIG. 5, a semiconductor substrate 1 made of, for example, p-type single crystal silicon is prepared, and a photoresist film 6 is formed on the surface thereof. Next, a pattern serving as an etching mask when forming a groove for a field insulating film is formed on the photoresist film 6 by using a photolithography technique.

Next, using the photoresist film 6 as an etching mask, a selective etching technique is used to form a groove 7 for a field insulating film in the semiconductor substrate 1.

Next, as shown in FIG. 6, after removing the unnecessary photoresist film 6, an insulating film 8 is formed on the semiconductor substrate 1 and the groove 7 is filled with the insulating film 8. In this case, as the insulating film 8, for example, a silicon oxide film containing boron is formed by the CVD method.

The mode of adding impurities such as boron to the insulating film 8 can be various modes as in the first embodiment.

Next, as shown in FIG. 7, CMP (Chemic
al mechanical polishing), the insulating film 8 is embedded in the groove 7 of the semiconductor substrate 1 and the surface of the semiconductor substrate 1 in the region other than the groove 7 is exposed. . Insulating film 8 embedded in the groove 7
Is used as a field insulating film in a semiconductor integrated circuit device.

In this case, the insulating film 8 is formed by the CMP method.
Since the surface of the insulating film 8 is polished from the surface thereof, the surface of the insulating film 8 embedded in the groove 8 and the surface of the semiconductor substrate 1 are polished even if the surface of the insulating film 8 is uneven and is not flattened. It can be flattened later.

It is possible to adopt a mode in which part of the insulating film 8 is removed by using an etching method or a method combining the etching method and the CMP method.

Next, as shown in FIG. 8, heat treatment is performed to diffuse the impurities inside the insulating film 8 as the field insulating film into the semiconductor substrate 1 to form the diffusion layer 9 having a predetermined impurity concentration. Form. The diffusion layer 9 is used as a channel stopper layer in a semiconductor integrated circuit device.

In this case, the heat treatment for diffusing the impurities inside the insulating film 8 as the field insulating film can be carried out by using an annealing device or the like, but the impurity concentration and shape of the diffusion layer 9 can be accurately adjusted. For control, an RTA capable of performing a diffusion process at a high temperature for a short time is used, and the impurity concentration and shape of the diffusion layer 9 are controlled with high accuracy to form a predetermined diffusion layer 9.

Next, although not shown in the drawing, after performing various wafer processes according to design specifications to form semiconductor elements such as MOSFETs or bipolar transistors in the region of the semiconductor substrate 1, the semiconductor elements are further formed thereon. The manufacturing of the semiconductor integrated circuit device is completed by forming a multi-layer wiring layer on.

According to the method of manufacturing the semiconductor integrated circuit device of the present embodiment described above, the impurities inside the insulating film 8 as the field insulating film formed on the surface of the semiconductor substrate 1 are used for the semiconductor by the solid phase diffusion method. By forming the diffusion layer 9 by diffusing into the substrate 1, the segregation phenomenon of impurities can be prevented, so that the impurity concentration and the concentration distribution according to the design specifications can be controlled with high accuracy and the diffusion layer as a channel stopper layer can be controlled. 9
Can be manufactured.

According to the method of manufacturing the semiconductor integrated circuit device of this embodiment, when the impurities inside the insulating film 8 are diffused into the semiconductor substrate 1 by the solid phase diffusion method to form the diffusion layer 9, Since RTA is used, the impurity concentration and shape of the diffusion layer 9 can be controlled with high accuracy, and the diffusion layer 9 can be formed in a short time.

Further, according to the method of manufacturing the semiconductor integrated circuit device of the present embodiment, the insulating film 8 as the field insulating film is embedded in the groove 7 of the semiconductor substrate 1. Therefore, the insulating film 8 as the field insulating film 8 is formed. In addition to being capable of fine processing, it is possible to form a high-performance insulating film 8 for element isolation in a small area.

(Third Embodiment) FIGS. 9 to 11 are sectional views showing a manufacturing process of a semiconductor integrated circuit device according to another embodiment of the present invention. The semiconductor integrated circuit device and the manufacturing method thereof according to the present invention will be specifically described with reference to FIG.

First, as shown in FIG. 9, an insulating film 8 having impurities such as boron added to a selective region of the semiconductor substrate 1 is formed by using the same manufacturing process as that of the second embodiment. It is formed as a field insulating film. Next, the insulating film 10 such as a silicon oxide film is formed on the semiconductor substrate 1 by the CVD method.

Next, as shown in FIG. 10, the film thickness of the insulating film 10 is reduced by using a CMP method, an etching method, or a combination thereof to form the insulating film 10 having a predetermined film thickness. To do. In the manufacturing process of the insulating film 10 described above, the thin insulating film 10 having a predetermined thickness is used.
If it can be formed, this manufacturing process can be omitted.

Next, after the photoresist film 11 is formed on the surface of the insulating film 10, the insulating film 10 other than the insulating film 8 is removed by using the photolithography technique and the selective etching technique, thereby insulating the insulating film 10. The insulating film 10 is left only on the film 8.

Next, as shown in FIG. 11, after removing the unnecessary photoresist film 11, heat treatment is performed to diffuse the impurities inside the insulating film 8 as the field insulating film into the semiconductor substrate 1. Thus, the diffusion layer 9 having a predetermined impurity concentration is formed. The diffusion layer 9 is used as a channel stopper layer in a semiconductor integrated circuit device.

In addition, the insulating film 8 as a field insulating film.
The heat treatment for diffusing the impurities in the inside can be performed using an annealing device or the like, but a short-time treatment such as RTA is used so that the impurities added to the insulating film 8 do not penetrate through the insulating film 10. As a condition, impurities are prevented from being diffused to the outside and being added to the semiconductor substrate 1 or the like whose surface is exposed.

Also, the insulating film 8 as a field insulating film.
The heat treatment for diffusing the impurities inside is formed by using a short-time treatment such as RTA and controlling the impurity concentration and shape of the diffusion layer 9 with high accuracy to form a predetermined diffusion layer 9.

Next, although not shown, various wafer processes are performed in accordance with design specifications to form semiconductor elements such as MOSFETs or bipolar transistors in the region of the semiconductor substrate 1, and then the semiconductor elements are formed thereon. A multi-layer wiring layer is formed on the substrate, and the manufacturing of the semiconductor integrated circuit device is completed.

According to the method of manufacturing the semiconductor integrated circuit device of the present embodiment, since the insulating film 10 is provided on the insulating film 8, the impurities added to the insulating film 8 penetrate through the insulating film 10. Since it is possible to prevent the impurities from being released to the outside and being added to the semiconductor substrate 1 or the like whose surface is exposed, it is possible to prevent unnecessary impurities from being added.

Further, according to the method of manufacturing a semiconductor integrated circuit device of the present embodiment, the impurity added to the insulating film 8 can be prevented from being released to the outside by the insulating film 10, so that the diffusion layer 9 is formed. The amount of impurities to be formed can be controlled with high accuracy. As a result, the impurity concentration and shape of the diffusion layer 9 can be controlled with high accuracy to form the predetermined diffusion layer 9.

(Embodiment 4) FIGS. 12 to 15 are sectional views showing the steps of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention. The semiconductor integrated circuit device and the manufacturing method thereof according to the present invention will be specifically described with reference to FIG.

First, as shown in FIG. 12, an insulating film 8 as a field insulating film and a channel stopper layer are formed in selective regions of the semiconductor substrate 1 by using the same manufacturing process as in the second embodiment. The diffusion layer 9 is formed. Next, the insulating film 12 such as a silicon oxide film is formed on the semiconductor substrate 1 by the CVD method.

Next, the insulating film 12 is doped with impurities such as boron by an ion implantation technique using an ion implantation method. In this case, a doping region doped with an impurity such as boron is formed in the region of the insulating film 12, and a MOSFET is formed on the semiconductor substrate 1 below the insulating film 12 by a manufacturing process described later using the impurity in the doping region. A diffusion layer is formed as a channel region for controlling the threshold voltage.

Next, as shown in FIG. 13, by using the CMP method, the etching method or a combination thereof, the thickness of the insulating film 12 is reduced to form the insulating film 12 having a predetermined thickness, and the gate is formed. The insulating film 12 as an insulating film is formed. In the manufacturing process of the insulating film 12 described above, when the thin insulating film 12 having a predetermined film thickness can be formed, this manufacturing process can be omitted.

Next, the gate electrode 13 and the gate electrode 1 made of, for example, a polycrystalline silicon film or the like are formed on the insulating film 12.
3, an insulating film 14 such as a silicon oxide film is formed, and then the insulating film 14, the gate electrode 13 and the insulating film 12 as a gate insulating film are selectively removed using a photolithography technique and a selective etching technique. Gate electrode 13
And a pattern of the insulating film 12 as a gate insulating film is formed. Next, the sidewall insulating film 15 made of a silicon oxide film or the like is formed on the sidewall of the gate electrode 13.

Next, as shown in FIG. 14, the gate electrode 1
An impurity such as phosphorus is ion-implanted by an ion implantation method into the semiconductor substrate 1 whose surface is exposed in a self-aligned state using 3 as an impurity diffusion mask.

Next, heat treatment is performed to diffuse the impurities in the insulating film 12 into the semiconductor substrate 1 to form a diffusion layer 16 having a predetermined impurity concentration, and the semiconductor substrate 1 is ion-implanted. Diffusion layers 17 serving as a source and a drain are formed by diffusing the existing impurities. In this case, the heat treatment for diffusing the impurities can be performed using an annealing device or the like, but RTA is used to control the impurity concentration and shape of the diffusion layer 16 with high accuracy, and the impurity of the diffusion layer 16 is used. A predetermined diffusion layer 16 is formed to control the threshold voltage of the MOSFET by controlling the concentration and shape with high accuracy.

The heat treatment for forming the diffusion layer 16 can be performed after the impurity is added to the insulating film 12 as the gate insulating film, so that the heat treatment for forming the diffusion layer 16 and the source and drain are performed. The heat treatment for forming the diffusion layer 17 can be performed by another heat treatment applying heat treatment conditions according to each design specification. The manufacturing process for forming the diffusion layer 17 serving as the source and the drain can use the mode using the method for manufacturing the diffusion layer of the first embodiment described above.

Next, as shown in FIG. 15, the semiconductor substrate 1
After forming an insulating film 18 such as a silicon oxide film on the
After forming a contact hole in the insulating film 18, a contact electrode 19 made of aluminum or the like is formed.

Next, although not shown, various wafer processes are performed according to design specifications to form a multilayer wiring layer on the semiconductor substrate 1 and the manufacturing of the semiconductor integrated circuit device is completed. .

According to the method of manufacturing the semiconductor integrated circuit device of this embodiment, the impurity is added to the insulating film 12 as the gate insulating film, and the semiconductor under the insulating film 12 is diffused by diffusing the impurity. Since the diffusion layer 16 as the channel region for controlling the threshold voltage of the MOSFET is formed on the substrate 1, the impurity concentration and shape of the diffusion layer 16 can be controlled with high accuracy to achieve a predetermined diffusion corresponding to the device characteristics. Layer 16 can be formed.

Although the invention made by the present inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above-mentioned embodiments, and various modifications can be made without departing from the scope of the invention. It goes without saying that it can be changed.

For example, a semiconductor integrated circuit device and a method of manufacturing the same according to the present invention include a MOSFET, a CMOSFET, a bipolar transistor or a BiMOS or BiCMOS in which a MOSFET and a bipolar transistor are combined in a semiconductor region such as a semiconductor substrate or an SOI substrate.
The present invention can be applied to a semiconductor integrated circuit device having various semiconductor elements such as structures and a manufacturing method thereof.

[0070]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

(1). According to the method of manufacturing the diffusion layer in the semiconductor integrated circuit device of the present invention, the diffusion layer is formed by diffusing the impurities inside the insulating film formed on the surface of the semiconductor substrate into the semiconductor substrate by the solid phase diffusion method. By doing so, the segregation phenomenon of impurities can be prevented, so that the diffusion layer can be formed by controlling the impurity concentration and the concentration distribution according to the design specifications with high accuracy.

Further, according to the method of manufacturing the diffusion layer in the semiconductor integrated circuit device of the present invention, the RTA is used when the diffusion layer is formed by diffusing the impurities inside the insulating film into the semiconductor substrate by the solid phase diffusion method. Since it is used, the impurity concentration and shape of the diffusion layer can be controlled with high accuracy to form a shallow junction, and the diffusion layer can be formed in a short time.

Further, according to the method of manufacturing the diffusion layer in the semiconductor integrated circuit device of the present invention, impurities are not ion-implanted into the semiconductor substrate when forming the diffusion layer, so that the crystals of the semiconductor substrate are damaged by the impurities. Can be prevented. As a result, the multiplication and diffusion phenomenon can be prevented, so that the impurity concentration distribution in the diffusion layer can be controlled with high accuracy and the pn
Leakage current at the junction can be prevented.

(2). According to the method for manufacturing a semiconductor integrated circuit device of the present invention, the diffusion layer is formed by diffusing the impurities inside the insulating film as the field insulating film formed on the surface of the semiconductor substrate into the semiconductor substrate by the solid phase diffusion method. By doing so, the segregation phenomenon of impurities can be prevented, so that it is possible to form the diffusion layer as the channel stopper layer by controlling the impurity concentration and the concentration distribution according to the design specifications with high accuracy.

Further, according to the method of manufacturing a semiconductor integrated circuit device of the present invention, since the insulating film as the field insulating film is embedded in the groove of the semiconductor substrate, the insulating film as the field insulating film can be finely processed. A high-performance insulating film for element isolation can be formed in a small area.

(3). According to the method for manufacturing a semiconductor integrated circuit device of the present invention, in the heat treatment for forming the diffusion layer, another insulating film is provided on the insulating film to which the impurity is added, and therefore, it is added to the insulating film. Since it is possible to prevent the existing impurities from penetrating the insulating film and being released to the outside and being added to the semiconductor substrate or the like whose surface is exposed, unnecessary addition of impurities can be prevented.

Further, according to the method for manufacturing a semiconductor integrated circuit device of the present invention, since the impurity added to the insulating film can be prevented from being released to the outside by another insulating film, the diffusion layer is formed. The amount of impurities can be controlled with high precision. As a result, the impurity concentration and shape of the diffusion layer can be controlled with high accuracy to form a predetermined diffusion layer.

(4). According to the method for manufacturing a semiconductor integrated circuit device of the present invention, an impurity is added to the insulating film serving as the gate insulating film, and the impurity is diffused to form a semiconductor substrate below the insulating film serving as the gate insulating film. Since the diffusion layer is formed as the channel region for controlling the threshold voltage of the MOSFET, the impurity concentration and shape of the diffusion layer can be controlled with high accuracy to form a predetermined diffusion layer corresponding to the device characteristics. .

[Brief description of drawings]

FIG. 1 is a fragmentary cross-sectional view showing a step of manufacturing a diffusion layer in a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 2 is a fragmentary cross-sectional view showing a step of manufacturing a diffusion layer in a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 3 is a fragmentary cross-sectional view showing a step of manufacturing a diffusion layer in a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 4 is a fragmentary cross-sectional view showing a step of manufacturing a diffusion layer in a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 5 is a main-portion cross-sectional view showing the manufacturing process of a semiconductor integrated circuit device which is another embodiment of the present invention;

FIG. 6 is a main-portion cross-sectional view showing the manufacturing process of a semiconductor integrated circuit device which is another embodiment of the present invention;

FIG. 7 is a main-portion cross-sectional view showing the manufacturing process of a semiconductor integrated circuit device which is another embodiment of the present invention;

FIG. 8 is a main-portion cross-sectional view showing the manufacturing process of a semiconductor integrated circuit device which is another embodiment of the present invention;

FIG. 9 is a fragmentary cross-sectional view showing a manufacturing step of the semiconductor integrated circuit device according to another embodiment of the present invention;

FIG. 10 is a fragmentary cross-sectional view showing a manufacturing step of a semiconductor integrated circuit device according to another embodiment of the present invention;

FIG. 11 is a fragmentary cross-sectional view showing a manufacturing step of the semiconductor integrated circuit device according to another embodiment of the present invention;

FIG. 12 is a main-portion cross-sectional view showing the manufacturing process of a semiconductor integrated circuit device which is another embodiment of the present invention;

FIG. 13 is a main-portion cross-sectional view showing the manufacturing process of a semiconductor integrated circuit device which is another embodiment of the present invention;

FIG. 14 is a main-portion cross-sectional view showing the manufacturing process of a semiconductor integrated circuit device which is another embodiment of the present invention;

FIG. 15 is a main-portion cross-sectional view showing the manufacturing process of a semiconductor integrated circuit device which is another embodiment of the present invention;

[Explanation of symbols]

 1 semiconductor substrate 2 insulating film 3 impurities 4 doping region 5 diffusion layer 6 photoresist film 7 groove 8 insulating film 9 diffusion layer 10 insulating film 11 photoresist film 12 insulating film 13 gate electrode 14 insulating film 15 sidewall insulating film 16 diffusion layer 17 Diffusion layer 18 Insulating film 19 Contact electrode

Front Page Continuation (72) Inventor Niko Aoyama 2326 Imai, Ome City, Tokyo, Hitachi Device Development Center (72) Inventor Hisaaki Kunitomo 2326 Imai, Ome City, Tokyo Hitachi, Ltd. Device Development Center (72) ) Inventor Hiroo Masuda 2326 Imai, Ome City, Tokyo Metropolitan Government Device Development Center, Hitachi, Ltd.

Claims (9)

[Claims] 1. A diffusion layer is formed in a semiconductor region in contact with an insulating film, and the diffusion layer is formed in the semiconductor region by solid phase diffusion of impurities from the insulating film. Semiconductor integrated circuit device. 2. The semiconductor integrated circuit device according to claim 1, wherein the insulating film is a gate insulating film in a MOSFET. 3. The semiconductor integrated circuit device according to claim 1, wherein the insulating film is a field insulating film. 4. The semiconductor integrated circuit device according to claim 1, wherein the insulating film is embedded in a groove formed in a selective region of the semiconductor region. apparatus. 5. A step of forming an insulating film on a surface of a semiconductor region, a step of adding an impurity to the insulating film, and a heat treatment to diffuse the impurity added to the insulating film into the semiconductor region. And a step of forming a diffusion layer in the semiconductor region, the method for manufacturing a semiconductor integrated circuit device. 6. The method of manufacturing a semiconductor integrated circuit device according to claim 5, wherein the step of forming an insulating film on the surface of the semiconductor region includes forming a groove in a selective region of the semiconductor region and then forming the trench in the groove. A method of manufacturing a semiconductor integrated circuit device, comprising a step of burying an insulating film. 7. The method for manufacturing a semiconductor integrated circuit device according to claim 5, further comprising a step of forming another insulating film on the insulating film after the step of adding impurities to the insulating film. A method for manufacturing a semiconductor integrated circuit device, comprising: 8. The method for manufacturing a semiconductor integrated circuit device according to claim 5, wherein the heat treatment is
A method for manufacturing a semiconductor integrated circuit device, which is performed using RTA. 9. The method for manufacturing a semiconductor integrated circuit device according to claim 5, wherein the insulating film is
A method of manufacturing a semiconductor integrated circuit device, which is characterized by being formed by a CVD method.