JPH09245489A - Ferroelectric memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a ferroelectric memory of a shadow RAM or the like which improves an operation margin checking increase in cost. SOLUTION: First switching means N8-NB are arranged to make a selective connection between non-inversion and inversion signal lines of complementary bit lines BLO*-BLn* of a memory array ARYL, for instance, to be selectively turned ON and made active during the reading operation in a recall mode of a non-volatile mode and non-inversion and inversion signal lines of corresponding complementary bit lines BS0*-BSn* of other memory arrays ARYR kept non-active. The first switching means is turned OFF immediately before the operation of a sense amplifier SA. At the same time, the means concurrently serves as shared MOSFET when a shadow RAM employs a shared sense system.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ferroelectric memory, for example, a shadow RAM (random access memory) that can be selectively used in a nonvolatile mode and a volatile mode.
In addition, the present invention relates to a technology that is particularly effective in reducing the chip size.

[0002]

2. Description of the Related Art Ferroelectric capacitors and address selection M
A memory array in which ferroelectric-type memory cells including an OSFET (metal oxide semiconductor field-effect transistor; generically referred to as an insulated gate field-effect transistor in this specification) is arranged in a grid pattern is provided. There is a ferroelectric memory as its basic constituent element. Also,
As a kind of ferroelectric memory, the plate potential of the ferroelectric capacitor and the precharge potential of the bit line are operated in the volatile mode as an intermediate potential between the power supply voltage VCC and the ground potential VSS during normal operation, and when the power is cut off. A so-called shadow RAM which operates in a non-volatile mode with the plate potential of the ferroelectric capacitor as the ground potential VSS is described in, for example, Japanese Patent Laid-Open No. 7-21784.

[0003]

In the shadow RAM described above, reading and writing of held data in the non-volatile mode is performed as follows.
The held data is read out by using the polarization of the ferroelectric substance between the electrodes of the ferroelectric capacitor.
After the bit line is precharged to the ground potential VSS to be in a floating state, the word line is selected to turn on the address selection MOSFET, and the potential change of the bit line due to the selective charge flow into the ferroelectric capacitor is performed. It is done by detecting. In other words, in the read operation in the non-volatile mode, the ground potential charged in the parasitic capacitance of the bit line is charge-shared with the interelectrode capacitance of the ferroelectric capacitor of the selected memory cell to make the ferroelectric capacitor. An electric field is applied between the electrodes of the electrodes, and the movement of charges accompanying the transition of the polarization state of the ferroelectric substance is utilized. Therefore, the amount of signal obtained on the bit line in the normal operation region is the electric field applied between the electrodes of the ferroelectric capacitor due to charge sharing, that is, the parasitic capacitance C of the bit line.
The larger the ratio of d to the interelectrode capacitance Cs of the ferroelectric capacitor, that is, the capacitive coupling ratio Cd / Cs, the larger.

On the other hand, reading and writing of the held data in the volatile mode of the shadow RAM is performed by utilizing the charges accumulated in the interelectrode capacitance of the ferroelectric capacitor due to the polarization of the ferroelectric substance, and the read operation in the volatile mode is performed. , For example, after precharging the bit line to an intermediate potential between the power supply voltage VCC and the ground potential VSS to bring it into a floating state, then selecting a word line to turn on the address selection MOSFET to turn on the interelectrode capacitance of the ferroelectric capacitor. This is performed by detecting the potential change of the bit line due to the movement of the charges accumulated in the. In other words, the read operation in the volatile mode is performed by sharing the charge accumulated in the interelectrode capacitance of the ferroelectric capacitor with the polarization of the ferroelectric substance with the parasitic capacitance of the bit line. In contrast to the case of the non-volatile mode, the amount of signal obtained on the bit line increases as the capacitive coupling ratio Cd / Cs decreases.

As described above, the signal amount on the bit line during the read operation in the nonvolatile mode and the volatile mode of the shadow RAM, that is, the operation margin of the shadow RAM is
The contradictory conditions for the capacitive coupling ratio Cd / Cs are required, but in order to deal with this, it is disclosed in JP-A-7-147.
In 094, dummy capacitors having a predetermined electrostatic capacitance are separately provided, and these dummy capacitors are connected to each bit line of the memory array during the read operation in the non-volatile mode and separated from each bit line during the read operation in the volatile mode. , A method of optimizing the capacitive coupling ratio in the non-volatile mode and the volatility mode respectively to increase the operation margin of the shadow RAM in both modes has been proposed. However, when this method is adopted, a dummy capacitor having a relatively large electrostatic capacity is additionally added, which increases the chip size of the shadow RAM and hinders its cost reduction.

An object of the present invention is to provide a ferroelectric memory such as a shadow RAM which has an improved operation margin while suppressing the cost increase.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[0008]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. That is, a ferroelectric RAM such as a shadow RAM, which has a plurality of memory arrays in which ferroelectric memory cells are arranged in a lattice and is selectively activated, can be selectively used in a volatile mode and a nonvolatile mode. In the body memory, for example, between each bit line of the memory array that is selectively turned on and activated during a read operation in the recall mode of the non-volatile mode and the corresponding bit line of another memory array that is not activated. First switch means for selectively connecting is provided. Further, when the shadow RAM adopts the shared sense system while the first switch means is turned off immediately before the operation of the sense amplifier, the shared MOSFET is also used as the first switch means. Further, when a plurality of pairs of shared sense type memory arrays are provided, a second switch means that is selectively turned on under the same condition as the first switch means is provided between the memory array pairs. If the capacity is still insufficient, for example, in the sense amplifier, a third line is provided for each bit line of the memory array that is activated.
A predetermined number of dummy capacitors are provided which are selectively connected via the switch means.

According to the above means, the load on the sense amplifier is reduced, the power supply noise accompanying the operation of the unit amplifier circuit is suppressed, and the parasitic capacitance of the memory array which is not activated is used as the dummy capacitance. By utilizing this, it is possible to optimize the capacitance coupling ratios in the non-volatile mode and the volatile mode of the shadow RAM and the like, and thereby a sufficient read signal amount can be secured. As a result, the shadow R is designed to improve the operation margin while suppressing the increase in the chip size and the cost.
A ferroelectric memory such as AM can be realized.

[0010]

FIG. 1 is a block diagram showing an embodiment of a shadow RAM (ferroelectric memory) to which the present invention is applied. 2 shows a partial circuit diagram of an embodiment of the memory array included in the shadow RAM of FIG. 1 and its peripheral portion, and FIG. 3 shows a ferroelectric circuit constituting the memory array of FIG. An information retention characteristic diagram of one embodiment of a body memory cell is shown. Further, FIG. 4 shows a conceptual diagram of one embodiment for explaining the transition of the operation mode of FIG. Based on these figures, first, the outline of the configuration and operation of the shadow RAM of this embodiment, the information retention characteristics of the ferroelectric memory cell, and the operation mode of the shadow RAM will be described. The circuit elements of FIG. 2 and the circuit elements of each block of FIG. 1 are not particularly limited, but are formed on a single semiconductor substrate surface such as single crystal silicon by a known MOSFET integrated circuit manufacturing technique. It is formed. Further, in the following circuit diagrams, MOSFETs having an arrow at the channel (back gate) portion are of a P-channel type, and are distinguished from N-channel MOSFETs without an arrow.

In FIG. 1, the shadow RA of this embodiment is shown.
M is not particularly limited, but a pair of memory arrays ARYL and AR which adopt a shared sense system and are arranged on both sides of the sense amplifier SA and share the sense amplifier SA are provided.
YR and X provided corresponding to these memory arrays
Address decoders XDL and XDR, and memory array A
And a Y address decoder YD arranged on the left side of RYL.

The memory arrays ARYL and ARYR are so-called 2-cell / 2-transistor type arrays, and as shown in FIG. 2, m + 1 arranged in parallel in the vertical direction.
Book word lines WL0 to WLm or WR0 to WRm
And n + 1 sets of complementary bit lines BL0 * to BLn * or BR0 * to BRn * arranged in parallel in the horizontal direction.
(Here, for example, the non-inverted bit line BL0T and the inverted bit line BL0R are collectively denoted by an asterisk such as the complementary bit line BL0 *. Also, when it is enabled, it is selectively set to a high level. A so-called non-inverted signal or the like is indicated by adding T to the end of its name, and a so-called inverted signal or the like that is selectively brought to a low level when it is valid is added with B at the end of its name. The same shall apply hereinafter). At the intersection of these word lines and complementary bit lines, a ferroelectric capacitor Ct or Cb and an address selection MOSFET Qt or Qb (m +
1) × (n + 1) pairs of ferroelectric memory cells are arranged in a grid pattern.

One electrode of the ferroelectric capacitors Ct or Cb of the m + 1 pairs of memory cells arranged in the same column of the memory arrays ARYL and ARYR serves as an information storage node of the corresponding address selection MOSFET Qt or Qt.
b through complementary bit lines BL0 * to BLn * or B
They are commonly coupled to the non-inverted or inverted signal lines of R0 * to BRn *. Also, memory arrays ARYL and ARY
The gates of the address selection MOSFETs Qt and Qb of the n + 1 pairs of memory cells arranged in the same row of R are commonly coupled to the corresponding word lines WL0 to WLm or WR0 to WRm, respectively. Memory arrays ARYL and ARY
A predetermined plate voltage VP is commonly supplied to the other electrodes, that is, the plates of the ferroelectric capacitors Ct and Cb of all the memory cells forming R. The plate voltage VP is the internal voltage HVC, that is, the power supply voltage V when the power supply voltage is applied and the shadow RAM is in the volatile mode.
When the intermediate potential between CC and the ground potential VSS is set, the power supply voltage is cut off, and the shadow RAM is set to the non-volatile mode,
The ground potential VSS is set to 0V.

The ferroelectric memory cells constituting the memory arrays ARYL and ARYR are shown in FIG. 3 in relation to the electric field applied between the electrodes of the ferroelectric capacitors Ct and Cb and the polarization of the ferroelectric substance between the electrodes. It has information holding characteristics as shown in. That is, the initial ferroelectric substance at the point A shifts its state to the point B by applying the electric field + Ep in the positive direction between the electrodes, and the maximum polarization + Pp in the positive direction occurs. This polarization gradually decreases as the electric field becomes smaller, but the polarization + Pr remains at the point C where the electric field becomes zero. On the other hand, the polarization of the ferroelectric substance is reversed at the point D where the electric field -Ec in the opposite direction is applied between the electrodes, and the maximum polarization -Pp in the opposite direction occurs at the point E where the electric field -Ep is applied. This polarization gradually decreases as the electric field becomes smaller, but the polarization -Pr remains at the point F where the electric field becomes zero. The point G to which the positive electric field + Ec is applied
A normal rotation is made at the boundary, and the above point B is reached. When the polarization state of the ferroelectric substance of the ferroelectric capacitor is on the + side, the memory cell is supposed to hold the data of logic “1”, but the polarization state of the ferroelectric substance is not particularly limited. When it is on the negative side, the data of logical "0" is held.

In this embodiment, the shadow RAM is
As shown in FIG. 4, when the power supply voltage is applied, the power supply voltage is cut off by operating in a volatilization mode using the accumulated charge of the interelectrode capacitance of the ferroelectric capacitor, as in a normal dynamic RAM. When operated, it operates in a non-volatile mode utilizing the polarization of the ferroelectric substance between the electrodes. When the power supply voltage is applied, the shadow RAM access device first sets the recall mode control signal RECM to the high level to temporarily set the shadow RAM to the recall mode, and then returns the recall mode control signal RECM to the low level to perform normal volatilization. Set to mode. In the recall mode, the shadow RAM performs a read operation for shifting from the non-volatile mode to the volatile mode in units of word lines, as will be described later, but this read operation is treated as a substantially non-volatile mode.

In this embodiment, the plate of the ferroelectric capacitor constituting each ferroelectric memory cell is supplied with a plate voltage VP which is an intermediate potential between the internal voltage HVC, that is, the power supply voltage VCC and the ground potential VSS. The potential serves as a reference potential that determines the interelectrode voltage of the ferroelectric capacitor. When the shadow RAM is in the non-selected state, the complementary bit lines BL0 * to BLn * and BR0 * to BRn * of the memory arrays ARYL and ARYR are precharged to the internal voltage HVC. The state corresponds to the state of zero electric field in FIG.

On the other hand, when the shadow RAM is set to the normal non-volatile mode due to the disconnection of the power supply voltage, the polarization state of the ferroelectric capacitors forming each ferroelectric memory depends on the logical value of the held data. Selectively at point C or point F in FIG. 3, this state does not change semipermanently.
When the power supply voltage of the shadow RAM is turned on and the read operation is performed in the recall mode, the memory array ARY
The complementary bit lines BL0 * to BLn * and BR0 * to BRn * of L and ARYR are first precharged to their low levels such as the ground potential VSS with their non-inverted and inverted signal lines as described later. This low level corresponds to the corresponding n by selectively setting one of the designated word lines WL0 to WLm or WR0 to WRm to the high level.
It is transmitted to the information storage nodes of the +1 pair of ferroelectric memory cells, and the polarization states of the ferroelectric capacitors of these memory cells are forced to shift to point E in FIG.

At this time, in the memory cell which holds the data of logic "1", the polarization inversion from the point C to the point E is involved, so that the relatively large negative charge, that is, the movement of the electron is required, and thereby the corresponding complementary. The potential of the non-inversion or inversion signal line of the bit line rises relatively large. However, in the memory cell holding the data of logic “0”, since the transition from the point F to the point E is not accompanied by the polarization inversion, the negative charges do not move much and the non-inversion or inversion signal of the corresponding complementary bit line is generated. The potential rise of the line is also relatively small. These potential changes in each complementary bit line are caused by the sense amplifier SA described later.
Of the n + 1 pairs of memory cells coupled to the selected word line as a binary read signal of high level such as the power supply voltage VCC or low level such as the ground potential VSS. The capacitance between the electrodes of the dielectric capacitor is rewritten. As a result, the shadow RAM shifts to the volatile mode, and the reading or writing of data by the access device can be accepted.

When the shadow RAM is used in the volatile mode, the charges accumulated in the interelectrode capacitance of the ferroelectric capacitors of each memory cell are stored in the address selection MOSFET.
Gradually leaks through the PN junction of the source region of the.
Therefore, also in the case of the shadow RAM, as in the case of a normal dynamic RAM, a refresh operation for reading and rewriting the data held in the memory cell in word line units at a predetermined cycle tref according to the leak characteristic of the ferroelectric capacitor. Is required. In order to deal with this, in the shadow RAM of this embodiment, the so-called CBR (CAS) is used.
Before RAS) refresh mode is prepared, and a series of refresh operations relating to the word lines WL0 to WLm and WR0 to WRm can be autonomously performed under the control of the built-in refresh controller RFC.

Next, when the read operation in the volatile mode is performed in the shadow RAM, the potentials of the non-inverted and inverted signal lines of the complementary bit lines BL0 * to BLn * and BR0 * to BRn * precharged to the internal voltage HVC. Is
When the word lines WL0 to WLm or WR0 to WRm are alternatively set to the high level, the charge accumulated in the interelectrode capacitance of the ferroelectric capacitor of the corresponding memory cell is charge-shared with the parasitic capacitance. It slightly rises or falls. These complementary bit lines BL0 *
.. to BLn * or BR0 * to BRn * are amplified by the corresponding unit amplifier circuits of the sense amplifier SA to be binary read signals,
Output from the complementary common data line CD * to the external access device via the data input / output circuit IO and the data output terminal Dout.

In other words, when the read operation in the volatile mode is performed in the shadow RAM of this embodiment, the polarization states of the ferroelectric capacitors of the selected memory cell are complementary bit lines BL0 * to BLn * and BR0 *.
From point C or point F in FIG. 2 in which the non-inverted and inverted signal lines of BRn * are in the precharged state, point B corresponding to the high level after amplification or point E corresponding to the low level after amplification
However, the polarization inversion accompanying the read operation does not occur. Therefore, it is possible to reduce the number of times of rewriting of the ferroelectric memory cell per time, and thereby to prolong the service life of the ferroelectric memory cell.

On the other hand, when the same data is written in the volatile mode in the shadow RAM, that is, the non-inverted write operation is performed, the polarization state of the ferroelectric capacitor of the selected memory cell is similar to that in the read operation, and the complementary bit line BL is used.
0 * to BLn * and BR0 * to BRn * have non-inverted and inverted signal lines in a precharged state from point C or point F in FIG. 2 to point B corresponding to the high level after amplification or point E corresponding to the low level. However, no polarization reversal associated with the write operation occurs. However, when writing data of different logical values, that is, inversion writing operation, the polarization state of the ferroelectric capacitor of the selected memory cell shifts from point C to point E or from point F to point B, respectively, and the polarization inversion is performed. It will be accompanied.

In FIG. 2, the sense amplifier SA is provided with n + 1 unit circuits provided corresponding to the complementary bit lines of the memory arrays ARYL and ARYR, and each of these unit circuits has a P-channel MOSFET P1 and an N-channel. It includes a unit amplifier circuit in which a pair of CMOS (complementary MOS) inverters composed of MOSFET N1 and P-channel MOSFET P2 and N-channel MOSFET N2 are cross-coupled to each other. Of these, P-channel MOSFE that constitutes each unit amplifier circuit
The sources of TP1 and P2 are commonly coupled to the common source line CSP, and the sources of N-channel MOSFETs N1 and N2 are commonly coupled to the common source line CSN. The commonly connected drains of the MOSFETs P1 and N1 and the commonly connected gates of the MOSFETs P2 and N2 are respectively connected to the non-inverting input / output node B of each unit circuit.
S0T to BSnT, and the commonly coupled gates of MOSFETs P1 and N1 and MOSFETs P2 and N.
The two commonly coupled drains serve as inverting input / output nodes BS0B to BSnB, respectively.

Each unit circuit of the sense amplifier SA is further connected between its non-inverting input / output nodes BS0T-BSnT and inverting input / output nodes BS0B-BSnB and the non-inverting and inverting signal lines of the complementary common data line CD *, respectively. A pair of N-channel type switch MOSFETs provided
N3 and N4 and three N-channel MOSFET N5
To N7 are connected in series and parallel, respectively. Further, each unit circuit is arranged between its non-inverting input / output nodes BS0T to BSnT and its inverting input / output nodes BS0B to BSnB and the corresponding non-inverting and inverting signal lines of the corresponding complementary bit lines BL0 * to BLn * of the memory array ARYL. A pair of shared N-channel type MOSFETs N8 and N9 (first switch means) provided
Each of which includes a non-inverting input / output node BS0T-B
SnT and inverted input / output nodes BS0B to BSnB and corresponding complementary bit lines B of the other memory array ARYR
Another pair of shared MOSFETs NA and NB provided between the non-inverted and inverted signal lines of R0 * to BRn *
Each includes (first switch means).

The drains of the switch MOSFETs N3 and N4 constituting each unit circuit of the sense amplifier SA have non-inverting input / output nodes BS0T to BSnT of the corresponding unit circuit.
Alternatively, it is coupled to inverting input / output nodes BS0B to BSnB. The sources of these switch MOSFETs are the non-inverting common data line CDT or the inverting common data line C.
Each of them is commonly coupled to DB, and the corresponding commonly coupled gates are supplied with corresponding bit line selection signals YS0 to YSn from the Y address decoder YD. on the other hand,
The gates of MOSFETs N5 to N7 forming the bit line precharge circuit of each unit circuit of the sense amplifier SA are
An internal control signal PC from a timing generation circuit TG described later.
Are commonly supplied, and a predetermined precharge voltage VC is commonly supplied to the sources of the MOSFETs N6 and N7 that are commonly coupled. Further, a shared control signal SHL is commonly supplied from the timing generation circuit TG to the gates of the shared MOSFETs N8 and N9, and the shared MOSs are shared.
The shared control signal S is applied to the gates of the FETNA and NB.
HR is commonly supplied.

The internal control signal PC is set to a high level like the power supply voltage VCC when the shadow RAM is in the non-selected state of the volatile mode, and when the shadow RAM is in the selected state, the ground potential VSS is set at a predetermined timing. It will be a low level like. In addition, the precharge voltage VC
As will be described later, when the shadow RAM is in the normal operation state in the volatile mode, the intermediate potential, that is, the internal voltage HVC is set, and when the shadow RAM is set to the recall mode for making a transition from the nonvolatile mode to the volatile mode, The ground potential VSS, that is, the low level is temporarily set at a predetermined timing. Furthermore, the shared control signal SH
When the shadow RAM is in a non-selected state, L and SHR are both set to a high voltage VCH higher than the power supply voltage VCC by at least the threshold voltage of the address selection MOSFETs Qt and Qb of the ferroelectric memory cell.
When AM is selected, one of them is selectively set to the low level such as the ground potential VSS.

From these facts, the shared MOSFETs N8 and N9 and NA and NB of each unit circuit of the sense amplifier SA are selectively turned on in response to the high level of the corresponding shared control signal SHL or SHR,
Complementary bit line BL of memory array ARYL or ARYR
0 * -BLn * or BR0 * -BRn * non-inverting and inverting signal lines and corresponding non-inverting input / output nodes BS0T-BSnT and inverting input / output node BS0B of the unit circuit
To BSnB are selectively connected. In addition, the MOS that constitutes the bit line precharge circuit of each unit circuit
The FETs N5 to N7 are selectively turned on in response to the high level of the internal control signal PC, and the non-inverting input / output nodes BS0T to BSnT and the inverting input / output nodes BS0B to BSnB of the corresponding unit circuit, that is, the memory array AR.
The complementary bit lines BL0 * to BLn * of YL and ARYR and the non-inverted and inverted signal lines of BR0 * to BRn * are precharged to the internal voltage HVC or the ground potential VSS.

On the other hand, the unit amplifier circuits of each unit circuit of the sense amplifier SA are selectively and simultaneously operated by being supplied with the power supply voltage VCC or the ground potential VSS via the common source lines CSP and CSN. , Memory array A
The corresponding complementary bit line BL0 from the n + 1 pairs of memory cells coupled to the selected word line of RYL or ARYR
The minute read signals output via * to BLn * or BR0 * to BRn * are amplified and converted into high level or low level binary read signals. Further, the switch MOSFETs N3 and N4 of each unit circuit are selectively turned on in response to the high level of the corresponding bit line selection signals YS0 to YSn, and the non-inversion input / output nodes BS0T to BSnT and the inversion input / output nodes of the corresponding unit circuit. The output nodes BS0B to BSnB are selectively connected to the non-inverted and inverted signal lines of the complementary common data line CD *, that is, the data input / output circuit IO.

In this embodiment, the shared control signal S
When the read operation in the recall mode, that is, the non-volatile mode is performed, the timing at which one of the HL and the SHR is set to the low level is slightly delayed compared to the case of the normal read operation in the volatile mode. That is, for example, when the read operation in the recall mode is performed by activating the memory array ARYL, in other words, designating any one of the word lines WL0 to WLm of the memory array ARYL, the shared control signal S
In the normal read operation in the volatile mode, the HR is set to the low level before the selection operation of the word lines WL0 to WLm is performed, and the memory array ARYR is quickly deactivated. However, when the read operation in the recall mode is performed, the shared control signal SHR is the complementary signal corresponding to the minute read signals of the n + 1 pairs of memory cells coupled to the selected word line after the selection operation of the word lines WL0 to WLm is completed. It is set to the low level after being output to the bit lines BL0 * to BLn *, that is, immediately before the unit amplifier circuit of the sense amplifier SA is activated.

In other words, when the designated word line is selected, the shared M of the sense amplifier SA is initially set.
The OSFETs N8 and N9 and NA and NB are turned on all at once, and the complementary bits of the memory array ARYL that are activated are seen from the n + 1 pair of ferroelectric memory cells coupled to the selected word line. Line BL0 *
In addition to the parasitic capacitances coupled to the non-inverting and inverting signal lines of BLn * to BLn *, the parasitic capacitances coupled to the non-inverting input / output nodes BS0T to BSnT and the inverting input / output nodes BS0B to BSnB of each unit circuit of the sense amplifier SA. And the complementary bit line BR of the memory array ARYR which is inactivated.
The non-inversion of 0 * to BRn * and the parasitic capacitance coupled to the inversion signal line are simultaneously coupled. As a result, the ratio between the bit line capacitance Cd and the interelectrode capacitance Cs of the ferroelectric capacitor, that is, the capacitance coupling ratio Cd / Cs, becomes large, which results in an increase in the operation margin of the read operation in the recall mode. The specific contents and characteristics of the read operation in the recall mode will be described later in detail.

In FIG. 1, word lines WL0 to WLm and word lines W of the memory arrays ARYL and ARYR are shown.
Below, R0 to WRm are coupled to the corresponding X address decoder XDL or XDR, respectively, and are alternatively set to the selected state. X address decoders XDL and X
To the DR, i-bit internal address signals X0 to Xi-1 excluding the most significant bit are commonly supplied from the X address buffer XB, and corresponding internal control signals XGL and XGR are respectively supplied from the timing generation circuit TG. The X address buffer XB has an address input terminal A
X address signals AX0 to AXi are time-divisionally supplied via 0 to Ai, and refresh address signals RX0 to RXi are supplied from the refresh controller RFC. The X address buffer XB is further supplied with internal control signals RF and XL from the timing generation circuit TG,
The refresh controller RFC is supplied with an internal control signal RC (not shown) from the timing generation circuit TG.

When the shadow RAM is in the refresh mode, the refresh controller RFC performs a step operation according to the internal control signal RC supplied from the timing generation circuit TG, and the refresh address signal RX0.
~ RXi is formed and supplied to the X address buffer XB. The X address buffer XB internally receives the X address signals AX0 to AXi which are time-divisionally input via the address input terminals A0 to Ai when the shadow RAM is in the normal operation mode and the internal control signal RF is at the low level. It is fetched and held according to the control signal XL. In addition, the shadow RAM is set to the refresh mode and the internal control signal RF is set.
Is set to a high level, the refresh address signal R supplied from the refresh controller RFC
X0 to RXi are fetched and held according to the internal control signal XL. Then, these X address signals AX0 to AX
i or the refresh address signals RX0 to RXi, the internal address signals X0 to Xi are formed. Of these, the internal address signal Xi of the most significant bit is supplied to the timing generation circuit TG and the other internal address signals X0 to Xi-1.
Are supplied to the X address decoders XDL and XDR, respectively.

The X address decoders XDL and XDR are
The internal address signals X0 to Xi supplied from the X address buffer XB are selectively activated by receiving the high level of the corresponding internal control signal XGL or XGR.
-1 is decoded to obtain the memory array ARYL or ARY.
Word line WL0 to WLm or WR0 corresponding to R
WRm is alternatively set to a selection level such as high voltage VCH.

The Y address decoder YD outputs an i + 1 bit internal address signal Y0 from the Y address buffer YB.
To Yi, and an internal control signal YG from the timing generation circuit TG. Also, a Y address buffer Y
B is supplied with Y address signals AY0 to AYi in a time-sharing manner through the address input terminals A0 to Ai, and an internal control signal YL from the timing generation circuit TG.

The Y address buffer YB is a shadow RA.
Address input terminals A0-A when M is selected
Y address signal AY0 supplied in a time-division manner through i
To AYi in accordance with the internal control signal YL and hold the same, and form the internal address signals Y0 to Yi based on these Y address signals to generate a Y address decoder YD
To supply. At this time, the Y address decoder YD is selectively activated by receiving the high level of the internal control signal YG, decodes the internal address signals Y0 to Yi supplied from the Y address buffer YB, and outputs the sense amplifier S.
The bit line selection signals YS0 to YSn for A are alternatively set to the high level.

The complementary common data line CD * to which the complementary input / output nodes BS0 * to BSn * of the designated unit circuit of the sense amplifier SA are alternatively connected is coupled to the data input / output circuit IO in the other side. To be done. The data input / output circuit IO includes one data input buffer, one data output buffer, a write amplifier and a main amplifier, respectively. Of these, the input terminal of the data input buffer is coupled to the data input terminal Din, and the output terminal thereof is coupled to the input terminal of the write amplifier. The input terminal of the data output buffer is coupled to the output terminal of the main amplifier, and the output terminal thereof is coupled to the data output terminal Dout. The output terminal of the write amplifier and the input terminal of the main amplifier are commonly coupled to a complementary common data line CD *. The write amplifier is supplied with the internal control signal WC from the timing generation circuit TG, and the data output buffer is supplied with the internal control signal OC.

The data input buffer of the data input / output circuit IO takes in the write data input via the data input terminal Din and transmits it to the write amplifier when the shadow RAM is selected in the write mode. At this time, the write amplifier is selectively activated by receiving the high level of the internal control signal WC, converts the write data transmitted from the data input buffer into a predetermined complementary write signal, and then outputs the complementary common data line CD. * To the memory array ARYL or ARYR via the sense amplifier SA
Writing to one selected ferroelectric memory cell.

On the other hand, the main amplifier of the data input / output circuit IO is connected to the sense amplifier SA and the sense amplifier SA from one selected ferroelectric memory cell of the memory array ARYL or ARYR when the shadow RAM is selected in the read mode. The binary read signal output via the complementary common data line CD * is further amplified and transmitted to the data output buffer. At this time, the data output buffer is selectively activated in response to the high level of the internal control signal OC, and outputs a read signal transmitted from the main amplifier from the data output terminal Dout to an external access device.

The timing generation circuit TG is provided with a row address strobe signal RASB and a column address strobe signal CAS which are supplied as activation control signals from an external device.
B, the write enable signal WEB and the recall mode control signal RECM, and the internal address signal Xi of the most significant bit supplied from the X address buffer XB are used to determine the operation mode of the shadow RAM and the various internal control signals described above. Etc. are selectively formed and supplied to each part of the shadow RAM.

FIG. 5 shows a signal waveform diagram of one embodiment of the read operation in the nonvolatile mode, that is, the recall mode of the shadow RAM of FIG. 1, and FIG. 6 shows one embodiment of the read operation in the volatile mode. A signal waveform diagram is shown. Further, FIG. 7 shows an array connection diagram during a read operation in the recall mode of FIG. 5, and FIG.
An array connection diagram during a read operation in the volatile mode is shown. Based on these figures, the outline and characteristics of the read operation of the shadow RAM in the recall mode and the volatile mode will be described. As described above, the read operation in the recall mode is performed in word line units, that is, in units of n + 1 pairs of ferroelectric memory cells coupled to each word line, and the read operation in the volatile mode is performed in 1 unit address It is performed in units of a pair of ferroelectric memory cells. 5 and 7 exemplify a case where the read operation in the recall mode is performed by designating the word line WL0 of the memory array ARYL, and FIGS. 6 and 8 show the read operation in the volatile mode in the memory array ARYL. Word line WL0 and complementary bit line BL0
The case where a pair of ferroelectric memory cells arranged at the intersections of * are designated is shown. In each embodiment,
Memory array ARYL is activated and memory array ARYR is deactivated.

In FIG. 5, the row address strobe signal RASB and the column address strobe signal CASB are used.
Is set to a high level and the shadow RAM is in a non-selected state, in the sense amplifier SA, the precharge MOSFETs N5 to N7 forming each unit circuit are controlled by the internal control signal P.
Upon receiving the high level of C, it is turned on, and the complementary bit lines BL0 * to BLn of the memory arrays ARYL and ARYR.
The non-inversion and inversion signal lines of * and BR0 * to BRn * are both precharged to the intermediate potential of the precharge voltage VC, that is, the internal voltage HVC. At this time, the shared control signals SHL and SHR are both set to the high voltage VCH,
Complementary bit lines BL of the memory arrays ARYL and ARYR
0 * to BLn * and BR0 * to BRn * are both coupled to complementary input / output nodes BS0 * to BSn * of the corresponding unit circuit of sense amplifier SA. In addition, the ground potential V is applied to the common source line CSP and the common source line CSN.
The SS and the power supply voltage VCC are respectively supplied, and the n + 1 unit amplifying circuits of the sense amplifier SA are cut off from the supply path of the operating power supply.

As a result, the complementary input / output nodes BS0 * to BSn * of each unit circuit of the sense amplifier SA, that is, the unit amplifier circuits USA0 to USAn are complementary to the memory array ARYL as illustrated in FIG. 7A. Bit line BL0
The parasitic capacitances Cdtl and Cdbl of * to BLn * and the parasitic capacitances Cdtr and Cdbr of the complementary bit lines BS0 * to BSn * of the memory array ARYR are simultaneously connected, and each parasitic capacitance corresponds to the corresponding bit of the sense amplifier SA. It is precharged to an intermediate potential, that is, the internal voltage HVC via the line precharge circuit.

When the shadow RAM is in the non-selected state immediately after the power is turned on, the memory arrays ARYL and ARY are
In each of the ferroelectric memory cells forming R, the polarization state of the ferroelectric substance provided between the electrodes of the ferroelectric capacitor is selectively changed according to the logical value of the held data to the point C or the point F in FIG. However, in the inter-electrode capacitance of the ferroelectric capacitor, charges corresponding to the logical value of the held data are hardly accumulated.

The shadow RAM executes a so-called CBR (CAS Before RAS) cycle in which the column address strobe signal CASB is changed to the low level prior to the row address strobe signal RASB while the recall mode control signal RECM is at the high level. Then, the read operation in the recall mode is started. At this time, the write enable signal WEB remains at the high level, and the word line targeted for the read operation is the refresh controller RFC of the shadow RAM.
Refresh address signals RX0 to RX output from
It is alternatively designated according to i. In shadow RAM,
In response to the fall of the row address strobe signal RASB, first, the precharge voltage VC is temporarily changed from the internal voltage HVC to the ground potential VSS for a predetermined period, and the internal control signal PC is set to the low level after a predetermined time. . Also, with a slight delay, the designated word line WL0 of the memory array ARYL is set to the selection level of the high voltage VCH,
After a predetermined time Td, the shared control signal SHL is kept at the high level and the shared control signal SHR is kept at the low level. Then, after a predetermined time, the common source line CSP
To the common source line CSN, and the ground potential VSS is supplied to the common source line CSN.

In the memory array ARYL, both the non-inverted and inverted signal lines of the complementary bit lines BL0 * to BLn * are precharged to the ground potential VSS, that is, 0V in response to the change of the precharge voltage VC to the ground potential VSS. To be done. In addition, as shown in FIG. 7B, the word line WL
In response to the selection level of 0, the address selection MOSFETs Qt and Qb of the corresponding n + 1 pairs of ferroelectric memory cells are turned on, and the reverse between the electrodes of the ferroelectric capacitors of each memory cell with HVC as an absolute value. Directional electric fields are applied all at once. In each ferroelectric memory cell, when it holds data of logic "1", for example, the polarization state shifts from point C to point E in FIG. 3, and when it holds data of logic "0", for example. Shifts from point F to point E.

As a result, in the memory cell pair of the memory array ARYL which holds data of logic "1", for example, from the point C to the point E in the memory cells coupled to the non-inverted signal lines of the complementary bit lines BL0 * to BLn *. Since the polarization inversion to the electric field is performed, a relatively large negative charge, that is, the movement of electrons is required, and the potential of the corresponding non-inversion signal line rises relatively large. However, in the memory cells coupled to the inversion signal lines of the complementary bit lines BL0 * to BLn *, since the transition from the point F to the point E without polarization inversion occurs, the movement of the negative charge is small, and the corresponding inversion signal. The potential rise of the line is also relatively small. On the other hand, for example, a logical "0" of the memory array ARYL
Of the complementary bit line B in the memory cell pair which holds the data of
Since the polarization inversion from the point C to the point E is performed in the memory cells coupled to the inversion signal lines L0 * to BLn *, the potential of the corresponding inversion signal line rises relatively large. However, in the memory cells connected to the non-inverted signal lines of the complementary bit lines BL0 * to BLn *, since the transition from the point F to the point E without polarization inversion occurs, the potential rise of the corresponding inversion signal line is also compared. Small

The above-mentioned potential difference in the non-inverted and inverted signal lines of the complementary bit lines BL0 * to BLn * is due to the common source line CSP being supplied with the power supply voltage VCC.
When the ground potential VSS is supplied to N, it is amplified by the corresponding unit amplifier circuit of the sense amplifier SA, and is at a high level such as the power supply voltage VCC or the ground potential V.
After a low level binary read signal such as SS, it is also written in the interelectrode capacitance of the ferroelectric capacitors of the n + 1 pairs of memory cells coupled to the selected word line WL0. As a result, the shadow RAM shifts to the volatile mode, and the reading or writing of data by the access device can be accepted.

As described above, the shadow RA of this embodiment is
The read operation of the M in the recall mode is performed at the ground potential V
Complementary bit lines BL0 * to BL precharged to SS
This is performed by utilizing the fact that the potential of n * selectively rises according to the polarization state of the ferroelectric capacitor of the selected memory cell. At this time, the plate voltage VP such as the internal voltage HVC is supplied to the plate of each ferroelectric capacitor. Further, in a normal operation region, between the electrodes of the ferroelectric capacitor, the parasitic capacitance coupled to the non-inversion or inversion signal line of the complementary bit lines BL0 * to BLn * is defined as Cs, which is the capacitance between the electrodes. When the electrostatic capacitance of Cd is Cd, an inter-electrode voltage Ve of Ve = HVC / (1 + Cs / Cd) is applied by charge sharing,
The amount of charge transfer due to the change of the polarization state of the ferroelectric substance is
Electrode voltage Ve, that is, complementary bit lines BL0 * to BLn
* Parasitic capacitance Cd and inter-electrode capacitance C of ferroelectric capacitor
It becomes maximum when the capacitive coupling ratio Cd / Cs with s is set to, for example, about "2".

Therefore, in this embodiment, as described above, the shared control signal SHR is set to the high level together with the shared control signal SHL for a predetermined period Td after the designated word line WL0 is set to the selection level, Complementary input / output nodes BS0 * to B of each unit circuit of the sense amplifier SA
Sn * includes, in addition to the parasitic capacitances Cdtl and Cdbl of the complementary bit lines BL0 * to BLn * of the memory array ARYL in the active state, the memory array AR in the inactive state.
Parasitic capacitance Cd of YR complementary bit lines BS0 * to BSn *
tr and Cdbr are connected at the same time. As a result, the capacitance coupling ratio Cd / Cs is optimized to, for example, about "2", and the maximum amount of potential change is obtained in the non-inverted and inverted signal lines of the complementary bit lines BL0 * to BLn *.

The memory array AR in the inactive state
The shared control signal SHR corresponding to YR is supplied to the common source lines CSP and CSN as the power supply voltage VCC or the ground potential V.
It is set to the low level immediately before SS is supplied, that is, immediately before the unit amplifier circuit of the sense amplifier SA is activated. Therefore, when the amplification operation by the unit amplifier circuit of the sense amplifier SA is performed, as shown in FIG. 7C, the complementary input / output nodes BS0 * to BS of each unit circuit are provided.
n *, that is, the complementary bit lines BL0 * to BLn * of the memory array ARYL that are activated, to the complementary bit lines BS0 * to BS of the memory array ARYR that are inactivated.
The n * parasitic capacitances Cdtr and Cdbr are disconnected.
As a result, the load on the unit amplifier circuits USA0 and the like of the sense amplifier SA is reduced, and the shadow RA accompanying the simultaneous operation of n + 1 unit amplifier circuits is performed.
The change in the operating current of M is suppressed, and thereby the power supply noise of the shadow RAM due to the operation of the sense amplifier SA is suppressed.

Next, the shadow RAM in the volatile mode
As shown in FIG. 6, the row address strobe signal RASB is brought to a low level to be selectively brought into a selected state, and the read operation is started in response to a high level of a write enable signal WEB (not shown). At this time, the recall mode control signal RECM remains low level. The address input terminals A0 to Ai are synchronized with the fall of the row address strobe signal RASB, for example, the word line W of the memory array ARYL.
The X address signals AX0 to AXi are supplied in a combination designating L0, that is, the row address ra0, and in synchronization with the fall of the column address strobe signal CASB,
For example, the bit line selection signal YS0, that is, the column address c
Y address signals AY0-A in combination that specifies a0
Yi is supplied.

In the shadow RAM, first, the internal control signal PC is set to the low level in response to the fall of the row address strobe signal RASB, and the precharge operation by the bit line precharge circuit of the sense amplifier SA is stopped. Further, the shared control signal SHL is kept at the high level, the shared control signal SHR is kept at the low level, and the complementary bit lines BR0 * to BRn forming the memory array ARYR are formed.
* Indicates a sense amplifier SA as shown in FIG.
The connection with the corresponding unit amplifier circuit USA0 is cut off. In the shadow RAM, the word line WL0 of the memory array ARYL designated at a predetermined timing is alternatively set to a selection level such as the high voltage VCH, and the complementary bit lines BL0 * to B precharged to the internal voltage HVC.
The potential of the non-inverted and inverted signal lines of Ln * is the same as the word line WL.
The accumulated charge of the inter-electrode capacitance of the n + 1 pairs of ferroelectric memory cells coupled to 0, that is, a minute read signal according to the logical value of the data held in each memory cell is output to be complementarily changed. The potential difference between the non-inverted and inverted signal lines of the complementary bit lines BL0 * to BLn * is the common source line CSP.
When the power supply voltage VCC is supplied to the common source line CSN and the ground potential VSS is supplied to the common source line CSN, the unit amplifier circuits corresponding to the sense amplifier SA respectively amplify the binary read signals of high level or low level.

When the column address strobe signal CASB is set to the low level, in the shadow RAM, the bit line selection signal YS0 corresponding to the column address ca0 is alternatively set to the high level, and the data input / output circuit I is slightly delayed.
The internal control signal OC for the O data output buffer is set to the high level. In the sense amplifier SA, the memory array AR receives the high level of the bit line selection signal YS0.
The complementary bit line BL0 * of YL is the complementary common data line CD *
2 connected to the non-inverted and inverted signal lines
The value read signal is output to the main amplifier of the data input / output circuit IO via the complementary common data line CD *. The binary read signal is amplified by the main amplifier, then receives the high level of the internal control signal OC, and is output from the data output buffer to the external access device via the data output terminal Dout. Complementary bit lines BL0 * to B
The binary read signal established on the non-inverted and inverted signal lines of Ln * is n + 1 directly connected to the word line WL0.
The capacitance between the electrodes of the ferroelectric capacitors of the paired ferroelectric memory cells is rewritten.

As described above, the shadow RA of this embodiment is
The read operation of M in the volatile mode is performed by precharging the potentials of the non-inverted and inverted signal lines of the complementary bit lines BL0 * to BLn * of the specified memory array ARYL to the internal voltage HVC in advance and then selecting the selected memory cell. It is carried out by selectively increasing or decreasing the interelectrode capacitance of the ferroelectric capacitor in accordance with 1. At this time, charges corresponding to the held data are accumulated in the inter-electrode capacitance of the ferroelectric capacitors of the n + 1 pairs of memory cells coupled to the selected word line WL0, and HVC is set to an absolute value between both electrodes. There is a positive or negative signal voltage that These accumulated charges, that is, signal voltages are charge-shared between the inter-electrode capacitance of the selected ferroelectric memory cell and the non-inversion of the complementary bit lines BL0 * to BLn * and the parasitic capacitance of the inversion signal line,
Usually, for the non-inverted and inverted signal lines of the complementary bit lines BL0 * to BLn *, the parasitic capacitance is Cd, and the interelectrode capacitance of the ferroelectric capacitor of the selected memory cell is Cs. At this time, a minute read voltage Vs of Vs = HVC / (1 + Cd / Cs) is obtained, and its signal amount is the capacitance between the parasitic capacitance Cd of the complementary bit lines BL0 * to BLn * and the interelectrode capacitance Cs of the ferroelectric capacitor. It becomes maximum when the coupling ratio Cd / Cs is set to, for example, about "1".

Therefore, in this embodiment, as shown in FIG. 7B, the memory array ARYR in the inactive state is set immediately before the designated word line WL0 is set to the selection level.
Of the shared control signal SHR corresponding to the low level and the complementary bit line BR0 * of the memory array ARYR.
The parasitic capacitances Cdtr and Cdbr coupled to the non-inverted and inverted signal lines of ~ BRn * are complementary input / output nodes BS0 * to BSn * of the corresponding unit circuit of the sense amplifier SA, that is, complementary bits of the active memory array ARYL. It is separated from the lines BL0 * to BLn *. As a result, the capacitance coupling ratio Cd / Cs is optimized to, for example, "1", and the maximum amount of minute read signal is obtained on the non-inverted and inverted signal lines of the complementary bit lines BL0 * to BLn *.

As described above, in the recall operation of the shadow RAM, that is, the read operation in the nonvolatile mode and the read operation in the volatile mode, the capacitive coupling ratio C
Although the optimum values of d / Cs are different from each other, in this embodiment, as described above, for example, the parasitic capacitance of the complementary bit lines BR0 * to BRn * of the memory array ARYR in the inactive state is the read operation in the recall mode. At times, the complementary bit lines BL0 * to B of the memory array ARYL in the active state to increase the capacitance coupling ratio Cd / Cs.
It is connected to Ln * as a dummy capacitor, and is disconnected from the complementary bit lines BL0 * to BLn * of the memory array ARYL in the read mode by the volatile mode, as in a normal dynamic RAM adopting the shared sense method. In addition, the capacitance coupling ratio Cd / Cs of these
Of the memory array ARYR in the inactive state.
This is realized by utilizing the parasitic capacitance of the complementary bit lines BR0 * to BRn *, that is, without adding a special dummy capacitance. As a result, it is possible to increase the operation margin as the shadow RAM while suppressing the increase in the chip size of the shadow RAM and suppressing the cost increase.

FIG. 9 shows an array configuration diagram of an embodiment of a second shadow RAM to which the present invention is applied.
0 shows an array configuration diagram of an embodiment of a third shadow RAM to which the present invention is applied. In addition, FIG.
4 shows a partial circuit diagram of an embodiment of a memory array of a fourth shadow RAM and its peripheral part to which the present invention is applied. Based on these drawings, an outline of the configuration and operation of the second to fourth shadow RAMs to which the present invention is applied and the features thereof will be described. Since these embodiments basically follow the shadow RAM shown in FIGS. 1 to 8, only the parts different from this will be described.

First, referring to FIG. 9, the shadow RAM of this embodiment has two pairs of memory arrays ARY which are in a shared sense form and are activated alternatively.
0 and ARY1 and ARY2 and ARY3. Of these, complementary bit lines B00 * to B0n * and B10 * to B1 of the memory arrays ARY0 and ARY1.
n * is a shared MOSFET NF and NG or N
Complementary input / output nodes BS00 * to BS0n of the corresponding unit circuit of the sense amplifier SA0 selectively via H and NI
Connected to * and complementary bit lines B20 * to B2n * and B30 * to B3 of the memory arrays ARY2 and ARY3.
n * is a shared MOSFET NJ and NK or N
Complementary input / output nodes BS10 * to BS1n of the unit circuit corresponding to the sense amplifier SA1 selectively via L and NM
Connected to *.

In this embodiment, the memory array ARY
1 and the complementary bit lines B10 * to B1n * corresponding to 1 and the corresponding complementary bit lines B20 * to B2 of the memory array ARY2.
Although it does not actually share a sense amplifier with n *, it is an N-channel switch MOSFET.
TND and NE (second switch means) are provided respectively, and the gates of these switch MOSFETs ND and NE are provided with the internal control signal N from the timing generation circuit TG.
VC1 is commonly supplied.

In the switch MOSFETs ND and NE, for example, when the memory array ARY0 is activated and the shared MOSFETs NF and NG of the sense amplifier SA0 are turned on, that is, the word line selection operation is initially performed in the read operation in the recall mode. , Shared MOSFETs NH and NI on the opposite side of the sense amplifier SA0
And the shared MOSFET N of the sense amplifier SA1
The memory arrays ARY1 and ARY2 which are in the inactive state and are turned on all together with J and NK, NL and NM.
And complementary bit lines B10 * to B1n * of ARY3,
The parasitic capacitances of B20 * to B2n * and B30 * to B3n * are connected as dummy capacitors to the complementary bit lines B00 * to B0n * of the memory array ARY0 in the active state. As a result, the capacitive coupling ratio Cd / C at the initial stage of word line selection during the read operation in the recall mode
s is set to, for example, about “4”, whereby the read signal amount of the non-inversion and inversion signal lines of the complementary bit lines BL0 * to BLn * can be increased, and the operation margin of the shadow RAM can be increased. .

Next, in the shadow RAM of the embodiment of FIG. 10, in order to prevent the layout pitch of the complementary bit lines such as the memory arrays ARY0 to ARY2 from being restricted by the layout pitch of the unit circuits such as the sense amplifiers SA0 to SA3. , The so-called staggered arrangement method is adopted. Therefore,
In particular, for example, only the complementary bit lines of the memory array ARY0 on the right side are connected to the unit circuit US of the sense amplifier SA0 arranged at the left end, and the complementary memory lines of the memory array inactivated as shown in FIGS. The bit line cannot be used as a dummy capacitor. To deal with this, in this embodiment, for example, even-numbered complementary bit lines B00 * .B02 * to B0n-1 of the memory array ARY0 are used.
* And even-numbered complementary bit lines B10 * / B of the memory array ARY1 that are not in a relationship of actually sharing a sense amplifier.
12 * to B1n-1 *, N-channel type switch MOSFETs NN and NO (second switch means) whose gates commonly receive the internal control signal NVC2.
Is provided.

The switch MOSFETs NN and NO are selectively turned on under the same conditions as the switch MOSFETs ND and NE of FIG. 9, and for example, the even-numbered complementary bit lines B10 * of the inactive memory array ARY1.
The parasitic capacitances of B12 * to B1n-1 * are connected as dummy capacitors to the even-numbered complementary bit lines B00 * / B02 * to B0n-1 * of the active memory array ARY0. As a result, even when the shadow RAM adopts the staggered arrangement method and the memory arrays arranged at both ends are activated, the capacitance coupling ratio Cd / Cs during the read operation in the recall mode is set to, for example, “2”. The operating margin of the shadow RAM can be increased by optimizing the degree.

On the other hand, the shadow RAM of the embodiment of FIG.
Is provided with two pairs of dummy capacitors Cy and Cz separately provided in each unit circuit of the sense amplifier SA. Of these, one electrode of the dummy capacitor Cy is coupled to the non-inverting input / output nodes BS0T to BSnT of the corresponding unit circuit of the sense amplifier SA via the N-channel type switch MOSFET NP (third switch means). The plate voltage VP is commonly supplied to the other electrode.
Similarly, one electrode of the dummy capacitor Cz has an N-channel type switch MOSFET NQ (third switch means).
Through the input / output nodes BS0B to BSnB of the corresponding unit circuit of the sense amplifier SA, and the plate voltage VP is commonly supplied to the other electrodes.

In this embodiment, the dummy capacitors Cy and Cz have the same structure as the ferroelectric capacitors Ct and Cb of the memory cells forming the memory arrays ARYL and ARYR, and the switch MOSFETs NP and NQ are the address selection MOSFETs Qt and Qb. It has the same structure as. Further, the gates of the switch MOSFETs NP and NQ have internal control signals NVC from the timing generation circuit TG.
3 are commonly supplied, and memory arrays ARYL and ARY
Shared control signals SHL and SH for connecting between each complementary bit line of R and the corresponding unit circuit of the sense amplifier SA.
R is selectively set to a high level or a low level under the same conditions as those in the embodiments of FIGS. The internal control signal NVC3 is set to a high level like the high voltage VCH when the shadow RAM is in the non-selected state, and during the read operation in the recall mode, that is, the nonvolatile mode,
For example, after the designated word line WL0 is set to the selection level, it is set to the low level after a predetermined period Td in FIG.

From these facts, in the shadow RAM of this embodiment, the complementary bit line B of the memory array ARYR which is in the inactive state at the beginning of the read operation in the recall mode and the selection operation of the word line WL0 is performed.
The parasitic capacitances of R0 * to BRn * and the dummy capacitances Cy and Cz of the sense amplifier SA are connected to the corresponding complementary bit lines BL0 * to BLn * of the active memory array ARYL, respectively. As a result, the capacitive coupling ratio Cd / Cs during the read operation in the recall mode is set to, for example, about "4", and the complementary bit line B
The operation amount of the shadow RAM can be increased by increasing the signal amount of the read signal on the non-inverted and inverted signal lines of L0 * to BLn *.

The operational effects obtained from the above embodiments are as follows. That is, (1) a shadow RAM or the like, which has a plurality of memory arrays in which ferroelectric memory cells are arranged in a grid and is selectively activated, and which can be selectively used in a volatile mode and a non-volatile mode. In the ferroelectric memory of, for example, each bit line of the memory array that is selectively turned on and activated during a read operation in the recall mode of the non-volatile mode and the corresponding bit line of another memory array that is not activated. By providing the first switch means for selectively connecting between the two, the parasitic capacitance of the memory array which is not activated is selectively used as the dummy capacitance, and the capacitance coupling in the nonvolatile mode and the volatile mode of the shadow RAM or the like is performed. The effect that each ratio can be optimized is obtained.

(2) According to the above item (1), a sufficient amount of read signal is output from the selected ferroelectric memory cell to the corresponding complementary bit line during the read operation in the nonvolatile mode and the volatile mode. The effect of being able to be obtained is obtained. (3) In the above items (1) and (2), the first switch means is turned off immediately before the unit amplifier circuit of the sense amplifier is brought into the operating state, so that the unit amplifier circuit of the sense amplifier is loaded. It is possible to obtain the effect of reducing the power supply noise and suppressing the power supply noise accompanying the operation of the unit amplifier circuit. (4) In the above (1) and (2), the shadow RA
If M adopts the shared sense method, shared MO
By also using the SFET as the first switch means,
The effect that the number of circuit elements required for switching, that is, optimization of the capacitive coupling ratio can be reduced can be obtained.

(5) In the above items (1) to (4), when the shadow RAM is provided with a plurality of pairs of shared sense type memory arrays, the same means as the first switch means is provided between the pairs of memory arrays. By providing the second switch means that is selectively turned on under the conditions, the required number of parasitic capacitances of the bit lines forming the plurality of pairs of memory arrays are selectively connected as dummy capacitances, and the non-volatile mode and the volatilization are performed. The effect that the capacitive coupling ratio in the mode can be further optimized is obtained. (6) In the above items (1) to (5), when the parasitic capacitance of the memory array in the inactive state is insufficient, for example, in the sense amplifier, a third line is provided for each bit line of the memory array to be activated. By providing a predetermined number of dummy capacitors that are selectively connected through the switch means, it is possible to more effectively switch the capacitance coupling ratio of the shadow RAM or the like. (7) According to the above items (1) to (6), it is possible to realize a ferroelectric memory such as a shadow RAM having an improved operation margin while suppressing an increase in the chip size and an increase in cost. Is obtained.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in FIG. 1, the shadow RAM does not require the shared sense method as an essential condition. Further, the memory arrays ARYL and ARYR can be divided into a plurality of memory mats including their direct peripheral circuits. Furthermore, the shadow RAM may have any bit configuration such as x4 bits, x8 bits or x16 bits, and its block configuration, names of start control signals and internal control signals, combinations and effective levels, and power supply voltage. For the polarity and the like, various embodiments can be adopted.

In FIG. 2, shared MOSFET N8
~ NB can be replaced with P-channel MOSFET, N-channel and P-channel MOSFE
It may be a complementary switch combining T. Also, the shadow RAM can take various array configurations such as a so-called 1 cell / 1 transistor type, and the memory array ARY.
The specific configurations of L and ARYR, the sense amplifier SA, and the conductivity type of MOSFET are also arbitrary. In FIG. 3, the information retention characteristic of the ferroelectric memory cell is a standard example and does not limit the present invention. FIG.
In the above, various embodiments can be adopted as the starting conditions for setting the shadow RAM to the recall mode. 5 and 6, the starting control signal, the internal control signal, and the absolute time relationship and effective level of the internal signal are not limited to those in this embodiment.

In FIGS. 9 and 10, the N-channel MOSFETs ND and NE which are the second switch means are
It can be replaced with a P-channel MOSFET or a complementary switch. Also, the shadow RAM can be provided with any number of memory arrays and memory array pairs. In FIG. 11, the number of dummy capacitors Cy and Cz provided in the sense amplifier SA can be set arbitrarily. Also, these dummy capacitors do not necessarily have the same structure as the ferroelectric capacitor of the ferroelectric memory cell,
It may be provided separately from the sense amplifier SA and independently.

In the above description, the case where the invention made by the present inventor is mainly applied to a shadow RAM which is a field of application which is the background of the invention has been described, but the invention is not limited thereto and, for example, a similar shadow. RA
It can also be applied to a digital integrated circuit device such as a single-chip microcomputer incorporating M. INDUSTRIAL APPLICABILITY The present invention can be widely applied to a ferroelectric memory selectively used in at least a non-volatile mode and a volatile mode, and a device or system including the same.

[0073]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, a ferroelectric RAM such as a shadow RAM, which has a plurality of memory arrays in which ferroelectric memory cells are arranged in a lattice and is selectively activated, can be selectively used in a volatile mode and a nonvolatile mode. In the body memory, for example, between each bit line of the memory array that is selectively turned on and activated during a read operation in the recall mode of the non-volatile mode and the corresponding bit line of another memory array that is not activated. First switch means for selectively connecting is provided. In addition, this first
The switch means is turned off immediately before the operation of the sense amplifier, and when the shadow RAM adopts the shared sense system, the shared MOSFET is also used as the first switch means. Further, when a plurality of pairs of shared memory arrays are provided, a second switch means that is selectively turned on under the same condition as the first switch means is provided between the memory array pairs, and If the line capacity is insufficient, for example, a dummy capacitor that is selectively connected to each bit line of the activated memory array via the third switch means is provided in the sense amplifier. This reduces the load on the sense amplifier,
While suppressing power supply noise that accompanies the operation of the unit amplifier circuit, the parasitic capacitance of the memory array that is not activated is used as a dummy capacitance to determine the capacitance coupling ratio in the nonvolatile mode and the volatile mode of shadow RAM and the like. It is possible to optimize, and thereby a sufficient read signal amount can be secured. As a result, it is possible to realize a ferroelectric memory such as a shadow RAM which has an improved operation margin while suppressing an increase in the chip size and an increase in cost.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a first shadow RAM to which the present invention is applied.

FIG. 2 is a partial circuit diagram showing one embodiment of a memory array included in the shadow RAM of FIG. 1 and a peripheral portion thereof;

FIG. 3 is an information holding characteristic diagram showing one embodiment of a ferroelectric memory cell constituting the memory array of FIG. 2;

FIG. 4 is a conceptual diagram showing an embodiment for explaining a transition of operation modes of the shadow RAM shown in FIG.

5 is a signal waveform diagram showing an embodiment of a read operation in the recall mode (nonvolatile mode) of the shadow RAM of FIG.

6 is a signal waveform diagram showing an example of a normal read operation in a volatile mode of the shadow RAM of FIG.

7 is an array connection diagram during a read operation of the shadow RAM of FIG. 1 in a recall mode (nonvolatile mode).

8 is an array connection diagram during a normal read operation in a volatile mode of the shadow RAM of FIG.

FIG. 9 is an array configuration diagram showing an embodiment of a second shadow RAM to which the present invention is applied.

FIG. 10 is a third shadow RAM to which the present invention is applied.
It is an array block diagram which shows one Example.

FIG. 11 is a fourth shadow RAM to which the present invention is applied.
3 is a partial circuit diagram showing an embodiment of a memory array included in FIG.

[Explanation of symbols]

ARYL, ARYR ... Memory array, XDL, XDR
... X address decoder, X0 to Xi ... X internal address signal, XB ... X address buffer, RFC ... refresh controller, SA ... sense amplifier, YD ...
... Y address decoder, Y0 to Yi ... Y internal address signal, YB ... Y address buffer, IO ... Data input / output circuit, TG ... timing generation circuit. Din ... Data input terminal, Dout ... Data output terminal, RASB
...... Row address strobe signal input terminal, CASB ...
… Column address strobe signal input terminal, WEB ……
Write enable signal input terminal, RECM ... Recall mode control signal, A0-Ai ... Address input terminal. W
L0 to WLm, WR0 to WRm ... Word line, BL0 *
To BLn *, BR0 * to BRn * ... Complementary bit lines, Q
t, Qb ... Address selection MOSFET, Ct, Cb ...
… Ferroelectric capacitor, VP… Plate voltage, VC…
... Precharge voltage, BS0 * to BSn * ... Complementary input / output nodes, SHL, SHR ... Shared control signal, PC
...... Precharge control signal, CSP, CSN ...... Common source line, YS0 to YSn ...... Bit line selection signal, CD
* …… Complementary common data line. tref ... Refresh cycle. VCC: power supply voltage, VSS: ground potential, HVC
...... Internal voltage (intermediate potential between power supply voltage and ground potential),
VCH ... High voltage. USA0: Sense amplifier unit amplifier circuit. Cy, Cz ... Dummy capacitance. ARY0 to ARY3
...... Memory array, W00 to W20 ...... Word line, B0
0 * to B0n * to B30 * to B3n * ... Complementary bit lines, SA0 to SA3 ... Sense amplifier, US ... Sense amplifier unit circuit, BS00 * to BS0n * to BS
30 * to BS3n * ... Complementary input / output node for sense amplifier. N1 to NQ ... N-channel MOSFETs, P1 to
P2, PC ... P-channel MOSFET.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kazuhiko Kajiya 2326 Imai, Ome City, Tokyo, Hitachi, Ltd. Device Development Center (72) Seiji Narii 2326 Imai, Ome City, Tokyo Hitachi, Ltd. Device Development Center (72) Inventor Tsuyuki Suzuki 5-20-1, Josuihoncho, Kodaira-shi, Tokyo Hitsuritsu Cho-LS Engineering Co., Ltd. (72) Innovator Yasunobu Aoki 5 Sanmizuhoncho, Kodaira-shi, Tokyo Chome No. 20-1 Hitate Super LSI Engineering Co., Ltd.

Claims (7)

[Claims] 1. A word line and a bit line arranged orthogonal to each other, and ferroelectric memory cells arranged in a lattice at intersections of these word lines and bit lines, respectively, and are selectively activated. A first connection for selectively connecting between a plurality of memory arrays and a bit line of each of the memory arrays that are activated among the plurality of memory arrays and a corresponding bit line of another memory array that is not activated. 2. A ferroelectric memory, comprising: 2. The ferroelectric memory is a shadow RAM that can be selectively used in a nonvolatile mode and a volatile mode, and the first switch means has a predetermined timing during a read operation in a recall mode of the nonvolatile mode. 2. The ferroelectric memory according to claim 1, wherein the ferroelectric memory is selectively turned on. 3. The ferroelectric memory comprises a sense amplifier including a unit amplifier circuit provided corresponding to each bit line of the memory array and selectively activated. 3. The ferroelectric memory according to claim 2, wherein the first switch means that is turned on during a read operation in the mode is turned off immediately before the unit amplifier circuit is turned on. . 4. The ferroelectric memory adopts a shared sense system, and a unit amplifier circuit provided corresponding to each bit line of the pair of memory arrays and selectively activated, and Of the unit amplifier circuit, and a sense amplifier including a shared MOSFET that selectively connects between the corresponding bit line of the pair of memory arrays, the first switch means comprising: 3. The shared MOSFET of the sense amplifier is also used as a shared MOSFET.
Alternatively, the ferroelectric memory according to claim 3. 5. The ferroelectric memory is provided between the pair of memory arrays and another pair of adjacent memory arrays and is selectively turned on at a predetermined timing during a read operation in the recall mode. 5. A second switch means comprising:
Ferroelectric memory. 6. The ferroelectric memory comprises a dummy capacitor connected to a corresponding bit line of the memory array selectively activated by a third switch means. The ferroelectric memory according to claim 1, claim 2, claim 3, claim 4, or claim 5. 7. The ferroelectric memory according to claim 6, wherein the third switch means and the dummy capacitor are provided in a sense amplifier.