JPH09244587A - Liquid crystal display control device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a display control device optimized to a system by changing loading amount of display control LSI and frame/line memories corresponding to them in accordance with a display specification of a system. SOLUTION: In a liquid crystal display control circuit performing control adjusting RGB analog video signals 102-104 from a personal computer 101 and a display size specification of a liquid crystal display panel 136, the number of loading of display control LSI 115-117, frame memories 118-120 corresponding to them, and line memories 121-123 are set adjusting to display specification of resolution and the number of simultaneous display colors.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display control device.

[0002]

2. Description of the Related Art Conventionally, as a liquid crystal display control device integrated into an LSI, for example, as disclosed in Japanese Patent Laid-Open No. 7-5856, a display resolution setting section, a liquid crystal panel resolution setting section, a scaling calculation section, a scaling The function of the data conversion part etc. which converts the input video data according to the result 1
A liquid crystal display control technology in which a chip LSI is used is known.
FIG. 13 is a block diagram showing a first embodiment of a liquid crystal display control LSI disclosed in Japanese Patent Laid-Open No. 7-5856.

In FIG. 13, reference numeral 1301 denotes a liquid crystal display LSI, 1302.
Is a display resolution setting unit, 1303 is a liquid crystal panel resolution setting unit,
1304 is a calculation unit, 1305 is a video data input unit, 1306 is a video timing input unit, 1307 is a data conversion unit, 1308 is a memory controller unit, 1309 is a memory interface unit,
1310 is a liquid crystal display timing generation unit, 1311 is a liquid crystal display data output unit, 1312 is a magnification adjustment signal input terminal, 1313 is a memory, and 1314 is a liquid crystal panel.

FIG. 14 is a block diagram of a liquid crystal display control LSI for the second conventional technique.

In FIG. 14, reference numeral 1401 denotes a display resolution identifying unit, 1402.
Is a horizontal or vertical sync signal.

Further, FIG. 15 is a block diagram of a liquid crystal display control LSI for the third prior art.

In FIG. 15, reference numeral 1501 denotes a liquid crystal module resolution register.

In FIG. 13, the number of vertical and horizontal dots of the screen to be displayed is set in the display resolution setting section 1302, and the number of vertical and horizontal dots of the liquid crystal panel 1314 is set in the liquid crystal panel resolution setting section 13.
Set to 03. Each of these settings may be in the form of inputting the number of dots in the vertical and horizontal directions, or may be in the form of selecting the display mode by storing the relationship between the specific display mode and the resolution in each of these setting units in advance. The calculation unit 1304 calculates (the number of vertical dots of the screen to be displayed) ÷ (the number of vertical dots of the connected liquid crystal panel) according to each resolution set by the display resolution setting unit 1302 and the liquid crystal panel resolution setting unit 1303. Two calculations of (the number of horizontal dots of the screen to be displayed) ÷ (the number of horizontal dots of the connected liquid crystal panel) are performed to calculate the reduction or enlargement ratio of the vertical and horizontal display data to be displayed on the display panel 1314. Based on the reduction or enlargement ratio thus obtained, the data conversion unit 1307 having the density conversion function reduces or enlarges the video data input from the video data input unit 1305, and writes it in the memory 1313 via the memory interface unit 1309. The data written in the memory 1313 is read by the memory controller unit 1308, and the memory interface unit
The data output unit for liquid crystal display 1311 through 1309 and in synchronization with the signal generated by the liquid crystal display timing generation unit 1310.
LCD panel 131 according to the timing for LCD panel
Output to 4. If the vertical / horizontal ratio of the screen you want to display is different from the vertical / horizontal ratio of the LCD panel 1314, the calculation unit 1304 will expand or contract to fill the screen of the LCD panel 1314, so the input data will be different. The image is displayed. In order to suppress this phenomenon, if the vertical or horizontal display data calculated in advance by the calculation unit 1304 is used, whichever has the smaller reduction or enlargement ratio, and the data conversion unit 1307 reduces or enlarges the liquid crystal panel. The 1314 display has L for liquid crystal display
It is displayed as an image similar to the video data input to SI 1301.

FIG. 14 shows a second embodiment of the prior art,
In contrast to the first embodiment shown in FIG. 13, the display resolution setting unit
A different point is that a video resolution identifying section 1401 is arranged instead of 1302, and at least one of a horizontal synchronizing signal and a vertical synchronizing signal of the video data input is inputted as a synchronizing signal 1402 from a video timing input section 1306. In the present embodiment, the display mode is set so that the number of vertical and horizontal dots of the screen to be displayed can be identified by a specific horizontal and / or vertical sync signal whose screen resolution is predetermined. The resolution identifying section 1401 identifies and supplies the identification information to the computing section 1304 to ensure a similar data conversion function.

FIG. 15 shows a third embodiment of the prior art,
It differs from the first embodiment shown in FIG. 13 in that a liquid crystal panel resolution register 1501 is arranged in the arithmetic unit 1304 instead of the liquid crystal panel resolution setting unit 1303. In this embodiment,
When a liquid crystal panel 1314 with a predetermined resolution is connected, the information of the liquid crystal panel resolution register 1501 in which the resolution is already fixed in the calculation unit 1304 and the display resolution input from the display resolution setting unit 1302 Using and, the calculation unit 1304 calculates the reduction or enlargement ratio.

[0011]

However, in the prior art, although the liquid crystal display panel can be controlled, since the control circuit is integrated into one chip LSI and controlled, high resolution and simultaneous multicolor display are realized. If such an attempt is made, the required display data bus width becomes large, and the dot clock frequency also becomes high, which causes a problem of LSI pin neck and heat generation.

Further, in the prior art, various input video data can be enlarged or reduced according to the specifications of the liquid crystal display panel. However, when high resolution and simultaneous multicolor display are possible, it is low. There was a problem that LSI was over-specified and memory was installed more than necessary when it was used in a limited application where the resolution or simultaneous display color was small.

An object of the present invention is to provide R, R when the required specifications of the liquid crystal display panel are high resolution and simultaneous multicolor display.
Uses an LSI that controls G and B display data independently.
Any one of the LSIs (for example, R color LSI)
It is to provide a liquid crystal display control device that satisfies the required specifications of the liquid crystal display panel by controlling the synchronization between the master chip and the slave chips by using the master chip as the master chip and the remaining two LSIs as the slave chips.

Another object of the present invention is to provide an LSI having an object to control R, G and B independently when the required specifications of the liquid crystal display panel are low resolution or there are few simultaneous display colors. An object of the present invention is to provide a liquid crystal display control device that satisfies the required specifications of a liquid crystal display panel by reallocating all the display data of R, G, B to the display data input / output terminals by using only one or two. .

Still another object of the present invention is to control liquid crystal display L
By converting the input / output display data of SI into 2 parallel, R, G, B display as non-parallelized data for low resolution required specifications and 2 parallel data for required specifications with few simultaneous display colors. An object of the present invention is to provide a liquid crystal display control device that satisfies a plurality of liquid crystal display panel required specifications with one circuit configuration by allocating data to an LSI.

Still another object of the present invention is that each of the R, G and B control LSIs independently controls the frame and line memory necessary for scaling the input display data and displaying it on the liquid crystal display panel. By doing so, it is possible to optimize the number of display control LSIs, frames and line memories used according to the required specifications of the liquid crystal display panel, and to reduce the circuit scale, reduce power consumption, and reduce costs. An object is to provide a liquid crystal display control device in consideration.

[0017]

In order to achieve the above object, the present invention provides an LSI for processing a video display signal from a personal computer or the like with R, G, and R corresponding to the required specifications of a liquid crystal display panel. LSI configured independently for each B color
Multiplexed functions.

When the required specifications of the liquid crystal display panel are high resolution and simultaneous multicolor display, three LSIs that control R, G, and B independently are used and the LSIs are controlled to be synchronized with each other. Therefore, the required specifications of the liquid crystal display panel can be satisfied.

Specifically, the required specifications of the liquid crystal display panel are as follows: resolution 1024 × 768 dots (XGA mode), simultaneous display color 16 million colors (full color mode),
In the case of a 2-parallel display data bus configuration, the input display data bus width of each R, G, B LSI is 16 bits, the output display data bus width is 12 bits, and the operating frequency is about 35 MHz (dot clock frequency is double 70 MHz). It can be realized by setting).

Next, when the required specifications of the liquid crystal display panel are low resolution or the number of simultaneous display colors is small, one or two of the three LSIs for controlling R, G and B independently. The individual pieces can be used to perform control to satisfy the required use of the liquid crystal display panel.

Specifically, when the liquid crystal display panel has the required specifications of a resolution of 640 × 480 (VGA mode), simultaneous display colors of 16 million colors (full color mode), and a non-parallel display data bus configuration, the above LSI is used. The operating frequency is about 32MHz by using two (dot clock frequency corresponds to 32MHz), R color data on 8 bits of display data bus of one LSI, G color data on the remaining 8 bits, and 8 of another LSI.
The required specifications can be satisfied by allocating G color data to the bits.

The required specifications of the liquid crystal display panel are as follows: resolution 1024 × 768 (XGA mode), simultaneous display color 256 colors,
In the case of a 2-parallel display data bus configuration, the LSI is 1
Allocate an operating frequency of about 35 MHz (dot clock frequency corresponds to 70 MHz, which is doubled), and allocate 6 bits each for R and G colors and 4 bits for B color to 16 bits of display data bus of LSI. Can meet the required specifications.

Further, the display control LSI for realizing high resolution and simultaneous multicolor display is equipped with a control function for scaling and displaying an input video signal, and the frame and line memory control required for scaling processing is R, L for G and B
Demand for the liquid crystal display panel that controls by mounting each one or two LSIs by controlling each SI chip and performing all interface control of the liquid crystal display panel by any one LSI chip In the case of the specifications, the frame and line memory corresponding to the unused LSI can also be deleted.

The present invention changes the data allocation to the display data terminal of the display control LSI according to the specifications of the resolution and the number of simultaneous display colors of various video signals output from a personal computer or the like, thereby displaying the system. It is possible to realize a liquid crystal display device optimized to specifications. That is, when the display specifications require high resolution and simultaneous multicolor display, three display control LSIs are used,
The number of data bits processed in one cycle at a high frequency is increased corresponding to each color of R, G, and B. Conversely, when the display specifications are low resolution or the number of simultaneous display colors is small, one or two display control LSIs are used.
By allocating the data to the display data terminal or changing the dot clock frequency, it is possible to reduce the number of data bits processed in one cycle or to process at a low frequency. To sum up, by using one type of display control LSI, it is optimized for the system by setting the number to be used, data allocation to display data terminals, and dot clock frequency according to the display specifications of the system. It can be used as a display control device.

[0025]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram of a liquid crystal display control device according to a first embodiment of the present invention.

In FIG. 1, 101 is a personal computer that outputs a video signal, and 102 to 104 are personal computers.
R, G, B analog video data output from 101, 10
5 is an input horizontal synchronizing signal (hereinafter, IHSYNC-N), 106 is an input vertical synchronizing signal (hereinafter, IVSYNC-N), 107 to 109
Is a 16-bit A / D converter that digitizes R, G, B analog video data 102-104, and 110-112 is an A / D
16-bit digital R, G, B video data output from the converters 107 to 109, 113 is a PLL circuit for the purpose of dot clock generation, 114 is a dot clock, and 115 to 11
7 is R, G, B display control LSI, 118-120 is R, G, B
Frame memory, 121 to 123 are R, G, B line memories,
124 to 126 are R, G and B output display data output from the R, G and B display control LSIs 115 to 117, 127 is an output horizontal synchronizing signal (hereinafter referred to as OHSYNC-N), and 128 is an output vertical synchronizing signal ( Hereinafter, OVSYNC-N), 129 is an output dot clock (hereinafter, ODOTCLK), 130 is an output display effective pulse (hereinafter, ODSPTMG), 131 is R, G, B display control L
A microcomputer that performs various SI settings, 132 is an external oscillator, 133
Is a liquid crystal drive driver control LSI (two parallel data bus configuration), 134 is a column driver, 135 is a common driver,
Reference numeral 136 denotes a liquid crystal display panel.

The liquid crystal display control device according to the present embodiment has the above-mentioned configuration, and each of the R, G, B A / D converters 107-
Digital R, G, B display data output from 109 110
Display control LSIs 115 to 117,
The processing is performed by the frame memories 118 to 120 and the line memories 121 to 123, and the display control LSI 115 for R color is used as a master chip, and the master chip is controlled by the driver control LSI.
OHSYNC-N 127, OVSYNC-N 128, ODOTCLK to control 133
Outputs 129 and ODSPTMG 130, and further R color display control LSI
The OHSYNC-N 127 output from 115 is the slave chip G color display control LSI 116, B color display control LSI 117.
To enable synchronization between the master / slave chip LSI.

The outline of the operation of the liquid crystal display control device of this embodiment will be described below with reference to FIG.

Table 1 shows, by way of example, typical display specifications of resolution, number of simultaneous display colors, data bus width, and dot clock frequency.

[0031]

[Table 1]

In the embodiment shown in FIG. 1, the input data and the display panel specifications are the high resolution (XGA) shown in No. 6 of Table 1.
Mode: 1024 x 768 dots), full color display (16 million colors can be displayed simultaneously), and the dot clock frequency is as high as 65MHz, so the data bus configuration will be 2 parallel configurations. First, personal computer 10
1 to R, G, B analog video signals 102 to 104 and IHS
YNC-N 105 and IVSYNC-N 106 are output. The R, G, B analog video signals 102-104 are input to the corresponding 16-bit A / D converters 107-109 and output as digital R, G, B display data 110-112. The output digital R, G, B display data 110 to 112 is 2
Due to the parallel data bus configuration, each is a 16-bit wide bus. At the same time, IHSYNC-N 105 PLL circuit
Input to 113 and generate dot clock 114. Since the dot clock 114 generated here has a 2-parallel data bus configuration, it can be lowered to a frequency (32.5 MHz) that is half the dot clock frequency (65 MHz) in the non-parallel data bus configuration. Frame memory installed to support input / output timing arbitration and scaling
~ 120 digital R, G, B display data 110 ~ 112,
The frame memory write control signals output from the R, G, B display control LSIs 115 to 117 are written at the timing of A / D conversion (the cycle of the dot clock 114).
The reading from the frame memories 118 to 120 is performed at the timing of the display output control clock output from the external oscillator 132 in order to satisfy the required timing of the driver control LSI 133. The R, G, B display data read from the frame memories 118 to 120 are R, G, B display control L
Enter in SI 115-117. When performing scaling processing At the same time, the R, G, and B line memories 121 to 123
However, in this embodiment, since the input / output resolution specifications are the same, scaling processing is not performed and the line memory 121 to
Writing to 123 is also not performed (that is, the line memory can be unmounted in this embodiment). The input display data specifications are based on IHSYNC-N 105 and IVSYNC-N 106
The determination is made in 131, and various settings of the R, G, B display control LSIs 115 to 117 are performed. R, G, B display control LSI 115-117
R, G, B output display data output by
Is divided into four gradations according to the data of the lower 2 bits according to the data of the lower 2 bits by the pseudo color function of the FRC control unit inside the LSI, and each of the 6 bits (2 parallel buses). Therefore, full-color (16 million colors) can be displayed with 12 bits, and input to the driver control LSI 133 at the timing of the display output control clock generated by the external oscillator 131. At the same time, OHSYNC-N 127, OVSYNC-N 128, ODOTCLK 129, O
The DSPTMG130 is output to the driver control LSI 133. The driver control LSI 133 receives these control signals, R, G,
Column driver 1 according to B output display data 124-126
34, common driver 135 is controlled, and liquid crystal panel 136 is displayed. Further, R, G, B display control LSIs 115 to 117
The synchronization control between them is performed by using the OHSYNC-N 127 output from the R color display control LSI 115 which is the master chip as the input horizontal synchronization signal (IHSYNC-N 105) and the G color display control LSI 116 and B color which are the slave chips. It is realized by inputting to the display control LSI 117.

According to this embodiment, when the input data and display panel specifications are compatible with high resolution (XGA mode: 1024 × 768 dots) and full color display (16 million colors can be displayed simultaneously), R, G, B display is possible. Each of the control LSIs 115 to 117 has a total of 44 data bus terminals for input and output (28 if the input data from the line memories 121 to 123 is deleted), and the dot clock frequency can be suppressed to 35 MHz or less. Therefore, even if other input / output signals, power supply, and ground terminals are included, a QFP with about 120 to 130 pins is included.
Can be realized in a package. When the liquid crystal display according to this specification is realized by a single-chip LSI according to the conventional technique, it is necessary to use a PGA package because of a pin neck and heat generation due to power consumption, which leads to an increase in total cost.

FIG. 2 shows R, G, B display control LSIs 115 to 11.
7 is a block diagram of the inside of FIG.

In FIG. 2, 201 is an input buffer unit, 202 is a register unit, 203 is a master / slave chip control unit, 204 is a frame / line memory control unit, 205 is an OSD control signal generation unit, and 206 is an output control signal generation unit. Section, 207 is a scaling data processing section, 208 is an FRC data processing section, and 209 is an OSD.
A data processing unit 210 indicates an output buffer unit. First, IHS
The microcomputer determines the state of YNC-N 105, IVSYNC-N 106,
The setting data for setting the display control LSI 115 is
It is input to the register unit 202 via the input buffer unit 201. According to the setting value of the register unit 202, the frame / line memory control signal generation unit 204, the OSD control signal generation unit 2
05, the output control signal generation unit 206 generates each control signal.
Here, the OSD control signal generation unit 205 is for displaying an adjustment menu on the screen when adjusting the liquid crystal display device. In the case of the first embodiment shown in FIG. 1, as the display data, the output data of the frame memory is the input buffer section.
It is input to the scaling data processing unit 207 via 201. In the scaling data processing unit 207, since the input display data and the display panel have the same resolution (1024 × 768), the through mode processing is performed and the display data is output as it is. At this time, since the line memory is not accessed, no data is input from the line memory. The 16-bit display data from the scaling data processing unit 207 is F
Input to RC data processing unit 208. FRC data processing unit
With the 208, the number of simultaneous display colors can be increased by subdividing the number of gradations, and full-color (16 million colors) can be displayed even if the output display data bus width is reduced from 16 bits to 12 bits. is there. The 12-bit display data from the FRC data processing unit 208 is the OSD data processing unit 2 in the next stage.
Enter 09. The OSD data processing unit 209 overlays the bitmap data read by the external bitmap memory control signal output by the OSD control signal generation unit 205 on the display data from the FRC data processing unit 208 only when an adjustment instruction is issued. And output. This output data is sent to the driver control LSI via the output buffer unit 210.
The output display data 124 is output to 133. In parallel with this display data processing, the frame / line memory control signal generation unit 204 performs the PLL memory write control on the frame memory.
The dot clock 114 output from the circuit 113 and the read control are performed based on the clock from the external oscillator 132, and the output control signal generator 206 uses the OHSYNC-N 127 and OVSYNC-N 128 based on the clock from the external oscillator 132. , ODOTCLK 129, ODS
Generate PTMG 130. Further, the master / slave chip discrimination control is performed by the master / slave control unit 203, and the master chip (R color display control LSI 115) uses IHSYNC.
-N 105 is input to the LSI as an input horizontal sync signal, and OHSY
NC-N 127 is output as an output horizontal sync signal. In the slave chip (G, B color display control LSI 116, 117), the OHSYNC-N 127 output from the master chip is input as an input horizontal synchronization signal from the OHSYNC-N 127 terminal which is a bidirectional terminal, so that the master / slave chip Synchronize between.

FIG. 3 shows the master / slave control section in FIG.
FIG. 3 is a logic diagram of 203 and an output horizontal synchronization signal generation unit in the output control signal control unit 206.

In FIG. 3, 301 is an input signal (hereinafter referred to as CHIPSEL1: 0) for determining the master / slave of the LSI, 30
2, 306, 309 are NOR gates, 303 is a bidirectional buffer, 30
4, 305, 307, 308, 313 are latches, 310 is an internal horizontal sync signal generation unit that operates during scaling expansion processing, 311, 312
Indicates a selector circuit.

Table 2 shows the states of the bidirectional buffer 303 and the selector 312 according to the settings of CHIPSEL0,1 301.

[0039]

[Table 2]

From FIG. 3 and Table 2, when CHIPSEL1: 0 301 is set to (0,0), the LSI becomes a master chip (R color display control LSI), and the output of the gate 302 causes the bidirectional buffer 303 to output. The selector 312 selects the (a) side.
In this state, the input horizontal synchronizing signal becomes IHSYNC-N 105, and the latches 307, 308, 313, NOR gate 309, selectors 311 and 312 (when the selector 311 is in the through mode, are generated by the internal horizontal synchronizing signal generator 310). Always select (a) because no horizontal sync signal is required), bidirectional buffer 30
The output horizontal sync signal (OHSYNC-N 127) is output via 3. Therefore, from IHSYNC-N 105 to OHSYNC-N 127 (that is,
The delay until the horizontal synchronizing signal used inside the LSI = the output of the latch 313 is the output control clock 3 of the external oscillator 132.
It is the clock. Then CHIPSEL1: 0 301 is set to (0,1)
Alternatively, in the case of (1,0), the LSI is a slave chip (G
Color or B color display control LSI), the bidirectional buffer 303 is in the input state by the output of the gate 302, and the selector 31
2 selects side (b). In this state, the input horizontal sync signal is OHSYNC-N 127 output from the master chip,
Latches 304, 305, 313, NOR gate 306, selector 31
The output of the latch 313 via 2 becomes the horizontal synchronizing signal used inside the LSI. For slave chips, this LS
The delay of the horizontal sync signal used inside I is 6 clocks from IHSYNC-N 105 input to the master chip,
A phase difference of 3 clocks occurs in the horizontal synchronization signal used inside the LSI between the master / slave chips. Therefore,
The LSI set in the slave mode controls the output horizontal counter control unit 314 to start counting from '3' after the internal horizontal output counter is cleared, thereby matching the phase between the master and slave chips.

FIG. 4 shows a timing chart of the output horizontal synchronization counter of each master / slave chip.

In the first embodiment shown in FIG. 1, by using three display control LSIs according to the present development, the display of the display specification (item No. 6) having the largest data processing amount in Table 1 is realized. Therefore, by using this configuration, it is possible to satisfy all other display specifications shown in Table 1. Furthermore, item numbers 1 to 4
For the VGA and SVGA mode display specifications of
In addition to through display, enlarged display by scaling processing is also possible. At this time, the display quality can be changed depending on whether the line memories 121 to 123 are installed.

FIG. 5 is a block diagram of a liquid crystal display control device according to a second embodiment of the present invention.

In the present embodiment, among the display specifications shown in Table 1, the low resolution (VGA mode: 640 × 480 dots) and full color display (capable of simultaneous display of 16 million colors) shown in item No. 2 are supported. Dot clock frequency is 31.5MHz
The data bus configuration is non-parallel because it is low (almost the same as that of the two parallel data buses in the XGA mode). In this case, the data bus width is 24 bits for all R, G, and B, and the dot clock frequency is 31.5 MHz. Therefore, the display control LSI shown in the first embodiment of FIG. can do.

In FIG. 5, R, G, B analog video signals 102 to 104 and IHSYNC-N 10 are sent from the personal computer 101.
5, IVSYNC-N 106 is output. The R, G, B analog video signals 102 to 104 are input to the corresponding 8-bit A / D converters 501 to 503, and the 8-bit digital R,
The G and B image data 504 to 506 are output. The output R, G, B display data 504 to 506 each have an 8-bit width because of the non-parallel data bus structure. R,
The 8-bit digital display data for G and B are R color and
The G color display data 504 and 505 are input to the frame memory 118, and the B color display data 506 is input to the frame memory 119. The subsequent operation is the same as that of the first embodiment shown in FIG. However, the B color display data processing frame memory 119, line memory 122, display control LSI 116
Since the display data bus of (1) requires only 8 bits for input and 6 bits for output, the upper half is unused. Further, the driver control LSI 507 is compatible with the non-parallel display data bus.

As described above, in the second embodiment shown in FIG. 5, the display specifications are low resolution (VGA mode) and simultaneous multicolor display (16
In the case where the number is limited to (million colors), it is possible to reduce the display control LSI according to the present development and the corresponding frame memory and line memory.

FIG. 6 is a block diagram of a liquid crystal display control device according to a third embodiment of the present invention.

In the present embodiment, among the display specifications shown in Table 1, the medium resolution (SVGA mode: 800 × 600 dots) shown in item No. 3 and 256 color simultaneous display are supported, and the dot clock frequency is 50 MHz. Since the cost is high, the data bus configuration is a 2-parallel configuration. In this case, the data bus width is 25
8 bits in total for all R, G, and B for 6-color display
2 parallel = 16 bits, dot clock frequency is 25MH
z, the display control L shown in the first embodiment of FIG.
It can be realized by mounting one SI.

In FIG. 6, a personal computer 101 outputs R, G, B analog video signals 102 to 104 and an IHSYNC-N 10 signal.
5, IVSYNC-N 106 is output. The R, G, and B analog video signals 102 to 104 are input to the corresponding 6-bit A / D converters 601 to 603, and the 6-bit digital R and G signals are input.
Data 604, 605 and 4-bit digital B video data 60
It is output as 6. In order to display 256 colors at the same time, a total of 8 bits of R, G, and B (1 for 2 parallel configurations)
6 bits), but in the present embodiment, 3 bits each for R and G colors (6 bits for 2 parallel configuration) and 2 bits for B color (4 bits for 2 parallel configuration) are allocated. The output 16-bit R, G, B display data are all input to the frame memory 118. The subsequent operation is the same as that of the first embodiment shown in FIG. However, since only one display control LSI 115 is mounted, there is no master / slave chip relationship and synchronization control between LSIs is not required.

As described above, in the third embodiment shown in FIG. 6, in the case where the display specifications are limited to the medium resolution (SVGA mode) and the simultaneous display of 256 colors, the second embodiment shown in FIG. It is possible to reduce the display control LSI and the corresponding frame memory and line memory by this development.

As described above, in the display specifications of Table 1, the same applies to the cases other than the first to third embodiments shown in FIGS. 1, 5 and 6.
With the number of display control LSIs mounted in Table 1, each optimized display control device can be realized.

7 to 9 are block diagrams of the liquid crystal display control device according to the fourth to sixth embodiments of the present invention.

In the present embodiment, there is shown a configuration diagram in the case where the scaling processing is not performed and only the through mode is displayed in contrast to the first to third embodiments shown in FIGS. In this case, since the input / output display data is synchronized with the timing of the dot clock 114 output from the PLL circuit 113, the frame memories 118 to 120 and the line memory 121 are synchronized.
It is possible to not install ~ 123.

10 to 12 are block diagrams of a liquid crystal display control device according to the seventh to ninth embodiments of the present invention.

In this embodiment, the personal computer 1 is different from the first to third embodiments shown in FIGS. 1, 5 and 6.
The configuration diagram when the R, G, B display data output from 01 is digital data from a feature connector or the like is shown. In this case, the A / D converter becomes unnecessary and the display data from the personal computer can be directly input to the frame memories 118 to 120. Furthermore,
The dot clock 114 generated by the PLL circuit 113 is also
Since the clock output from the personal computer 101 can be directly input to the display control LSI, the PL
The L circuit 113 is also unnecessary.

[0056]

According to the present invention, one type of display control LS
Since the number of mounted I is changed according to the display specifications of the entire system, the liquid crystal display device can be optimized for the system.

Also, since the number of corresponding frame / line memories to be mounted is determined according to the number of display control LSIs to be mounted, the effects of downsizing the circuit scale, lowering power consumption, and reducing costs can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram of a liquid crystal display control device that is a first embodiment of the present invention.

FIG. 2 is a block diagram inside a display control LSI of the present invention.

FIG. 3 is a circuit diagram of a master / slave control inside the display control LSI of the present invention and an output horizontal synchronization signal generation unit.

FIG. 4 is a timing chart showing the operation of the output horizontal synchronization counter of each of the display control LSI master / slave chips of the present invention.

FIG. 5 is a block diagram of a liquid crystal display control device according to a second embodiment of the present invention.

FIG. 6 is a block diagram of a liquid crystal display control device that is a third embodiment of the present invention.

FIG. 7 is a block diagram of a liquid crystal display control device that is a fourth embodiment of the present invention.

FIG. 8 is a block diagram of a liquid crystal display control device that is a fifth embodiment of the present invention.

FIG. 9 is a block diagram of a liquid crystal display control device according to a sixth embodiment of the present invention.

FIG. 10 is a block diagram of a liquid crystal display control device that is a seventh embodiment of the present invention.

FIG. 11 is a block diagram of a liquid crystal display control device according to an eighth embodiment of the present invention.

FIG. 12 is a block diagram of a liquid crystal display control device according to a ninth embodiment of the present invention.

FIG. 13 is a block diagram showing a first embodiment of a conventional liquid crystal display control LSI.

FIG. 14 is a block diagram showing a second embodiment of a conventional liquid crystal display control LSI.

FIG. 15 is a block diagram showing a third embodiment of a conventional liquid crystal display control LSI.

[Explanation of symbols]

101 ... Personal computer, 107-109 ... R, G, B
16-bit A / D converter, 110 to 112 ... 16-bit digital R, G, B video data, 113 ... PLL circuit, 114 ...
Dot clock, 115-117 ... R, G, B display control LS
I, 118 to 120 ... R, G, B frame memories, 121 to 123 ...
R, G, B line memory, 124-126 ... R, G, B output display data, 129 ... Output dot clock, 130 ... Output display valid pulse, 131 ... Microcomputer, 132 ... External oscillator, 133 ... Liquid crystal drive driver control LSI , 134… Column driver, 135
… Common driver, 136… Liquid crystal display panel.

Front page continuation (72) Inventor Akihiro Higa 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Hitachi Imaging Information Systems Co., Ltd. (72) Inventor Hiroshi Kurihara 3300 Hayano, Mobara-shi, Chiba Hitachi Ltd (72) Inventor Naruhiko Kasai 1099, Ozenji, Aso-ku, Kawasaki-shi, Kanagawa Ltd. System Development Laboratory, Hitachi, Ltd.

Claims (8)

[Claims] 1. A liquid crystal display control device for displaying analog and digital video signals from a personal computer on a liquid crystal display panel, wherein red, green, and blue digital data are provided in accordance with the timing required by the liquid crystal display panel and the number of pixels. A liquid crystal display control device characterized by being capable of sending out. 2. The three-color digital data control applied to the liquid crystal display panel is configured by three independent LSIs, one of the LSIs being a master chip, and the remaining two LSs.
2. The liquid crystal display control device according to claim 1, wherein I is a slave chip and the timing of the slave LSI is synchronized with the operation timing of the master LSI. 3. The liquid crystal display control device according to claim 1, wherein each of the three color digital data is controlled by an independent LSI. 4. The liquid crystal display panel is limited in its use, and in a required specification with a small number of simultaneous display colors, all the three-color digital data are supplied to a single LSI that individually controls the three-color digital data. The liquid crystal display control device according to claim 1, wherein the liquid crystal display control device is allocated. 5. Use of two LSIs, each of which controls each of the three-color digital data independently, with a required specification that the liquid crystal display panel is used for low resolution or medium resolution.
2. The liquid crystal display control device according to claim 1, wherein the three-color digital data is allocated to the two LSIs, and one of the LSIs is a master LSI and the other is a slave LSI for synchronization control. 6. A liquid crystal display panel that requires high resolution by converting input / output display data controlled by the liquid crystal display control LSI chip into two parallel data,
It is possible to control the frequency by halving it. Further, for a liquid crystal display panel which has a low resolution but is required to display multiple colors simultaneously, the display data which has been parallelized to 2 is allocated as non-parallelized data. Item 2. The liquid crystal display control device according to item 1. 7. A liquid crystal display control LSI chip is provided with a frame memory and a line memory, which are necessary when scaling and displaying input display data on a liquid crystal display panel.
The liquid crystal display control device according to claim 1, wherein each of the G and B display control LSIs independently controls a corresponding memory. 8. The number of mounted display control LSIs according to the required specifications of the liquid crystal display panel, the parallelization of the display data controlled by the LSIs to two parallels, and the reduction of the frame and line memories accompanying the reduction of the display control LSIs. 1. The liquid crystal display control device according to 1.