JPH09233060A - Clock supply system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a clock supply system capable of evaluating the function only by a board itself without necessitating a special jig or an external device for clock supply. SOLUTION: An oscillator 104 that generates a local clock specific to each board is provided to each board 10. Then the local clock generated from the oscillator 104 is used in place of a global clock received from the other boards to generate an operating clock for LSIs (102-1, 102-1,..., 102-n) of each board 10.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock supply system in an exchange system or the like composed of a plurality of boards, and more particularly to a clock supply system constructed so that the function evaluation can be performed even with a single board.

[0002]

2. Description of the Related Art Conventionally, when constructing a large-scale system such as an exchange, a bookshelf type is generally used in which the system is divided into units according to functions and each unit is formed from each board.

For example, the line interface unit of the exchange system is located between the line and the switching unit. The line interface unit is unitized from the viewpoint of expandability of the accommodated line and the unitized line is used. The interface unit and the switching unit, which are similarly unitized, are integrated into one board, and these boards are connected via a mother board.

By the way, the ATM communication system is constructed to handle data in a fixed length format called a cell. Even in the ATM switching system for transferring and exchanging in units of cells, the line cell data is transmitted as described above. In many cases, a line interface section for interfacing with the transfer cell data in the system and an ATM switch section for switching to a desired speech path by a header are unitized, and each unitized circuit is configured on a different substrate. .

In the above-mentioned structure, since the cells are transferred between the substrates, the processing is performed by hardware,
It is essential that cell synchronization and bit synchronization be taken.

Therefore, each substrate needs to have a function of performing speed conversion, phase absorption, overflow control, etc. These functions are specifically realized by a cell buffer or the like by a storage device such as a memory. There is.

However, if the operation clocks between the substrates are not synchronized, even if there is a cell buffer or the like, it overflows, causing cell loss.

Therefore, in order to synchronize the operation between the boards, it is necessary to operate the entire system, that is, the boards with the synchronized clocks. In that case, the clock supply is as follows. Has been realized.

FIG. 6 shows one conventional clock supply system in which the operating clock of each board is obtained from a reference clock. In FIG. 6, 10 is a board, 102-1 and 102.
-2, ..., 102-n are various LSIs (integrated circuits) mounted on the substrate 10, and 110 is a PLL (face locked loop) circuit for obtaining a clock synchronized with the reference clock.

In the conventional clock supply system shown in FIG. 6, data is input from the left side of the drawing in synchronization with a bit clock, and the LSIs 102-1 and 102 receiving the data are received.
-2, ..., 102-n transfer data to the output side while performing various processing such as cellizing data, converting cell format, adjusting cell flow rate, or exchanging according to cell header information. To be done.

Here, the respective LSIs 102-1 and 1-1
02-2, ..., 102-n receive a reference clock from a board (not shown) serving as a clock source in order to perform these processes in synchronization with the input data, and generate the reference clock based on the reference clock. Then, a clock synchronized with this reference clock is generated on the substrate 10 by the PLL circuit 110,
The LSI 102-1 uses this clock as an operation clock,
102-2, ..., 102-n.

However, in the conventional clock supply system shown in FIG. 6, the operation of the substrate 10 alone cannot be confirmed unless the data and the reference clock are input.

FIG. 7 shows another conventional clock supply system using the input bit clock as an operating clock of the board. In the clock supply system shown in FIG. 7, the bit clock is shown in FIG. Since it also serves as the reference clock, the wiring for the reference clock and the PLL circuit 110 shown in FIG. 6 are not required, which is advantageous in terms of mounting area of components, cost, etc., but the clock supply system shown in FIG. Similar to the clock supply system shown in FIG. 6, there is a problem that the operation of the substrate 10 alone cannot be confirmed unless the data and bit clock are input.

[0014]

As described above, according to the conventional clock supply system, there is no clock source on the board, and the clock source of another board is used as the operation clock of various functional LSIs mounted on the board. Since it was configured to use the clock (global clock), the operation of this board cannot be confirmed unless the board having the clock source is connected.

This means that a jig or an external device for supplying a clock corresponding to the global clock from the clock source is required when this board is evaluated alone.

Further, when a situation occurs in which the global clock from the clock source of another board is not supplied at the time of an accident, it is difficult to identify the location of the accident.

Therefore, it is an object of the present invention to provide a clock supply system that enables the evaluation of the function of a single board without requiring a special jig or an external device for supplying the clock.

[0018]

In order to achieve the above object, the present invention comprises a plurality of substrates, and the operating clock of each substrate is created based on the global clock by passing a global clock between the substrates. In the clock supply system in the electronic device system for integrally controlling the entire system, clock generating means for generating a local clock unique to each board corresponding to each board, and the local clock from the clock generating means to the global clock. An operation clock generating means for generating an operation clock for each of the substrates by using it instead is provided.

According to the present invention, clock generating means for generating a local clock unique to each board is provided for each board, and the local clock generated by the clock generating means is used in place of the global clock by the operation clock generating means. As a result, an operation clock for each board is generated.

As a result, even if the global clock from the board serving as the clock source is shut off due to an accident or the like, each of the boards is based on the local clock generated by the clock generating means provided corresponding to each board. Since it is possible to generate an operation clock for each board, it is possible to operate each board independently by this operation clock, which makes it possible to evaluate the function of each board alone, and The identification can be performed quickly, and no special jig or external device for supplying a clock is required for this functional evaluation.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a clock supply system according to the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a functional board constructed by applying the clock supply system of the present invention.

In FIG. 1, 10 is a substrate, 101 is a selector, 102-1, 102-2, ..., 102-n are various LSIs mounted on this substrate 10, 103 is a CPU mounted on the substrate, and 104. Is a clock oscillator that generates a system clock for the CPU 103.

In the structure shown in FIG. 1, normally,
The selector 101 is switched so as to select the bit clock side from another board. In this case, the bit clock supplied with data from another board (not shown) is supplied to the LSI 102-1 via the selector 101,
102-2, ..., 102-n to supply each LSI 102
, 102-2, ..., 102-n operate using this bit clock as an operation clock.

However, when the bit clock is not supplied from another board constituting the clock source, the selector 101 is switched to the clock oscillator 104 side which generates the system clock for the CPU 103.

As a result, each of the LSIs 102-1 and 102
The system clock for the CPU 103 generated from the clock oscillator 104 is supplied to the -2, ..., 102-n as a local clock via the selector 101.

In this case, each of the LSIs 102-1 and 102-
, ..., 102-n operate using the system clock (local clock) for the CPU 103 generated from the clock oscillator 104 as an operation clock.

According to such a configuration, even if the bit clock from another board serving as a clock source is not supplied, it is possible to evaluate the function of the board 10 alone.

In this embodiment, the CPU 10
3 is configured to generate the local clock by using the output of the clock oscillator 104 that generates the system clock for the third clock. However, instead of the clock oscillator 104, a dedicated clock oscillator for generating the local clock is provided. May be.

However, in order to perform complicated processing, this type of substrate 10 is generally equipped with a CPU that integrally controls it, as shown in FIG.
If the clock oscillator for generating the system clock for the CPU 103 is used, it is very economical because no special oscillator needs to be provided.

In the configuration of FIG. 1, the system clock generated by the clock oscillator 104 for the CPU 103 is not synchronized with the bit clock supplied from another substrate which is a clock source (not shown). This synchronization is not always necessary to evaluate the functions of the 10 units alone.

FIG. 2 shows the LSI 1 of the substrate 10 shown in FIG.
02-1, 102-2, ..., 102-n, one L
It is a conceptual illustration of the case where the SI 102 functions as a cell buffer in ATM communication.

In this case, normally, the LSI 102 operates with a bit clock synchronized with an input cell supplied from another substrate serving as a clock source (not shown) as an operation clock.

By the way, if the bit clock from another board is cut off for some reason, in this case, the system clock for the CPU 103 generated from the clock oscillator 104 by the selector 101 instead of this bit clock. Is selected as a local clock, and the LSI 102 operates using this local clock as an operating clock.

Here, the transfer rate determined by the bit clock (global clock) from another board is fi, and the transfer rate determined by the local clock generated from the clock oscillator 104 is fo, and fi
Consider when> fo. In this case, in the cell buffer configured by the LSI 102, if all input cells are valid cells, this cell buffer will overflow, but if the load of the input cell is adjusted so that the cell buffer does not overflow, Can be evaluated independently.

That is, in the cell buffer used in the ATM switching system, the speed can be adjusted by inserting and discarding empty cells. Therefore, when adjusting a single substrate including this cell buffer, a local clock and a global clock are used. Do not necessarily have to be in sync.

FIG. 3 is a block diagram showing another embodiment of the functional board constructed by applying the clock supply system of the present invention. In the embodiment shown in FIG. 3, a bit clock normally supplied with data from another substrate (not shown) is added to the PLL circuit 105, and the PLL circuit 10 is supplied.
5, based on this bit clock, the LSIs 102-1 and 1
02-2, ..., 102-n, operation clocks are created, and the operation clocks are generated by the LSIs 102-1, 102-2 ,.
102-n to supply each LSI 102-1, 102-
2, ..., 102-n operate by this operation clock.

However, if the bit clock is not supplied from another board for some reason, or when the board 10 is tested alone, the PLL circuit 105 is controlled by the control unit 120. , The clock signal output from the PLL circuit 105 is supplied to the LSIs 102-1, 102-2, ..., 102.
As the operation clock of -n, the LSIs 102-1 and 102-
2, ..., 102-n to supply each LSI 102-1, 1
02-2, ..., 102-n operate by this operation clock.

FIG. 4 shows a specific configuration of the control unit 120 shown in FIG. In FIG. 4, the control unit 120 includes a reference voltage generating circuit including a resistor 121 and a variable resistor 122, and a changeover switch 123.

Further, the PLL circuit 105 includes the phase comparator 1
11, a low pass filter 112, a DC amplifier 113, a voltage controlled oscillator (VCO) 114, and a phase comparator 111.
Input the bit clock (input clock) from another board to the phase comparator 111 and input the input clock and VCO1.
Phase comparison with the output of 14
Of the output of the DC amplifier 113 via the low-pass filter 112
Input to the control unit 120.
It is configured to be applied to the voltage control input of the VCO 114 via the change-over switch 123.

In such a configuration, during normal operation, the changeover switch 123 of the control unit 120 is switched to select the output side of the DC amplifier 113, as shown in FIG. 4, and in this case, the PLL circuit 105. Performs a PLL operation in synchronization with the input pulse, and uses the output of the VCO 114 as an operation clock to generate the LSIs 102-1, 102-2,
, 102-n to supply the respective LSIs 102-1 and 102
-2, ..., 102-n are operated by this operation clock.

However, due to some reason, the bit clock from another board is not supplied, or when the board 10 is tested alone, the changeover switch 123 of the control section 120 is set to the control section 120. Resistance 12
1 and the variable resistor 122 is switched to the reference voltage generating circuit side. As a result, the PLL circuit 105 self-oscillates according to the output voltage of the reference voltage generating circuit composed of the resistor 121 and the variable resistor 122, and the clock signal output from the VCO 114 by this self-oscillating oscillation is used as the operation clock. LSIs 102-1, 102-2, ..., 1
02-n, and each LSI 102-
, 102-n are operated by this operation clock.

In the above-mentioned structure, especially when the substrate 10 is already PL
In the case of using the L circuit, it can be realized by a simple circuit change, and the number of parts to be added can be reduced accordingly.

FIG. 5 shows another specific configuration of the control unit 120 shown in FIG. In FIG. 5, the control unit 120 controls A / D (analog / digital) / D /
A (digital / analog) converter 125, register 1
26, and a clock loss detector 127.

Further, the PLL circuit 105 includes the phase comparator 1
11, a low pass filter 112, a DC amplifier 113, a voltage controlled oscillator (VCO) 114, and a phase comparator 111.
Input a bit clock (input clock) from another board to the phase comparator 111 and input the input clock and VCO1.
Phase comparison with the output of 14
Of the output of the DC amplifier 113 via the low-pass filter 112
Input to the control unit 120.
It is configured to be applied to the voltage control input of the VCO 114 via the A / D / D / A converter 125.

In such a configuration, during normal operation, the A / D / D / A converter 125 of the control unit 120 is configured to add the output of the DC amplifier 113 to the voltage control input of the VCO 114 as it is.

Therefore, in this case, the PLL circuit 105
Performs PLL operation in synchronization with the input pulse, and VCO1
The output of 14 is used as the operation clock, and LSIs 102-1 and 1
02-2, ..., 102-n, and each LSI 102-
, 102-n are operated by this operation clock.

Further, during the above-mentioned normal operation, the A / D / D / A converter 125 of the control unit 120 causes the DC amplifier 1 to operate.
Register 1 after analog / digital conversion of 13 output
It is stored in 26 as a digital value.

By the way, when the bit clock is not supplied from another board due to some cause, and the disconnection of the bit clock is detected by the clock disconnection detector 127 of the control unit 120, or Board 1
0 When performing a single test, A / D ・ D / A
The converter 125 replaces the output of the DC amplifier 113 with the digital value stored in the register 126 as a digital / digital value.
Analog conversion is performed and a voltage signal corresponding to the digital value stored in the register 126 is output. This voltage signal is applied to the voltage control input of VCO 114 of PLL circuit 105.

As a result, the PLL circuit 105 has the A / D
・ Self-propelled transmission according to the output voltage of the D / A converter 125,
The clock signal output from the VCO 114 by this self-propelled transmission is the LSI 102-1 or 10 as an operation clock.
2-2, ..., 102-n are supplied to each L
SI 102-1, 102-2, ..., 102-n operate by this operation clock.

The above configuration is slightly more complicated than the configuration shown in FIG. 4, but with this configuration, an operation clock close to the operation clock during normal operation can be obtained. High reliability of the operation clock can be obtained in both cases.

[0052]

As described above, according to the present invention, clock generating means for generating a local clock unique to each board is provided for each board, and the operation clock generating means generates the clock from the clock generating means. Since it is configured to generate the operating clock of each board by using the local clock instead of the global clock,
When the global clock from the board that is the clock source is cut off due to an accident, etc., or even during a unit test, it is possible to generate an operating clock for each board based on this local clock.
It is possible to evaluate the function of each board alone, and to quickly identify the location of the accident. In addition, a special jig that supplies a clock for this functional evaluation and identification of the location of the accident. The effect is that no external device is required.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a functional board configured by applying a clock supply system of the present invention.

FIG. 2 is a diagram conceptually showing a case where the LSI of the substrate shown in FIG. 1 functions as a cell buffer in ATM communication.

FIG. 3 is a block diagram showing another embodiment of a functional board configured by applying the clock supply system of the present invention.

FIG. 4 is a block diagram showing a specific configuration of a control unit and a PLL circuit shown in FIG.

5 is a block diagram showing another specific configuration of the control unit and the PLL circuit shown in FIG.

FIG. 6 is a block diagram showing a conventional clock supply system.

FIG. 7 is a block diagram showing another conventional clock supply system.

[Explanation of symbols]

 10 substrate 101 selector 102-1, 102-2 ... 102-n LSI 103 CPU 104 oscillator 105 PLL circuit 111 phase comparator 112 low-pass filter 113 DC amplifier 114 VCO 120 control unit 121 resistance 122 variable resistance 123 changeover switch 125 A / D / D / A converter 126 register 127 clock loss detector

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location H04Q 11/04 304 9466-5K H04L 11/20 D

Claims (4)

[Claims] 1. A clock supply method in an electronic device system, comprising a plurality of boards, wherein each board transfers a global clock to create an operation clock for each board based on the global clock to integrally control the entire system. A clock generation means for generating a local clock unique to each board corresponding to each board, and an operation for generating an operation clock of each board by using the local clock in place of the global clock from the clock generation means A clock supply system comprising a clock generation means. 2. The clock generating means comprises a clock oscillator for generating a system clock of a central processing unit provided for each substrate, and the operation clock generating means replaces the global clock with the clock generator. 2. The clock supply system according to claim 1, further comprising a selection switch for selecting a system clock generated by the clock generation means, and generating the operation clock based on an output of the selection switch. 3. The clock generation means includes a PLL circuit that receives the global clock and creates an operation clock of each substrate based on the global clock, and the operation clock generation means presets the PLL circuit. 2. The clock supply system according to claim 1, wherein the operation clock is generated by self-propagating with the control voltage. 4. The clock generation means includes a PLL circuit that receives the global clock and creates an operation clock for each substrate based on the global clock, and the operation clock generation means includes the PLL based on the global clock. Storage means for storing a control voltage of the circuit; and, when the global clock is cut off, the operation clock is generated by self-oscillating the PLL circuit by the control voltage stored in the storage means. The clock supply system according to claim 1.