JPH09233009A - Space diversity synthesis circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent pull-in of an opposite phase in the case of in-phase synthesis. SOLUTION: An operation control means 9 activates a 2nd phase shift control means 8 for a prescribed time at a prescribed timing and then activates a 1st phase shift control means 7 so that a phase shift means 4 makes the phase of a 1st reception signal and the phase of a 2nd reception signal outputted from a reception means 3 to be matched with each other. At first, the operation control means 9 allows the 2nd phase shift control means 8 to control a phase shift of the phase shift means 4 so that a phase difference detected by a phase difference detection means 6 is converged to a 2nd phase difference region and then to control the phase shift quantity of the phase shift means 4 so that a phase difference detected by the phase difference detection means 6 is converged to a 1st phase difference region.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a space diversity combining circuit for performing in-phase combining, and more particularly to matching the phases of a plurality of received signals respectively received using a plurality of antennas arranged apart from each other. The present invention relates to a space diversity combining circuit for combining.

Under fading, transmission characteristics are greatly deteriorated. This is because the amplitude level of the received wave often drops close to the thermal noise level of the receiver, and the amplitude level of the received wave may become smaller than the interference wave level. In order to deal with this, there is so-called space diversity reception in which two or more fading waves are combined to reduce the probability of a drop in the amplitude level of the desired wave. High quality transmission can be realized by this method. In addition, in order to combine two or more fading waves, it is necessary to match their phases in advance and then combine them (in-phase combination).

[0003]

2. Description of the Related Art FIG. 10 shows the structure of a conventional space diversity combining circuit for performing in-phase combining. The same transmission signal is received by two different antennas (not shown) and input to terminals 11 and 12, respectively. The first reception signal input to the terminal 11 is directly input to the combiner 13, and the second reception signal input to the terminal 12 is input to the combiner 13 via the phase shifter 14, where the first reception signal is input. The signal and the second received signal are combined and sent to the AGC amplifier 15. The phase shifter 14 is intended to change the phase of the input signal by ψ _0, ψ ₀
Of the first received signal and the second received signal input to the combiner 13.
The signal is controlled by a phase shift control signal from the control unit 20 described later so that the received signal has the same phase.

In order to perform such control, the first reception signal
The signal is sent to the mixer 19 via the AGC amplifier 16, and the phase is shifted.
The second received signal that has passed through the converter 14 is the AGC amplifier 17 and
It is sent to the mixer 19 through the 90 ° phase shifter 18. AGC
The amplifiers 16 and 17 keep the level-changing signal constant.
To correct. The first received signal is sin (ωt +
ψ _m) And the second received signal passed through the phase shifter 14 is sin (ω
t + ψ_s+ Ψ₀) Is generated by the AGC amplifiers 16 and 17.
Phase delay_AThen, in the mixer 19,
sin (ωt + ψ_m+ Ψ_A) And cos (ωt + ψ_s+ Ψ₀+
ψ_A) Is entered. As a result, in the mixer 19, the ωt term
No component sin (ψ_m−ψ_s−ψ₀) And 2ωt term
The ingredients and are generated. Remove components containing 2ωt term
Component sin (ψ_m−ψ_s−ψ₀) Is controlled by the mixer 19
It is output to the unit 20. The control unit 20 receives the first received signal
And the phase difference between the second received signal that has passed through the phase shifter 14 (ψ_m
−ψ_s−ψ₀), The phase shift control signals sinV and cosV are created.
And outputs it to the phase shifter 14. The phase shifter 14 has a phase difference (ψ
_m−ψ_s−ψ₀) Becomes 0, that is, phase shift
Quantity ψ₀(= Ψ_m−ψ_s) With respect to the second received signal
Do it. As a result, the synthesizer 13 has the same first phase
And the second received signal will be sent.

FIG. 11 shows the internal structure of the control unit 20. The control unit 20 includes comparators 21 and 22, a counter 23, and a ROM.
24, a D / A converter 25, a clock generator 26 and the like. Output signal from mixer 19 sin (ψ _m −ψ _s −
ψ ₀ ) is input to the + terminal of the comparator 21 and the − terminal of the comparator 22, the threshold V _H1 is applied to the − terminal of the comparator 21, and the threshold V _L1 (<V _H1 ) is applied to the + terminal of the comparator 22. Is entered.
Therefore, the output signal sin (ψ _m −ψ _s from the mixer 19
-Ψ ₀ ) is larger than the threshold V _H1 , the comparator 21 inputs the high level signal to the D terminal of the counter 23, and the output signal sin (ψ _m −ψ _s −ψ ₀ ) from the mixer 19 is the threshold V _L1.
When it is smaller than this, the comparator 22 inputs a high level signal to the U terminal of the counter 23. In other cases, the comparators 21 and 22 output low level signals, respectively.

The counter 23 is an up / down counter. When a high level signal is input to the D terminal, the counter 23 counts down the clock signal sent from the clock generator 26, and a high level signal is input to the U terminal. When you are
The clock signal sent from the clock generator 26 is counted up. The count value of the counter 23 is the ROM 24
The data stored in the address corresponding to the count value is sent to the D / A converter 25. This data is a data value of the phase shift amount ψ ₀ of the phase shifter 14 corresponding to the count value, and the D / A converter 25 converts the transmitted data value into analog phase shift control signals sinV, cosV.
And output to the phase shifter 14.

Phase shift amount ψ of the phase shifter 14₀Is the counter 23
Becomes larger as the count value decreases and the count value becomes smaller.
Is set to be. Therefore, the counter 23
As the count value decreases, the phase difference (ψ_m−ψ_s−
ψ₀) Also becomes smaller. In FIG. 12, the horizontal axis indicates the phase difference (ψ_m−
ψ_s−ψ₀) And the vertical axis represents the output signal sin of the mixer 19.
(ψ _m−ψ_s−ψ₀) Is taken. This FIG.
In, for example, the output of the mixer 19 was at point 27
Then, the comparator 21 sends the high level signal to the counter 23.
It is output and the counter value becomes smaller. Therefore, the phase shifter
14 Phase shift amount ψ₀Becomes larger and the phase difference (ψ_m−ψ_s−
ψ₀) Becomes smaller. That is, the mixer 1 in FIG.
The output point 27 of 9 moves in the direction of arrow 28. And the threshold
Value V_H1When you reach the level, this movement stops.

On the contrary, the phase shift amount ψ ₀ of the phase shifter 14 is set so as to decrease as the counter 23 counts up and the count value increases. Therefore, as the count value of the counter 23 increases, the phase difference (ψ _m −ψ
_{s −} ψ ₀ ) also becomes large. In FIG. 12, for example, if the output of the mixer 19 is at the point 29, the comparator 22
Outputs a high level signal to the counter 23, and the counter value increases. Therefore, the phase shift amount ψ ₀ of the phase shifter 14 becomes small, and the phase difference (ψ _m −ψ _s −ψ ₀ ) becomes large.
That is, in FIG. 12, the output point 29 of the mixer 19 moves in the direction of the arrow 30. Then, this movement is stopped reaches the threshold V _L1 level.

In this way, the phase difference (ψ_m−ψ_s−ψ
₀) Is the threshold V of FIG._H1And threshold V _L1Area enclosed by and
Is drawn to the value within. Phase difference in this pull-in area
(ψ_m−ψ_s−ψ₀) Is almost 0. That is,
The phase difference between the first received signal and the second received signal (ψ₀= Ψ_m
−ψ_s) Is generated by the phase shifter 14 to generate the first received signal and the second received signal.
This means that the received signal has been corrected to have the same phase.

[0010]

However, the output signal sin (ψ _m −ψ _s −ψ ₀ ) from the mixer 19 has a pull-in region even in the vicinity of the phase difference ± π / 2, as shown in FIG. Therefore, when the phase difference (ψ _m −ψ _s −ψ ₀ ) is near + π / 2 or −π / 2, the comparator 21 and the comparator 22 do not output a high level signal. Therefore, the control unit 20 does not change the phase shift amount ψ ₀ of the phase shifter 14. Therefore, a phase difference of π / 2 occurs between the phase of the first received signal and the phase of the second received signal, resulting in a so-called opposite phase, and there is almost no output from the combiner 13. Will hold. Such an inconvenience occurs accidentally immediately after the power of the receiving device is turned on, or immediately after the state in which there is no transmission signal is changed, and once this state occurs,
The unreceivable state will continue forever.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a space diversity combining circuit in which reverse phase pull-in is prevented.

[0012]

In order to achieve the above-mentioned object, the present invention, as shown in FIG. 1, receives the same transmission signal by at least two antennas 1 and 2, respectively, and receives the first reception signal and Receiving means 3 for outputting as a second received signal and phase shifting means 4 for changing the phase of the second received signal.
, A first receiving signal and a second receiving signal that has been phase-shifted by the phase shifting means 4, a synthesizing means 5 for synthesizing the first received signal, and a second phase shifted by the phase shifting means 4. Phase difference detecting means 6 for detecting the phase difference from the received signal, and based on the phase difference detected by the phase difference detecting means 6, of the phase shift means 4 so that the phase difference converges in the first phase difference area. Based on the phase difference detected by the first phase shift control means 7 for controlling the phase shift amount and the phase difference detection means 6, the phase shift means 4 shifts the phase difference so as to converge to the second phase difference region. Operation control for operating the second phase shift control means 8 for controlling the phase amount and the second phase shift control means 8 at a predetermined timing for a predetermined time, and then operating the first phase shift control means 7. And a means 9 for providing a space diversity combining circuit.

In the above structure, the receiving means 3
However, the same transmission signal is transmitted to at least two antennas 1 and 2.
To receive and output as a first reception signal and a second reception signal. The phase shift means 4 makes the phase of the first reception signal and the phase of the second reception signal coincide with each other,
The phase of the second received signal is changed. The first reception signal and the second reception signal in phase are combined by the combining means.

By the way, in order for the phase shift means 4 to match the phase of the first received signal with the phase of the second received signal,
The operation control means 9 operates the second phase shift control means 8 at a predetermined timing for a predetermined time, and then operates the first phase shift control means 7. The predetermined timing is immediately after the power is turned on or immediately after there is no transmission signal.

The phase difference detection means 6 always detects the phase difference between the first reception signal and the second reception signal phase-shifted by the phase shift means 4. First, the operation of the second phase shift control means 8 causes the phase shift means 4 to converge on the basis of the phase difference detected by the phase difference detection means 6 so as to converge in the second phase difference region.
Control the amount of phase shift. By properly setting the second phase difference region, even if there is an output signal from the mixer 19 in the pull-in region near the phase difference ± π / 2 shown in FIG. 12, it is pulled out from the pull-in region. After that, the first phase shift control means 7 is operated, whereby the phase difference of the phase shift means 4 is converged to the first phase difference region based on the phase difference detected by the phase difference detection means 6. Control the amount of phase shift. The first retardation region corresponds to a region surrounded by the threshold value V _H1 and the threshold value V _L1 shown in FIG. As a result, the output signal from the mixer 19 has the phase difference 0 shown in FIG.
It can be reliably converged to the nearby pull-in area.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. First, the principle configuration of the first embodiment will be described with reference to FIG. The space diversity combining circuit according to the first embodiment includes receiving means 3 that receives the same transmission signal by at least two antennas 1 and 2 and outputs the reception signal as a first reception signal and a second reception signal. Phase shifting means 4 for changing the phase of the second received signal, the first received signal, and the second phase shifted by the phase shifting means 4.
, A phase difference detecting means 6 for detecting a phase difference between the first received signal and the second received signal phase-shifted by the phase-shifting means 4, and a phase difference detection Based on the phase difference detected by the means 6, the first phase shift control means 7 for controlling the amount of phase shift of the phase shift means 4 so that the phase difference converges to the first phase difference region, and the phase difference detection means. Based on the detected phase difference of No. 6, the second phase shift control unit 8 that controls the phase shift amount of the phase shift unit 4 so that the phase difference converges to the second phase difference region, and the second phase shift control unit 8 at a predetermined timing. Of the phase shift control means 8 is operated for a predetermined time, and then the first phase shift control means 7 is operated.

FIG. 2 is a block diagram showing the detailed structure of the first embodiment. Since this structure is basically the same as the structure shown in FIG. 10 which has already been described, the same parts are designated by the same reference numerals and the description thereof will be omitted.

In the first embodiment, the output of the AGC amplifier 15 that amplifies the combined signal is the SW control signal generator 3.
Sent to 1. The SW control signal generation unit 31 detects the signal level after the combination, and detects the time when the state in which there is no transmission signal changes to the state that exists, from the detection result. Then, a SW control signal that is at a high level is generated for a predetermined time (for example, 2 to 3 seconds) from the change point, and the control unit 32
Send to A power-on signal is input to the SW control signal generator 31 when the power is turned on. The SW control signal is generated and sent to the control unit 32 for the predetermined time from the time when the power-on signal is input.

FIG. 3 is a block diagram showing the internal structure of the control unit 32. The configuration of the control unit 32 is similar to that of FIG.
The configuration of FIG. 3 includes the same components as those of FIG. 11 because the configuration shown in FIG. Therefore, the same parts are designated by the same reference numerals and the description thereof will be omitted.

In the control section 32, comparators 41 and 42 and a switch section 43 are newly added. The output signal sin (ψ _m −ψ _s −ψ ₀ ) from the mixer 19 (FIG. 2) is input to the + terminal of the comparator 41 and the − terminal of the comparator 42, and the threshold value V is input to the − terminal of the comparator 41. _The threshold value V _L2 (<V _H2 ) is input to the + terminal of the comparator 42. As shown in FIG. 4, the threshold value V _H2 and the threshold value V _L2 are set to values such that the threshold value V _H1 and the threshold value V _L1 are in the relationship of V _H2 > V _L2 > V _H1 > V _L1. . The switch unit 43 includes two changeover switches 43a and 43b.
3a selects one of the outputs of the comparator 21 and the comparator 41 and sends it to the D terminal of the counter 23, and the changeover switch 43b selects one of the outputs of the comparator 22 and the comparator 42. Send to the U terminal of the counter 23. From the SW control signal generator 31 (FIG. 2) to the switch 43
Only while the control signal is sent and the SW control signal is input, the changeover switches 43a and 43b are located at the positions shown by the broken lines in the figure.

The phase shift means 4 of FIG. 1 is the phase shifter 1 of FIG.
4, the synthesizing means 5 of FIG. 1 corresponds to the synthesizer 13 of FIG. 2, the phase difference detecting means 6 of FIG. 1 corresponds to the mixer 19 and the 90 ° phase shifter 18 of FIG. The first phase shift control means 7 is composed of the comparators 21 and 22, the counter 23 and the ROM of FIG.
24, the D / A converter 25, and the clock generator 26, and the second phase shift control means 8 in FIG. 1 corresponds to the comparator 4 in FIG.
1, 42, counter 23, ROM 24, D / A converter 2
5 and the clock generator 26, and the operation control means 9 of FIG. 1 corresponds to the SW control signal generation unit 31 of FIG. 2 and the switch unit 43 of FIG.

In such a configuration, first, assuming that the power is turned on or the state in which there is no transmission signal is changed to the state in which there is no transmission signal, the SW control signal generation unit 31 to the control unit 32.
The SW control signal is sent to the switch unit 43 of. As a result, the changeover switches 43a and 43b are positioned at the broken line positions in FIG. Therefore, the output of the comparator 41 is the counter 23.
Of the comparator 42, and the output of the comparator 42 is sent to the U terminal of the counter 23. Accordingly, when the output signal sin (ψ _m −ψ _s −ψ ₀ ) from the mixer 19 is larger than the threshold value V _H2 , the comparator 41 inputs the high level signal to the D terminal of the counter 23, and the output from the mixer 19 is output. Signal sin (ψ _{m −} ψ _s
-Ψ ₀₎ is the comparator 42 inputs a high level signal to the U terminal of counter 23 when less than the threshold value V _L2. In other cases, the comparators 41 and 42 output low level signals, respectively.

As a result, as shown in FIG.
(ψ _m −ψ _s −ψ ₀ ) moves in the direction of arrow 44 or arrow 45. As a result, the phase difference (ψ _{m −} ψ _{s −} ψ ₀ )
Is drawn into the value in the region surrounded by the threshold V _H2 and the threshold V _{L2 in} FIG. That is, the phase difference ± π / 2 shown in FIG.
The output signal from the mixer 19 sin (ψ
_{If there is (m −} ψ _{s −} ψ ₀ ), it will be extracted from it.

The predetermined time, which is the high-level duration of the SW control signal, is set longer than the time required to complete the pulling into the area surrounded by the thresholds V _H2 and V _L2 . The maximum time required to complete the pull-in is the time required for the phase shifter 14 to change the phase shift amount ψ ₀ by one cycle.

After the elapse of a predetermined time, the SW control signal does not come from the SW control signal generating section 31 to the switch section 43 of the control section 32, so that the changeover switches 43a and 43b are switched to the positions indicated by the solid lines in FIG. Therefore, the output of the comparator 21 is sent to the D terminal of the counter 23, and the output of the comparator 22 is sent to the U terminal of the counter 23. This gives a phase difference
(ψ _m −ψ _s −ψ ₀ ) will be reliably pulled into the pull-in region near the phase difference 0 surrounded by the threshold V _H1 and the threshold V _{L1 in} FIG.

Next, a second embodiment will be described. Since the configuration of the second embodiment is basically the same as that of the first embodiment, the same parts are designated by the same reference numerals and the description thereof will be omitted. For details, see FIG. 1 and FIG.
The configuration of the first embodiment shown in is also the same in the second embodiment. However, the internal configuration of the control unit 32 is different.

FIG. 5 is a block diagram showing the internal structure of the control unit 32 in the second embodiment. In the second embodiment, the comparators 51 and 52 and the inverters 53 and 54
And an AND circuit 55 are newly provided. Comparator 51
The output signal sin (ψ _m −ψ _s −ψ ₀ ) from the mixer 19 (FIG. 2) is input to the positive (+) terminal of the comparator 52 and the negative (−) terminal of the comparator 52, and the threshold V _H3 is input to the negative (−) terminal of the comparator 51. The threshold value V _L3 (<V _H3 ) is input to the + terminal of the comparator 52. Threshold V _H3
As shown in FIG. 6, the threshold V _L3 and the threshold V _L3 are set to values such that V _H3 > V _H1 > V _L1 > V _L3 , with respect to the threshold V _H1 and the threshold V _L1 . The output of the comparator 51 is connected to the AND circuit 55 via the inverter 53, and the output of the comparator 52 is ANDed via the inverter 54.
Connected to circuit 55. The output of the AND circuit 55 is connected to one input terminal of the changeover switch 43b of the switch unit 43, and the output of the comparator 22 is connected to the other input terminal of the changeover switch 43b. Further, one input terminal of the changeover switch 43a of the switch unit 43 is grounded, and the output of the comparator 21 is connected to the other input terminal of the changeover switch 43a.

In such a configuration, first, assuming that the power is turned on or the state in which there is no transmission signal is changed to the state in which there is no transmission signal, the SW control signal generation section 31 to the control section 32.
The SW control signal is sent to the switch unit 43 of. As a result, the changeover switches 43a and 43b are positioned at the broken line positions in FIG. Therefore, the output of the AND circuit 55 is sent to the U terminal of the counter 23, and no high level signal is input to the D terminal of the counter 23. Thus, when the output signal sin (ψ _m −ψ _s −ψ ₀ ) from the mixer 19 is smaller than the threshold V _H3 and larger than the threshold V _L3 , the comparators 51,
Both 52 output a low level signal, so that the inverters 53 and 54 both output a high level signal. Therefore, the AND circuit 55 outputs the high level signal to the counter 2
Output to U terminal of 3. Otherwise, counter 2
A low level signal is input to the U terminal of No. 3.

As a result, as shown in FIG.
(ψ_m−ψ_s−ψ₀) Moves in the direction of arrows 56 and 57
You. As a result, the phase difference (ψ_m−ψ_s−ψ₀) Is shown in FIG.
Threshold V _H3Area above or threshold V_L3In the value in the following area
Be drawn in. That is, with the phase difference ± π / 2 shown in FIG.
The output signal sin (ψ_m
−ψ_s−ψ₀), If there is
Would.

After the elapse of a predetermined time, the SW control signal does not come from the SW control signal generating section 31 to the switch section 43 of the control section 32, so that the changeover switches 43a and 43b are switched to the positions indicated by the solid lines in FIG. Therefore, the output of the comparator 21 is sent to the D terminal of the counter 23, and the output of the comparator 22 is sent to the U terminal of the counter 23. This gives a phase difference
(ψ _m −ψ _s −ψ ₀ ) is surely drawn into the pull-in region near the phase difference 0 surrounded by the threshold V _H1 and the threshold V _{L1 in} FIG.

Next, a third embodiment will be described. Since the configuration of the third embodiment is basically the same as that of the first embodiment, the same parts are designated by the same reference numerals and the description thereof will be omitted. For details, see FIG. 1 and FIG.
The configuration of the first embodiment shown in is also the same in the third embodiment. However, the internal configuration of the control unit 32 is different.

FIG. 7 is a block diagram showing the internal structure of the control unit 32 in the third embodiment. In the third embodiment, a comparator 61 is newly provided. Comparator 61
Of the output signal from the mixer 19 (FIG. 2) sin (ψ
_m −φ _s −φ ₀ ), and the threshold value V _H4 is input to the + terminal of the comparator 61. As shown in FIG. 8, the threshold V _H4 is such that V _H4 > V _H1 > V with respect to the threshold V _H1 and the threshold V _L1 .
It is set to a value that is related to _L1 . Also, the comparator 6
The output of 1 is connected to one input terminal of the changeover switch 43b of the switch unit 43, and the output of the comparator 22 is connected to the other input terminal of the changeover switch 43b. Further, one input terminal of the changeover switch 43a of the switch unit 43 is grounded, and the output of the comparator 21 is connected to the other input terminal of the changeover switch 43a.

In such a configuration, first, assuming that the power is turned on or the state in which there is no transmission signal is changed to the state in which there is no transmission signal, the SW control signal generation unit 31 to the control unit 32.
The SW control signal is sent to the switch unit 43 of. As a result, the changeover switches 43a and 43b are positioned at the positions indicated by broken lines in FIG. Therefore, the output of the comparator 61 is the counter 23.
No signal of high level is input to the D terminal of the counter 23. Thus, when the output signal sin (ψ _m −ψ _s −ψ ₀ ) from the mixer 19 is smaller than the threshold value V _H4 , the comparator 61 outputs a high level signal, and the high level signal is the U terminal of the counter 23. Is input to. At other times, a low level signal is input to the U terminal of the counter 23.

As a result, as shown in FIG.
(ψ _m −ψ _s −ψ ₀ ) moves in the direction of arrow 62. As a result, the phase difference (ψ _m −ψ _s −ψ ₀ ) is equal to the threshold V of FIG.
_It is drawn to the value in the area above _H4 . That is, even if the output signal _{sin (ψ m -ψ s -ψ 0} ) from the phase difference ± [pi / 2 near the pull-in area in the mixer 19 shown in FIG. 8, will be withdrawn from it.

After the elapse of a predetermined time, the SW control signal does not come from the SW control signal generating section 31 to the switch section 43 of the control section 32, so that the changeover switches 43a and 43b are switched to the positions indicated by the solid lines in FIG. Therefore, the output of the comparator 21 is sent to the D terminal of the counter 23, and the output of the comparator 22 is sent to the U terminal of the counter 23. This gives a phase difference
(ψ _m −ψ _s −ψ ₀ ) will be surely drawn into the pull-in region near the phase difference 0 surrounded by the threshold V _H1 and the threshold V _{L1 in} FIG.

Next, a fourth embodiment will be described. FIG. 9 is a block diagram showing the configuration of the fourth embodiment.
Since the configuration of the fourth embodiment is basically the same as the configuration shown in FIG. 10 which has already been described, the same portions are denoted by the same reference numerals and the description thereof will be omitted.

In the fourth embodiment, a Δψ control signal generator 71 and a Δψ phase shifter 72 are newly provided. In addition,
The internal configuration of the control unit 20 of the fourth embodiment is exactly the same as the internal configuration of the control unit 20 shown in FIG.

The output of the AGC amplifier 15 for amplifying the combined signal is sent to the Δψ control signal generator 71. Δψ
The control signal generator 71 detects the signal level after the combination,
From the detection result, the time point at which there is no transmission signal is changed to a certain state is detected. Then, it becomes a high level for a predetermined time (for example, 2 to 3 seconds) from the change point.
A φ control signal is generated and sent to the Δφ phase shifter 72. Also, Δ
A power-on signal is input to the ψ control signal generator 71 when the power is turned on. The Δψ control signal is generated for the predetermined time from the time when this power-on signal is input, and the Δψ phase shifter 7
Send to 2.

When the Δψ control signal is input, the Δψ phase shifter 72 shifts the output from the 90 ° phase shifter 18 by a predetermined phase shift amount Δψ. When the input of the Δψ control signal disappears, the phase shift is stopped. Therefore, the output signal from the mixer 19 remains sin for a predetermined time from the time when the power is turned on or the time when there is no transmission signal changes to the state where there is no transmission signal.
(ψ _{m −} ψ _{s −} ψ _{0 −} Δψ). Therefore, the original output signal sin (ψ _m −ψ _s −ψ ₀ ) from the mixer 19 is
Even in the pull-in region near the phase difference ± π / 2 shown in FIG. 12, if the phase shift amount Δψ is appropriately set, the output signal can be pulled out from the pull-in region. In the pulled out state, the control unit 20
Is activated, the phase difference (ψ _{m −} ψ _s − ψ ₀ − Δ
ψ) is pulled into the pull-in region near the phase difference 0 surrounded by the threshold V _H1 and the threshold V _{L1 in} FIG.

After a lapse of a predetermined time, the mixer 19 outputs
Force signal is sin (ψ_m−ψ_s−ψ₀), But the phase difference is already
 (ψ_m−ψ_s−ψ₀−Δψ) is the threshold value V in FIG._H1And the threshold
Value V _L1Pulled to the pull-in area near the phase difference 0 surrounded by
Output signal from the mixer 19 sin (ψ_m
−ψ_s−ψ₀) Is the subtraction near the phase difference ± π / 2 shown in FIG.
There is no return to the imprint area. Therefore, the subsequent control
The phase difference (ψ_m−ψ_s−ψ₀) Is
Threshold value V in FIG._H1And threshold V_L1Phase difference near 0 surrounded by and
Will be reliably pulled into the pull-in area.

In the fourth embodiment, the Δψ phase shifter 72 is provided on the processing side of the second received signal, but instead of this, the Δψ phase shifter 72 is used for the first received signal. It may be provided on the processing side.

In any of the above embodiments, 2
Although two received signals received by one antenna are phase-matched, the present invention can be applied to phase matching of three or more received signals received by three or more antennas.

[0043]

As described above, according to the present invention, the second area is set in addition to the first area which is a normal pull-in area, and a plurality of reception signals are set immediately after the power is turned on or the transmission signal is generated. By pulling the phase difference between the signals into the second region,
Pull out from the reverse phase pull-in state. After that, the plurality of received signals are brought into the in-phase state by pulling them into the first area as usual. This surely prevents the reverse phase pull-in.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a block diagram showing a detailed configuration of the first embodiment.

FIG. 3 is a block diagram showing an internal configuration of a control unit according to the first embodiment.

FIG. 4 is a diagram illustrating an operation of a control unit according to the first embodiment.

FIG. 5 is a block diagram showing an internal configuration of a control unit in the second embodiment.

FIG. 6 is a diagram illustrating an operation of a control unit according to the second embodiment.

FIG. 7 is a block diagram showing an internal configuration of a control unit in the third embodiment.

FIG. 8 is a diagram illustrating an operation of a control unit according to the third embodiment.

FIG. 9 is a block diagram showing a configuration of a fourth embodiment.

FIG. 10 is a block diagram showing a configuration of a conventional space diversity combining circuit for performing in-phase combining.

FIG. 11 is a block diagram showing an internal configuration of a conventional control unit.

FIG. 12 is a diagram illustrating an operation of a conventional control unit.

[Explanation of symbols]

 1 Antenna 2 Antenna 3 Receiving Means 4 Phase Shifting Means 5 Combining Means 6 Phase Difference Detecting Means 7 First Phase Shifting Control Means 8 Second Phase Shifting Control Means 9 Operation Control Means

Claims (7)

[Claims] 1. A space diversity combining circuit for performing in-phase combining, comprising: receiving means for receiving the same transmission signals respectively by at least two antennas and outputting them as a first reception signal and a second reception signal; Phase shift means for changing the phase of the received signal, the first received signal, and the second phase shifted by the phase shift means
Combining means for synthesizing the received signal of the second signal, the first received signal and the second phase shifted by the phase shifting means.
Phase difference detecting means for detecting a phase difference from the received signal, and based on the phase difference detected by the phase difference detecting means, shift of the phase shifting means so that the phase difference converges to the first phase difference region. First phase shift control means for controlling the phase amount, and based on the phase difference detected by the phase difference detection means, the phase shift amount of the phase shift means so that the phase difference converges to the second phase difference region. A second phase shift control means for controlling the first phase shift control means, and a second phase shift control means for activating the second phase shift control means at a predetermined timing for a predetermined time, and thereafter operating the first phase shift control means. A space diversity combining circuit having: 2. The first phase difference region is a region centered on a point where the phase difference between the first received signal and the second received signal phase-shifted by the phase shifting means becomes zero. The space diversity combining circuit according to claim 1, wherein 3. The space diversity combining circuit according to claim 2, wherein the second retardation region is a region that does not include the first retardation region therein. 4. The space diversity combining circuit according to claim 1, wherein the predetermined time is set to a value equal to or longer than a time required for the phase shift means to change the phase shift amount by one cycle. 5. A space diversity combining circuit for performing in-phase combining, wherein the receiving means receives the same transmission signal by at least two antennas and outputs the received signals as a first reception signal and a second reception signal, respectively. Phase shifting means for changing the phase of the received signal, the synthesizing means for synthesizing the first received signal and the second received signal phase-shifted by the first phase shifting means, Based on the phase difference detected by the phase difference detecting means, the phase difference detecting means detecting a phase difference between the first received signal and the second received signal phase-shifted by the first phase shifting means, A phase shift control unit that controls the amount of phase shift of the first phase shift unit so that the phase difference converges to a predetermined phase difference region; and the phase of the first received signal or the second received signal, At a given timing for a given time A second phase shift means for changing only a fixed amount, and a space diversity combining circuit. 6. The predetermined phase difference region is centered on a point where the phase difference between the first received signal and the second received signal phase-shifted by the first phase shifting means becomes zero. 6. The space diversity combining circuit according to claim 5, wherein the space diversity combining circuit is a region. 7. The space diversity according to claim 5, wherein the predetermined time is set to a value equal to or longer than a time required for the first phase shift means to change the phase shift amount by one cycle. Synthesis circuit.