JP3254606B2 - Intermediate frequency synthesis type space diversity reception system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a radio transmitting / receiving apparatus used for marine communication, long-distance communication, etc., and more particularly to an intermediate frequency combining type space diversity receiving system in which an input system of a receiving apparatus is duplicated.

[0002]

2. Description of the Related Art In general, in a space diversity (hereinafter, referred to as SD) receiving method for synthesizing an intermediate frequency (hereinafter, referred to as IF), high-frequency (hereinafter, referred to as RF) signals received by antennas at different positions are respectively intermediately transmitted. Frequency (hereinafter, IF
The first and second frequency converters for converting the signals into a signal and an intermediate frequency synthesizer for synthesizing the outputs of these frequency converters, performing SD control, and leading the resultant signal to a subsequent demodulation circuit are provided at an input stage of the SD receiver. To mitigate the effect of the fading phenomenon, thereby improving the reliability of the line. Hereinafter, the first input system will be referred to as a main system, and the second input system will be referred to as a sub system.

The frequency converters of the main system and the sub system usually each have a local oscillation circuit (hereinafter, abbreviated as a local oscillator). However, in order to properly perform the subsequent demodulation, both the local oscillators are used. Must be kept in sync. This is for the following reason.

If the self-propelled local oscillators are used arbitrarily, the IF main signal obtained in the main system and the IF main signal obtained in the sub system have different frequencies. Is as shown in the following Expression 1.

[0005]

(Equation 1)

Therefore, an amplitude-modulated wave with phase inversion is superimposed due to the frequency of the difference between the two, and normal demodulation cannot be performed by a subsequent demodulator.

In this case, as the simplest method of establishing synchronization between the local oscillators, there is a method in which the local oscillator is used as one common circuit and the output of the common oscillator is branched and supplied. However, in this method, it is necessary to exchange the output between the main system local oscillator and the sub system local oscillator, which is difficult to be realized when each is separated in a separate configuration. In addition, the fact that the input system is not completely duplexed up to the IF synthesis stage is also an insufficient element for an SD receiver.

Therefore, in many cases, the mutual synchronization between the main system station and the sub system station of the SD receiver is configured by using a phase comparison lock loop (PLL). However, if the mutual synchronization between the local stations is impaired, a fatal line failure will be caused due to the above-mentioned circumstances, so that some measure for avoiding the failure is required.

FIG. 4 is a block diagram of an input system of an IF in-phase combining SD receiver conventionally used as a measure for avoiding the above-mentioned obstacle. 4, 1 is a main system antenna, 40 is a main system reception front end, 50 is a main system local oscillator, 2 is a sub system antenna, 60 is a sub system reception front end, 7
0 is a sub-system local oscillator, and 80 is an IF in-phase synthesis circuit.

Each of the reception front ends 40 and 60 is a circuit that converts the frequency of an RF band signal received from each of the antennas 1 and 2 into an IF band signal. Also, 50, 70
Is a circuit for generating an IF signal having a frequency corresponding to the shift amount of the RF signal. In the example of FIG. 4, the X'tal standard signal sources 51 and 71 are configured to be able to achieve phase synchronization. In this configuration example, each of the local oscillators 50 and 70 has phase comparators 52 and 72, RF VCOs 53 and 73, and a frequency divider 5
4 and 74, each of which is independently operated, and a phase synchronization means is added to the sub system local oscillator 70.

That is, X'tal from the main system local oscillator 50
A synchronizing phase comparator 75 having the input of the standard signal source 51 and its own X'tal standard signal source 71 is provided to form a PLL circuit that follows and synchronizes with the phase of the main system local oscillator 50.

For monitoring the mutual synchronization between the local oscillators 50 and 70, the SD control monitoring circuit 8 of the IF in-phase synthesizing circuit 80
It is common to delegate the function to one. That is, in the IF in-phase synthesis type SD receiver, the output phases of the main and sub-system reception front ends 40 and 60 are compared with the phase comparator 81.
And the built-in EPS (infinite phase shifter) circuit 82 is controlled so that the input of the synthesizer is always in phase. When the synchronization between the local oscillators is abnormal, the SD control system itself performs the frequency difference between the local oscillators. In order to follow the direction of absorbing
The synchronization abnormality is detected by monitoring with the control monitoring circuit 83.

Further, as a function of avoiding a failure, in the example of FIG. 4, when the SD control monitoring circuit 83 detects a synchronization abnormality,
This is realized by turning off the IF signal switch 84 to cut off the sub-side input of the output combiner 85 at the next stage. In other words, if a synchronization error occurs and the above-described amplitude-modulated wave with phase inversion is transmitted, the signal on the sub side is cut off, and only the signal on the main side is transmitted from the output combiner 85 to hold the line. Let it.

[0014]

However, in the configuration example shown in FIG. 4, since the synchronization abnormality between local oscillators is detected by monitoring the behavior of the SD control system, the SD is always kept in the abnormal synchronization state. It means that the control system is confused. Therefore,
It is necessary to recognize the behavior in the normal operation state following the fading phenomenon and the stray at the time of abnormal synchronization separately, but in fact, it is very difficult to distinguish this in the fading phenomenon that fluctuates at high speed .

In the example shown in FIG. 4, when the mutual synchronization is restored, the IF signal switch 84 is turned on to immediately start the synthesis.
Since the signals are in phase, an amplitude shock occurs at the same time when the IF signal switch 84 is turned on. As a result, there is a problem that the line is unstable even though it is momentary, and the line quality is degraded.

The present invention has been made to solve these problems. It is an object of the present invention to provide a circuit for quickly detecting a mutual synchronization abnormality and for stabilizing and rationalizing an SD control system. An object of the present invention is to provide an IF-combined type SD receiver provided in a stage.

[0017]

In order to achieve the above object, it is essential to make the SD control system insensitive to mutual synchronization abnormality. Therefore, in the present invention, the mutual synchronization abnormality detection function and the SD synthesis stop / recovery function are arranged at the preceding stage of the SD control system.

More specifically, first and second frequency converters for converting RF signals received by antennas at different positions into IF signals, respectively, and synthesizing the outputs of these frequency converters to S
An IF synthesis circuit that performs D control and leads to a subsequent demodulation circuit is provided at the input stage, and one of the frequency conversion units is:
IF having phase synchronization means for following and synchronizing the phase of its own standard signal source with the phase of the standard signal source of the other frequency converter
In the combined SD reception method, a mutual synchronization monitoring circuit for detecting the occurrence and recovery of an abnormality of the phase synchronization means in one of the first and second frequency converters, And an amplitude control circuit that suppresses the amplitude of the frequency-converted IF signal itself when it is detected and cancels the suppression when recovery is detected. This was done before the circuit.

It should be noted that the amplitude control circuit immediately suppresses the amplitude of its own IF signal when an abnormality is detected, and gradually releases the amplitude suppression with a predetermined time constant at the time of recovery. As a result, even when rising from the worst anti-phase correlation at the time of recovery detection, the state shifts to the synthesis state at the steady amplitude while prompting the SD control system to follow.

[0020]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an input system according to an embodiment of the present invention, showing an example of an IF in-phase synthesis type SD device.
Since the present invention is an improvement of this type of conventional SD device, the same parts as those of the prior art are denoted by the same reference numerals, and the description thereof will be omitted. Only different parts will be described.

In FIG. 1, reference numeral 60 'denotes a sub-system reception front end, 70' denotes a sub-system local oscillator, and 30 denotes an IF in-phase synthesizer. These main and sub system reception front ends 4
0, 60 ', main and sub system receiving stations 50, 7
Basic operations up to the 0 'and IF in-phase synthesis circuit 30 are the same as those of the conventional configuration shown in FIG.

This embodiment is characterized in that a sub-system local oscillator 70 'having a mutual synchronization monitoring circuit 10 therein and a sub-system reception front end 6 which is obtained by adding an amplitude control circuit 20 at the last stage thereof.
0 'and the IF in-phase synthesizing circuit 30 in which the configuration of the SD control system is simplified as compared with the conventional one.

FIG. 2 is a specific configuration diagram of the mutual synchronization monitoring circuit 10. When the PLL is closed so that mutual synchronization is established, the control impedance of the X'tal standard signal source 71 decreases. On the other hand, when the PLL is open due to loss of mutual synchronization, the control impedance of the X'tal standard signal source 71 increases. In the present embodiment, the presence or absence of a mutual synchronization abnormality is monitored at a stage preceding the IF in-phase synthesizing circuit 30 by utilizing the nature of the PLL.

That is, resistors R1 and R2 having sufficiently high values are connected to each other in FIG.
, And a signal corresponding to the level of the control impedance is input to the comparator 11 to obtain one of the predetermined binary signals, thereby causing an abnormality in the mutual synchronization without affecting the operation of the PLL. And monitoring its recovery.

In the connection configuration of FIG. 2, when the loop gain of the PLL is kept low, the detection output when the synchronization is lost may become unstable, resulting in erroneous detection. In such a case, instead of the connection configuration as shown in FIG. 2, a configuration may be adopted in which the input amplitude of the mutual synchronization signal from the main system local oscillator 50 is monitored.

FIG. 3 is a specific configuration diagram of an amplitude control circuit 20 of a continuously variable IF signal type. A pin diode 21 is connected to the illustrated polarity, and a Lag Filter (integrating circuit) 22 and The circuit configuration is such that current flows gradually through the buffer amplifier 23.

In such a configuration, the pin diode 2
When a current is supplied to the IF, the suppression of the amplitude of the IF signal is released slowly with a predetermined time constant with respect to the rise of the synchronization detection signal. Further, when the synchronization detection signal output from the mutual synchronization monitoring circuit 10 falls, that is, when the local oscillators lose synchronization, the amplitude suppression must be completed immediately. Therefore, at this time, as shown in FIG.
The current is immediately cut off without the function of the ag Filter 22.

The operation of this embodiment will be described below with reference to these figures.

First, start from a situation in which mutual synchronization between local stations is established. At this point, the mutual synchronization monitoring circuit 10
Determines that synchronization has been established, and sends an instruction to the amplitude control circuit 20 in a direction in which amplitude is not suppressed. Therefore, the output of the sub system reception front end 60 'is supplied to the IF in-phase synthesis circuit 30 at the same level as the output of the main system reception front end 40. This is a steady operation state of the SD device of the present embodiment. For example, even in a situation where fading is added to each of the main system / sub system input signals, the EPS is controlled so that the inputs of the output combiner 85 are in phase. The circuit 82 is controlled. If this is the minimum amplitude deviation combining type SD receiving method, the EPS circuit 82 is controlled in a direction in which the combined signal spectrum becomes flat.

Next, a situation where mutual synchronization is lost will be described. For example, if the mutual synchronization signal from the main station 50 is interrupted, or if synchronization cannot be ensured due to an abnormality in the PLL, the mutual synchronization monitoring circuit 10 detects the state, and the amplitude control circuit 20 And sends an instruction in the direction to suppress the amplitude.

At this time, if the difference between the free-running frequencies of the sub system local oscillator 70 'and the main system local oscillator 50 is at most several kHz, the first reverse phase synthesis state arrives from the moment when the synchronization is lost. Up to a few hundred μs. Therefore, several μs
If the amplitude control circuit 20 is controlled to the amplitude suppression state within
Before the effect of the local synchronization error is transmitted, the operation switches to single operation of the main system only, and the line is kept stable.

On the other hand, in the SD control system of the IF in-phase synthesizing circuit 30, since there is no input of the sub system,
The output of the phase comparator 81 that detects the relative phase between the sub-system signals becomes zero, and the entire control system stops. In the case of the minimum amplitude deviation synthesizing SD device, the perturbation method is used for the SD control.
Since no change is obtained in the combined signal spectrum with respect to the perturbation, the control system also stops.

Further, a case where the mutual synchronization between the local oscillators is restored will be described. In this case, the mutual synchronization monitoring circuit 10 recognizes the restoration of the synchronization, and the amplitude control circuit 20 gradually releases the amplitude suppression.

The reason for the gradual release here is that, as described above, the phases of the main system / sub system signals at the moment of the recovery are relatively uncertain, and there is a possibility that the signals may rise in opposite phases. Because.

That is, in the case of rising in the opposite phase,
Once the combined output drops significantly, the combined output amplitude recovers as the SD control follows and the line becomes stable. At this time, if the SD control speed is sufficiently fast, it is considered that no problem occurs.
There is an upper limit for each method. In particular, in the case of the minimum amplitude deviation synthesis type SD using the perturbation method for the SD control, it is almost impossible to expect high speed. Therefore, it rises from the opposite phase and S
It takes a very long time for the line to stabilize after waiting for the control of D.

It should be noted that the speed of gradually releasing is determined by S
What is necessary is just to determine by the operation speed of a D control system. For example,
Assuming that the control speed of the EPS circuit 82 is 3000 [゜ / sec], the degree that the amplitude suppression is released to half the amplitude in 0.03 [sec], which starts from the reverse phase and escapes from the reverse phase, is as follows. Appropriate.

Finally, at the stage when all the amplitude cancellations have been completed, the SD receiver returns to the initial steady operation state. During this time, the line is hardly affected by the mutual synchronization abnormality.

In this embodiment, the configuration in which the phase synchronization means, the mutual synchronization monitoring circuit 10, and the amplitude control circuit 20 are added to the input stage of the sub system has been described. Since it may be provided on either side, it may be configured to be added to the input stage of the main system.

[0040]

As described above, according to the present invention, the amplitude control of the IF signal based on the detection of the synchronization abnormality between the local oscillators and the recovery thereof is independently performed in the preceding stage of the SD control system. The behavior of the system is only a response due to the actual fading from the atmosphere, which has the effect of stabilizing the operation. This eliminates the danger of malfunction and the like, and improves the reliability of the SD receiver.

Further, the amplitude release of the IF signal performed at the time of recovery detection is gradually performed with a predetermined time constant, so that the amplitude shock that occurs when the IF signal switch is turned on is eliminated, and the line quality is improved. There is. In addition, even if the input system configuration is changed from duplex to single or the work is again performed to make the duplex configuration, there is no direct effect on the line, so that the workability of maintenance management is improved. is there.

Further, since the amplitude control accompanying the detection / recovery of the synchronization error is all performed in the preceding stage of the SD control system, there is also an effect that the configuration of the IF synthesis circuit is simplified as compared with the conventional one.

[Brief description of the drawings]

FIG. 1 is an input system configuration diagram of an IF in-phase synthesis type SD device according to an embodiment of the present invention.

FIG. 2 is a specific configuration diagram of a mutual synchronization monitoring circuit used in the present embodiment.

FIG. 3 is a specific configuration diagram of an IF signal continuous variable amplitude control circuit used in the present embodiment.

FIG. 4 is an input system configuration diagram of a conventional IF in-phase synthesis type SD device.

[Explanation of symbols]

 1, 2, Antenna 10, Mutual synchronization monitoring circuit 20, Amplitude control circuit 30, 80, IF in-phase synthesizing circuit 40, Main system reception front end 50, Main system local oscillator 60, 60 'Sub system reception front end 70, 70 '… Sub-system local oscillator

────────────────────────────────────────────────── (5) References JP-A-62-219836 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04B ⁷ /02-7/12 H04L 1 / 02-1/06

Claims (2)

(57) [Claims] 1. A first and a second frequency converter for converting high-frequency signals received by antennas at different positions into intermediate frequency signals, respectively, and the outputs of these frequency converters are combined to perform space diversity control, and the subsequent stage is performed. And an intermediate frequency synthesizing circuit for leading the demodulation circuit to the demodulation circuit, and one of the frequency converters synchronizes the phase of its own standard signal source with the phase of the standard signal source of the other frequency converter. In the intermediate frequency synthesis type space diversity receiving system having a phase synchronization unit, in any one of the first and second frequency conversion units, a mutual synchronization monitoring circuit that detects the occurrence of an abnormality in the phase synchronization unit and its recovery, When the occurrence of abnormality is detected by the mutual synchronization monitoring circuit, the amplitude of the frequency-converted own intermediate frequency signal is suppressed, and when recovery is detected, the suppression is released. That the amplitude control circuit is provided, intermediate-frequency synthesis type space diversity receiving system which is characterized in that the amplitude control by the abnormality or the recovery of the phase synchronization at the front stage of the intermediate frequency synthesis circuit. 2. The amplitude control circuit according to claim 1, wherein the amplitude control circuit immediately suppresses the amplitude of its own intermediate frequency signal when an abnormality is detected, and gradually releases the amplitude suppression with a predetermined time constant at the time of recovery. 2. The intermediate frequency combining type space diversity receiving system according to claim 1.