JP2007103991A - Method and apparatus of controlling phase of diversity reception - Google Patents

Method and apparatus of controlling phase of diversity reception Download PDF

Info

Publication number
JP2007103991A
JP2007103991A JP2005287258A JP2005287258A JP2007103991A JP 2007103991 A JP2007103991 A JP 2007103991A JP 2005287258 A JP2005287258 A JP 2005287258A JP 2005287258 A JP2005287258 A JP 2005287258A JP 2007103991 A JP2007103991 A JP 2007103991A
Authority
JP
Japan
Prior art keywords
phase
control
phase shifter
received
diversity
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2005287258A
Other languages
Japanese (ja)
Inventor
Keita Nakano
景太 中野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Kokusai Electric Inc
Original Assignee
Hitachi Kokusai Electric Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Kokusai Electric Inc filed Critical Hitachi Kokusai Electric Inc
Priority to JP2005287258A priority Critical patent/JP2007103991A/en
Publication of JP2007103991A publication Critical patent/JP2007103991A/en
Pending legal-status Critical Current

Links

Images

Landscapes

  • Radio Transmission System (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the influence, on a poststage demodulator, of the phase fluctuation of a composite signal in a diversity receiver of equal gain composition or maximum ratio composition when a reception signal level is reduced. <P>SOLUTION: In a diversity reception system in which at least two antennas are arranged, when the reception level is reduced even in one of a plurality of received high-frequency signals, the control of the phase shifter of a converter for downconverting the plurality of received high-frequency signals is stopped. When the control is started again, the continuity of a phase is maintained, the amount of change in the phase is suppressed, and then the plurality of received high-frequency signals are synthesized. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、無線伝送装置に適用される、等利得合成または最大比利得合成のダイバーシティ受信器や、アレイアンテナ等の無線受信部分の位相制御に関わるものである。   The present invention relates to phase control of a radio receiver such as an equal gain combining or maximum ratio gain combining diversity receiver and an array antenna applied to a radio transmission apparatus.

図7に従来の等利得合成ダイバーシティ受信器のブロック図を示す。受信信号#1と受信信号#2から合成部101において双方の位相差情報が検出される。位相差情報はDC電圧であり、同相に近ければ近いほど高い値をとる。この位相差情報を基に移相器制御部102において、受信信号#1と受信信号#2の合成信号レベルが高くなるような移相器制御電圧が移相器103に出力され、ミキサ104で受信信号#2の位相を変えるという構成である。受信信号#1と受信信号#2を同相にする制御を無限に繰り返し、合成出力レベルを常に最大とするものである。   FIG. 7 is a block diagram of a conventional equal gain combining diversity receiver. Both phase difference information is detected by the combining unit 101 from the received signal # 1 and the received signal # 2. The phase difference information is a DC voltage, and takes a higher value as it is closer to the in-phase. Based on this phase difference information, the phase shifter control unit 102 outputs a phase shifter control voltage that increases the combined signal level of the received signal # 1 and the received signal # 2 to the phase shifter 103. In this configuration, the phase of the received signal # 2 is changed. The control to make the received signal # 1 and the received signal # 2 in phase is repeated infinitely, and the combined output level is always maximized.

図8に従来の合成部101のブロック図を示す。ミキサ201において、IF帯にダウンコンバートされた受信信号#3と受信信号#4から合成出力と位相差電圧を検出する。
図7における移相器制御部103はマイコンで構成される。図3にマイコン制御の各条件における概要図を示す。図3におけるcはマイコンの制御値、PD(c)は位相差電圧を表す。図3(A)は制御値を+1するとPD(c)が大きくなる(受信信号#3と受信信号#4が同相に近づく)条件、図3(B)は制御値を+1してもPD(c)が変わらない(受信信号#3と受信信号#4がほぼ同相である)条件、図3(C)は制御値を+1するとPD(c)が小さくなる(受信信号#3と受信信号#4が同相から遠ざかる)条件である。マイコンは条件(A)のとき、図における(1)から(2)となるように制御方向を維持する。条件(B)のときは出力する移相器制御電圧を一定とし、条件(C)のときは図における(1)から(2)となるように制御方向を逆にするような動作を行う。
特開平6−303171号公報
FIG. 8 shows a block diagram of the conventional synthesis unit 101. The mixer 201 detects the combined output and the phase difference voltage from the received signal # 3 and the received signal # 4 down-converted to the IF band.
The phase shifter control unit 103 in FIG. 7 is configured by a microcomputer. FIG. 3 shows a schematic diagram for each condition of microcomputer control. In FIG. 3, c represents the control value of the microcomputer, and PD (c) represents the phase difference voltage. 3A shows a condition in which PD (c) increases when the control value is incremented by 1 (received signal # 3 and received signal # 4 approach the same phase). FIG. 3B shows PD (c) even if the control value is incremented by +1. c) does not change (received signal # 3 and received signal # 4 are substantially in phase). FIG. 3C shows that PD (c) decreases when the control value is increased by 1 (received signal # 3 and received signal #). 4 is a condition for moving away from the same phase). In the condition (A), the microcomputer maintains the control direction so as to change from (1) to (2) in the figure. When the condition (B) is satisfied, the output phase shifter control voltage is fixed, and when the condition (C) is satisfied, the control direction is reversed so as to change from (1) to (2) in the figure.
JP-A-6-303171

等利得合成ダイバーシティ受信器に入力される移相器制御を受けていない方の受信信号(図7における受信信号#1)が受からなくなったとき、図8におけるミキサ201から出力されるDC電圧には大きな雑音が加わる。このとき図7の移相器制御部(マイコン)102には雑音の乗った位相差電圧が入力されるため常に不安定な動作をし、その結果等利得合成ダイバーシティ受信器の合成信号は位相変動の激しいものとなり、後段の復調器等に影響を与える可能性がある。最大比利得合成は、各アンテナ信号レベルに比例した重み付けを受信信号につけるため、低レベル受信信号は合成信号への寄与率は少ない。しかし、低レベル受信信号の急激な変動は合成信号の雑音となり、後段の復調器等に影響を与える可能性がある。   When the received signal (received signal # 1 in FIG. 7) that is not subjected to the phase shifter control input to the equal gain combining diversity receiver is not received, the DC voltage output from the mixer 201 in FIG. Adds a lot of noise. At this time, the phase shifter control unit (microcomputer) 102 shown in FIG. 7 is always operated in an unstable manner because the phase difference voltage with noise is input, and as a result, the combined signal of the equal gain combining diversity receiver has a phase fluctuation. May affect the demodulator at the later stage. In the maximum ratio gain combining, the received signal is weighted in proportion to each antenna signal level. Therefore, the low-level received signal has a small contribution ratio to the combined signal. However, sudden fluctuations in the low-level received signal become noise of the combined signal, which may affect the demodulator and the like at the subsequent stage.

本発明は、上記の受信信号レベル低下時のダイバーシティ受信器の等利得合成または最大比利得合成の合成信号の位相変動が、後段の復調器等への影響を低減することを目的とする。   It is an object of the present invention to reduce the influence on the demodulator and the like of the subsequent stage due to the phase fluctuation of the combined signal of equal diversity combining or maximum ratio gain combining of the diversity receiver when the received signal level is lowered.

本発明は上記の目的を達成するため、少なくとも2つ以上のアンテナが配置された、ダイバーシティ受信装置において、受信した複数の信号の内一つでも受信レベルが低下した場合、上記受信した複数の信号を位相する移相器の制御を停止させ、再び制御を開始するときには位相の連続性を保ち、さらに位相の変化量を抑えてから、受信した複数の信号を合成する。   In order to achieve the above object, the present invention provides a diversity receiving apparatus in which at least two or more antennas are arranged, and when the reception level is reduced even in one of the received signals, the received signals When the control of the phase shifter that stops the phase is stopped and the control is started again, the continuity of the phase is maintained and the amount of change in the phase is suppressed, and then the received signals are synthesized.

つまり、等利得合成または最大比利得合成のダイバーシティ受信方式において、ダイバーシティ受信器のどちらの受信信号が受からない状況においても、合成信号の位相を乱さない。   That is, in the diversity reception method of equal gain combining or maximum ratio gain combining, the phase of the combined signal is not disturbed even in a situation where neither of the diversity receivers receives the received signal.

以上説明したように本発明のダイバーシティ受信器を用いることにより、複数ある受信信号の内、どの受信信号のレベルが低下しても安定した位相を持つ等利得合成または最大比利得合成の合成信号を出力することが可能になる。   As described above, by using the diversity receiver of the present invention, it is possible to generate a composite signal of equal gain synthesis or maximum ratio gain synthesis that has a stable phase regardless of the level of any received signal among a plurality of received signals. It becomes possible to output.

また移相器制御の停止から復帰するときも、極端な変化の移相器制御は合成信号の位相を短時間に大きく変化させることになり、後段の復調器は位相変化に追従することができず、復調特性劣化に繋がる。しかし、移相器制御の停止復帰後にも移相器制御電圧は常に連続性を保ちつつ、時間当りの位相の変化量をある程度抑える。これにより、合成信号の位相が短時間に極端に変化することを回避することが可能であり、後段の復調器は特性を劣化させることなく復調可能となる。   In addition, when returning from stoppage of phase shifter control, phase shifter control with extreme changes will greatly change the phase of the composite signal in a short time, and the demodulator at the subsequent stage can follow the phase change. Therefore, the demodulation characteristic is deteriorated. However, even after the phase shifter control is stopped and returned, the phase shifter control voltage always maintains continuity and suppresses the amount of phase change per time to some extent. Thereby, it is possible to avoid the phase of the combined signal from changing extremely in a short time, and the demodulator at the subsequent stage can demodulate without deteriorating the characteristics.

図1に本発明の1実施例の等利得合成ダイバーシティ受信器のブロック図を示す。図7の従来の等利得合成ダイバーシティ受信器のブロック図とは、合成部と移相器制御部とが異なる。そこで、図2に本発明の1実施例の等利得合成ダイバーシティ受信器の合成部と移相器制御部のブロック図を示す。図2の合成部404において、従来方式で出力していた位相差電圧に加え、AGC401とAGC402において受信信号#3と受信信号#4に対するAGC電圧を出力し、その各AGC電圧を調整して電力を表す受信電力#1と受信電力#2を移相器制御部403に出力する。移相器制御部403において、受信電力#1と受信電力#2のどちらかの値が所定レベル以下のとき、位相制御を停止するものである。   FIG. 1 shows a block diagram of an equal gain combining diversity receiver according to one embodiment of the present invention. The combining unit and the phase shifter control unit are different from the block diagram of the conventional equal gain combining diversity receiver of FIG. FIG. 2 shows a block diagram of the combining unit and phase shifter control unit of the equal gain combining diversity receiver according to one embodiment of the present invention. 2, in addition to the phase difference voltage output in the conventional method, AGC 401 and AGC 402 output AGC voltages for reception signal # 3 and reception signal # 4, and adjust the respective AGC voltages to adjust the power. The received power # 1 and the received power # 2 representing are output to the phase shifter control unit 403. The phase shifter control unit 403 stops phase control when the value of either received power # 1 or received power # 2 is equal to or lower than a predetermined level.

本発明の1実施例の制御を表す概略図を図4に示す。図4は時間tの経過に対して移相器制御を行っているものを表している。受信電力が所定レベル、例えば通常電力の1/4以下に落ちたとき、移相器制御を停止する。   A schematic diagram illustrating the control of one embodiment of the present invention is shown in FIG. FIG. 4 shows a case where phase shifter control is performed over time t. When the received power falls to a predetermined level, for example, 1/4 or less of the normal power, the phase shifter control is stopped.

また移相器制御の停止から復帰するとき、図4に示すように極端な変化の移相器制御は合成信号の位相を短時間に大きく変化させることになり、後段の復調器は位相変化に追従することができず、復調特性劣化に繋がる。これを回避するために、本発明の別の実施例として、移相器制御の停止復帰後にも移相器制御電圧は常に連続性を保ちつつ、時間当りの位相の変化量をある程度抑える。この本発明の別の実施例の制御例の模式図を図5に、移相器制御部403の制御ブロック図を図6に示す。これにより、合成信号の位相が短時間に極端に変化することを回避することが可能であり、後段の復調器は特性を劣化させることなく復調可能となる。   In addition, when returning from the stoppage of the phase shifter control, as shown in FIG. 4, the phase shifter control of extreme change greatly changes the phase of the synthesized signal in a short time, and the demodulator at the subsequent stage changes the phase. Unable to follow, leading to degradation of demodulation characteristics. In order to avoid this, as another embodiment of the present invention, the amount of phase change per time is suppressed to some extent while the phase shifter control voltage always maintains continuity even after the phase shifter control is stopped and returned. A schematic diagram of a control example of another embodiment of the present invention is shown in FIG. 5, and a control block diagram of the phase shifter control unit 403 is shown in FIG. Thereby, it is possible to avoid the phase of the combined signal from changing extremely in a short time, and the demodulator at the subsequent stage can demodulate without deteriorating the characteristics.

本発明の別の実施例の移相器制御部の制御例の図5は、制御停止期間に位相差が変化し(位相差電圧PD(c)の低下)、制御再開時に同相となっていない状態において、制御停止前の位相状態からスタートし、その後、位相差が最大となるまでの間は位相回転速度を低くする制御を表している。   FIG. 5 of the control example of the phase shifter control unit of another embodiment of the present invention shows that the phase difference changes during the control stop period (decrease in the phase difference voltage PD (c)) and is not in phase when the control is resumed. In the state, the control starts from the phase state before stopping the control and then decreases the phase rotation speed until the phase difference becomes maximum.

本発明の別の実施例の移相器制御部の制御ブロック図6において、(A)は受信レベルが低下した場合の移相器制御部403の制御ブロック図を示している。受信レベル低下検出部701, 702において受信電力#1、#2を監視し、レベル低下時に移相器制御電圧生成部703に制御停止命令、位相保持命令を送る。図6において、(B)は受信レベルが閾値以上に戻ったときの移相器制御部403の制御ブロック図を示している。このとき、移相器制御電圧生成部703は制御を再開し、移相器にて位相回転させるための電圧を生成するが、その回転速度は後段の復調器に影響が出ないように十分低速なものとなるように制御する。   FIG. 6A is a control block diagram of the phase shifter control unit 403 when the reception level is lowered. FIG. 6A is a control block diagram of the phase shifter control unit 403 according to another embodiment of the present invention. Received power level drop detectors 701 and 702 monitor received power # 1 and # 2, and send a control stop command and a phase hold command to phase shifter control voltage generator 703 when the level drops. FIG. 6B is a control block diagram of the phase shifter control unit 403 when the reception level returns to the threshold value or more. At this time, the phase shifter control voltage generation unit 703 restarts the control and generates a voltage for phase rotation by the phase shifter, but the rotation speed is sufficiently low so as not to affect the subsequent demodulator. Control it to become something.

ところで、以上の実施形態では、等利得合成ダイバーシティ受信器についてだけ説明したが、本発明では、等利得合成ダイバーシティ受信器に限定されるものではなく、最大比利得合成ダイバーシティ受信器であっても良い。   By the way, in the above embodiments, only the equal gain combining diversity receiver has been described. However, the present invention is not limited to the equal gain combining diversity receiver, and may be a maximum specific gain combining diversity receiver. .

また、以上の実施形態では、局部発振器(LOC)106とミキサ201とを用いた、受信した複数の高周波信号を低周波信号にダウンコンバートしてから合成する方式について説明したが、本発明では、受信した高周波信号を直接合成する方式であっても良い。
In the above embodiment, a method of using a local oscillator (LOC) 106 and a mixer 201 to synthesize a plurality of received high-frequency signals after down-converting them into low-frequency signals has been described. A method of directly synthesizing received high-frequency signals may be used.

本発明の1実施例の等利得合成ダイバーシティ受信器のブロック図1 is a block diagram of an equal gain combining diversity receiver according to an embodiment of the present invention. 本発明の1実施例の合成部と移相器制御部のブロック図The block diagram of the synthetic | combination part and phase shifter control part of one Example of this invention 移相器制御部の制御例の模式図Schematic diagram of control example of phase shifter controller 本発明の1実施例の移相器制御部の制御例の模式図The schematic diagram of the control example of the phase shifter control part of one Example of this invention 本発明の別の実施例の移相器制御部の制御例の模式図The schematic diagram of the control example of the phase shifter control part of another Example of this invention 本発明の別の実施例の制御例の移相器制御部の制御ブロック図The control block diagram of the phase shifter control part of the control example of another Example of this invention 従来の等利得合成ダイバーシティ受信器のブロック図Block diagram of conventional equal gain combining diversity receiver 従来の合成部のブロック図Block diagram of conventional synthesis unit

符号の説明Explanation of symbols

101, 404:合成部、102,403:移相器制御部、103:移相器
104,105,201:ミキサ、106:局部発振器(LOC)、
401,402:AGC、701, 702:受信レベル低下検出部、
703:移相器制御電圧生成部

101, 404: synthesis unit, 102, 403: phase shifter control unit, 103: phase shifter 104, 105, 201: mixer, 106: local oscillator (LOC),
401, 402: AGC, 701, 702: reception level decrease detection unit,
703: Phase shifter control voltage generator

Claims (2)

少なくとも2つ以上のアンテナが配置された、ダイバーシティ受信装置において、
受信した複数の信号の内一つでも受信レベルが低下した場合、
上記受信した複数の信号を位相する移相器の制御を停止させ、再び制御を開始するときには位相の連続性を保ち、さらに位相の変化量を抑えてから、受信した複数の信号を合成することを特徴とする位相制御方法。
In a diversity receiver in which at least two or more antennas are arranged,
If the reception level drops even in one of the received signals,
Stop the control of the phase shifter that phase the received multiple signals, and maintain the continuity of the phase when starting the control again, and further suppress the amount of phase change before synthesizing the received multiple signals A phase control method characterized by the above.
少なくとも2つ以上のアンテナが配置された、ダイバーシティ受信装置において、受信した複数の信号の内一つでも受信レベルが低下した場合、上記受信した複数の信号を位相する移相器の制御を停止させ、再び制御を開始するときには位相の連続性を保ち、さらに位相の変化量を抑えてから、受信した複数の信号を合成する機能と、
ダイバーシティ等利得合成機能またはダイバーシティ最大比利得合成機能とを有する事を特徴とするダイバーシティ受信装置。
In a diversity receiving apparatus in which at least two or more antennas are arranged, if even one of a plurality of received signals has a reduced reception level, control of the phase shifter that phases the plurality of received signals is stopped. When starting control again, the function of synthesizing a plurality of received signals after maintaining the continuity of the phase and further suppressing the amount of phase change,
A diversity receiver having a gain combining function such as diversity or a diversity maximum ratio gain combining function.
JP2005287258A 2005-09-30 2005-09-30 Method and apparatus of controlling phase of diversity reception Pending JP2007103991A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2005287258A JP2007103991A (en) 2005-09-30 2005-09-30 Method and apparatus of controlling phase of diversity reception

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005287258A JP2007103991A (en) 2005-09-30 2005-09-30 Method and apparatus of controlling phase of diversity reception

Publications (1)

Publication Number Publication Date
JP2007103991A true JP2007103991A (en) 2007-04-19

Family

ID=38030545

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005287258A Pending JP2007103991A (en) 2005-09-30 2005-09-30 Method and apparatus of controlling phase of diversity reception

Country Status (1)

Country Link
JP (1) JP2007103991A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016076779A (en) * 2014-10-03 2016-05-12 パナソニック株式会社 Diversity receiver
JP2018160839A (en) * 2017-03-23 2018-10-11 日本電気株式会社 Receiving circuit, receiving device, and receiving method

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56168440A (en) * 1980-05-30 1981-12-24 Nissan Motor Co Ltd Diversity receiver for car
JPH04274625A (en) * 1991-03-01 1992-09-30 Toshiba Corp Diversity antenna system
JPH0993172A (en) * 1995-09-21 1997-04-04 Nec Corp Space diversity synthesis system
JP2003512745A (en) * 1999-05-04 2003-04-02 シュアー インコーポレイテッド Method and apparatus for diversity antenna with predictive switching on signal dropout
JP2003179530A (en) * 2001-12-10 2003-06-27 Alps Electric Co Ltd Receiver device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56168440A (en) * 1980-05-30 1981-12-24 Nissan Motor Co Ltd Diversity receiver for car
JPH04274625A (en) * 1991-03-01 1992-09-30 Toshiba Corp Diversity antenna system
JPH0993172A (en) * 1995-09-21 1997-04-04 Nec Corp Space diversity synthesis system
JP2003512745A (en) * 1999-05-04 2003-04-02 シュアー インコーポレイテッド Method and apparatus for diversity antenna with predictive switching on signal dropout
JP2003179530A (en) * 2001-12-10 2003-06-27 Alps Electric Co Ltd Receiver device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016076779A (en) * 2014-10-03 2016-05-12 パナソニック株式会社 Diversity receiver
JP2018160839A (en) * 2017-03-23 2018-10-11 日本電気株式会社 Receiving circuit, receiving device, and receiving method

Similar Documents

Publication Publication Date Title
JP4574681B2 (en) Diversity receiver
EP1995889A1 (en) Diversity reception device
JP2005348137A (en) Radio receiver and antenna selection method
JP2006279212A (en) Mobile broadcast receiver and control method thereof
JP2007116454A (en) Diversity receiver and reception method
JPWO2009081575A1 (en) Electronic tuner and high frequency receiver using the same
JP2007103991A (en) Method and apparatus of controlling phase of diversity reception
JP4712866B2 (en) Diversity receiving apparatus and diversity receiving method
JP2010161691A (en) Onboard receiver and method of controlling the onboard receiver
JPWO2008007490A1 (en) Diversity receiving apparatus and diversity receiving method
JP2009060178A (en) Diversity device
KR100643644B1 (en) Space diversity receiver, operation control method thereof, and computer readable recording medium which records program thereof
JP2008172670A (en) Receiver, and electronics using the same
JP2006352674A (en) Receiver
US20080218637A1 (en) Receiving apparatus, method of controlling apparatus, and program for implementing the method
JP4378263B2 (en) Receiver
JP5017070B2 (en) In-vehicle receiving apparatus and in-vehicle receiving apparatus receiving method
JP2010045706A (en) Diversity reception device and electronic apparatus using the same
JP2007104164A (en) Digital television receiver
JP4401147B2 (en) Frequency diversity receiver for digital broadcast receiver
WO2006061930A1 (en) Receiving device
JP2005136820A (en) Frequency diversity receiver in digital broadcast receiver
JP4775740B2 (en) Receiver circuit
JP2006279450A (en) On-vehicle digital television receiver
JP5257457B2 (en) Receiving device and electronic apparatus using the same

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20080331

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20100518

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20100525

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20100713

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20100803