JP4775740B2 - Receiver circuit - Google Patents

Description

  The present invention relates to a receiving circuit that receives a radio transmission signal, and more particularly to suppression of beat interference.

FIG. 2 is a block diagram showing a circuit configuration of a conventional FM radio receiver. The main part of the receiving circuit is configured in an integrated circuit (IC) 2. The first mixing circuit 4 mixes the first local oscillation signal S _LO1 output from the first local oscillation unit 6 and an RF (Radio Frequency) signal S _RF obtained from the antenna 8, and sets the target reception signal to a predetermined value. The frequency is converted to the first intermediate frequency signal _SIF1 having the intermediate frequency _fIF1 . The second mixing circuit 10 includes a second local oscillation signal _{S LO2} output from the second local oscillation unit _12, by mixing the _{S IF1,} a second intermediate frequency signal S to the _{S IF1} having a predetermined intermediate frequency _{f IF2} Frequency conversion to _IF2 . S _IF2 passes through IFBPF 14 which is a band pass filter (BPF) having f _IF2 as a center frequency, and then FM detected by the FM detection circuit 16, and the detected detection output signal S _OUT is composed of a speaker or the like. Output to the output circuit.

The first local oscillating unit 6 includes a first oscillating circuit 20 configured using a PLL (Phase Lock Loop) and a frequency dividing circuit 22. The IC 2 is provided with a crystal oscillation circuit 26 using a crystal oscillator 24 externally attached to the IC 2. The first oscillation circuit 20 receives the original oscillation signal S ₀ having the frequency f ₀ from the crystal oscillation circuit 26. In the first oscillation circuit 20, _{S 0} is used as the reference oscillation signal of the PLL. The first oscillation circuit 20 changes the frequency f _OSC1 of the output oscillation signal S _{OSC1 according} to the target reception frequency f _P , and the frequency _dividing circuit 22 divides S _OSC1 to obtain the frequency (f _P + f to generate the _{S LO1} of _IF1). Then, the first mixing circuit 4 mixes S _LO1 and S _RF as described above, and converts the received signal having the frequency f _P into S _IF1 .

For example, when f _IF1 is 10.7 MHz, f ₀ can be 20.5 MHz. In this case, a signal having a frequency of 10.25 MHz obtained by dividing f ₀ by 2 can be used as the second local oscillation signal S _LO2 and f _IF2 can be set to 450 kHz.
JP 2002-158595 A

By increasing the output level of the oscillation signal S ₀ of the crystal oscillation circuit 26 is formed as a large amplitude, is secured a carrier-noise ratio (CN ratio), stability in detection is increased, sensitivity is improved. In the case of using the S ₀ to generate the reference clock, such as a logic circuit for controlling the reception circuit, by increasing the level of S _0, thereby improving the stability of the clock.

However, when the output level of S ₀ is increased, harmonics having a frequency that is m times f ₀ (m is an integer of 2 or more) included therein are also increased. The harmonic component generated in the crystal oscillation circuit 26 causes a potential fluctuation or the like in the substrate on which the receiving circuit is formed, and the harmonic component can be transmitted to the first mixing circuit 4 through such a potential fluctuation or the like. As a result, the same frequency as the harmonic component in the S _RF of the antenna 8, or frequency signals close to it is present, produces a beat the signal is mixed with the harmonic component in the first mixing circuit 4. This beat has a problem in that it passes through the subsequent circuit and is output as S _OUT , causing beat interference in the reproduced sound and reducing the reception sensitivity.

For example, for FM radio broadcasting in Japan (frequency band 76-90 MHz), the harmonic component of n = 4 (frequency 82.0 MHz) when f ₀ = 20.5 MHz is particularly problematic. In addition, for FM radio broadcasting in the United States and the like (frequency band: 87.5 to 108 MHz), n = 5 harmonic components (frequency: 102.5 MHz) are particularly problematic.

In response to this problem, Patent Document 1 discloses a technique for suppressing a beat by shifting the frequency f ₀ of the original oscillation signal S ₀ when a beat occurs. In this configuration, the intermediate frequency associated with the shift of f ₀ is also shifted. For example, when f _IF1 normally set to 10.7 MHz shifts by 20 kHz in accordance with the shift of f ₀ and becomes 10.72 MHz, f _IF2 normally set to 450 kHz also shifts by 20 kHz and becomes 470 kHz. On the other hand, the pass band of IFBPF 14 is set to a predetermined width with normal f _IF2 as the center frequency. Therefore, when f _IF2 is shifted, there is a problem that the band of the FM signal to be received is limited by the IFBPF 14, and the sound signal of the detection output may be distorted. In particular, when adjacent interference caused by another signal having a frequency close to the reception target station is received, the influence of the adjacent interference is reduced by narrowing the pass band of the IFBPF 14. Thus, in a state where the pass band of the IFBPF 14 is narrowed, the audio distortion is more likely to occur due to the shift of f _IF2 .

  The present invention has been made to solve the above-described problems, and an object thereof is to provide a receiving circuit capable of reproducing a suitable audio signal in which beat disturbance is suppressed.

  A receiving circuit according to the present invention includes a reference oscillator that generates a reference oscillation signal having a predetermined reference frequency, a local oscillation unit that generates a local oscillation signal having a frequency corresponding to a target reception frequency based on the reference oscillation signal, A control circuit that controls the intensity of the reference oscillation signal generated by the reference oscillator; and a mixing circuit that generates an intermediate frequency signal by mixing an input reception signal of radio frequency and the local oscillation signal The unit normally sets the intensity of the reference oscillation signal to a normal level, while the target reception frequency is set to a value corresponding to m times the reference frequency (m is an integer of 2 or more). In this case, the intensity is set to a suppression level lower than the normal level. The reference oscillator may be a crystal oscillation circuit using a crystal oscillator.

  According to the present invention, when the target reception frequency and the oscillation frequency of the reference oscillator have a relationship that can cause a beat, the strength of the reference oscillation signal is reduced. As a result, the harmonic component of the reference oscillation signal transmitted to the mixing circuit is reduced, making it difficult for beats to occur.

  Hereinafter, embodiments of the present invention (hereinafter referred to as embodiments) will be described with reference to the drawings.

  FIG. 1 is a block diagram showing a schematic configuration of an FM radio receiver according to an embodiment of the present invention. The main part of the FM radio receiver 50 is configured as an integrated circuit (IC) IC 52, and is used, for example, in an in-vehicle audio device of an automobile. The FM radio receiver 50 includes an antenna 54, an RF amplifier 56, a first local oscillation unit 58, a first mixing circuit 60, BPFs 62 and 66, amplifiers 64 and 74, a second local oscillation unit 68, a second mixing circuit 70, and an IFBPF 72. , An FM detection circuit 76, a crystal oscillation circuit 78, an oscillation level adjustment circuit 80, and a control unit 82.

The RF signal S _RF received by the antenna 54 is amplified by the RF amplifier 56 and then input to the first mixing circuit 60. The first mixing circuit 60 mixes the input RF signal S _RF with the first local oscillation signal S _LO1 input from the first local oscillation unit 58 to generate a first intermediate signal S _IF1 . Frequency of S _{LO1 f LO1 is} such that the signal of interest received station of the frequency _{f P} contained in the _{S RF} is converted to a first intermediate frequency _{f IF1} predetermined by the frequency conversion to _{S IF1} by the first mixing circuit 60 Adjusted to The first intermediate frequency _{f IF1} is set to, for example, 10.7 MHz.

S _IF1 is input to the second mixing circuit 70 via the BPF 62, the amplifier 64, and the BPF 66. The second mixing circuit 70 mixes the input first intermediate signal S _IF1 with the second local oscillation signal S _LO2 input from the second local oscillation unit 68 to obtain a second intermediate of the second intermediate frequency f _IF2 . A signal _SIF2 is generated. The frequency f _{LO2 of} S _LO2 is set to (f _IF1 −f _IF2 ), and the target reception signal of the frequency f _IF1 included in S _IF1 is converted into the frequency f _IF2 in the second mixing circuit 70. The second intermediate frequency f _IF2 is set to 450 kHz, for example.

S _IF2 is input to the FM detection circuit 76 via the IFBPF 72 and the amplifier 74. The FM detection circuit 76 is composed of, for example, a quadrature detection circuit. The FM detection circuit 76 performs FM detection on the S _IF2 input from the amplifier 74, extracts a detection output signal S _OUT in the voice band, and outputs it to an output circuit including a speaker or the like.

  The first local oscillation unit 58 includes a first oscillation circuit 90 and a frequency dividing circuit 92.

The first oscillation circuit 90 outputs an oscillation signal S _OSC1 having a frequency f _OSC1 . The first oscillation circuit 70 is configured by a PLL circuit that uses the original oscillation signal S ₀ output from the crystal oscillation circuit 78 as a reference oscillation signal. Specifically, the first oscillation circuit 90 includes a phase comparison unit 100, a loop filter 102, a voltage controlled oscillator (VCO) 104, and frequency dividing circuits 106 and 108.

Divider circuit 106, the _{S 0} from the crystal oscillator 78 and r division, generates a reference oscillation signal _{S R} of the phase comparator 100. Dividing ratio r may be, for example, the frequency f _R of the S _R is set to be a value corresponding to the interval of the carrier frequency assigned to the radio station.

On the other hand, the frequency dividing circuit 108 divides S _OSC1 generated by the VCO 104 by n and generates an oscillation signal _SN fed back to the phase comparison unit 100. Division ratio n, depending on the frequency f _P of the object receiving station is set by the control unit 82.

Phase comparator 100 generates a pulse having a time width corresponding to a phase difference between S _R supplied from S _N and division circuit 106 which is input from the frequency divider circuit 108.

The loop filter 102 smoothes the output of the phase comparison unit 100 and generates a control voltage V _T. The VCO 104 changes the oscillation frequency according to V _T , and as a result, the generated S _OSC1 is input to the phase comparison unit 100 via the frequency divider circuit 108 as described above.

The PLL circuit is configured to feedback control so that the frequency _{f N} of the _{S N} coincides with the frequency _{f R} of _{S R,} generates a _{S OSC1} with a frequency _{f OSC1} corresponding to the intended receiving station, the output to the frequency divider circuit 92 To do. f _OSC1 is set to α · (f _P + f _IF1 ). Here, α is a frequency dividing ratio of the frequency dividing circuit 92.

As described above, the frequency _dividing circuit 92 divides S _OSC1 from the first oscillation circuit 90 by α, generates S _LO1, and outputs it to the first mixing circuit 60. Incidentally, by changing the frequency dividing ratio α of the frequency dividing circuit 92, the radio receiver can flexibly cope with a plurality of broadcast bands. For example, by setting the frequency division ratio α according to the country in which the radio receiver is used, it is possible to receive broadcasts in different bands depending on the country. For example, in the frequency dividing circuit 92, α can be set to any one of 1, 2, and 3.

Crystal oscillator circuit 78 is configured by using a crystal oscillator 84 which is externally attached to the IC 52, and outputs the original oscillation signal S ₀ of the frequency f _0. The crystal oscillation circuit 78 is configured so that the oscillation output level can be adjusted by the oscillation level adjustment circuit 80. In the present embodiment, _{f 0} is set to 20.5MHz.

  The oscillation level adjustment circuit 80 controls the output level of the crystal oscillation circuit 78 in accordance with a control signal from the control unit 82. This control can be performed, for example, by adjusting the gain of the amplifier constituting the crystal oscillation circuit 78.

The second local oscillating unit 68 generates S _LO2 having a frequency f _LO2 of 10.25 MHz corresponding to the case where f _IF1 = 10.7 MHz and f _IF2 = 450 kHz. In order to generate this S _LO2 , the second local oscillation unit 68 of the present embodiment has a _{frequency dividing} circuit 94. The frequency dividing circuit 94 divides the 20.5 MHz oscillation signal S ₀ from the crystal oscillation circuit 78 by 2 to generate the S _LO2 and supplies it to the second mixing circuit 70.

IFBPF72 _is centered frequency _{f IF2,} and a band-pass filter the pass bandwidth _{W F} can be variably set. Bandwidth _{W F} passing IFBPF72 are wide and narrow is switched according to the presence or absence of adjacent interference. Specifically, when the adjacent interference wave does not exist, while setting the W _F to the reference bandwidth of spread so as not to cause audio distortion, when the adjacent interfering wave exists, a reference bandwidth W _F By making it narrower, adjacent interference removal can be achieved.

For example, the control unit 82 sets the frequency division ratio n of the frequency dividing circuit 108 of the first oscillation circuit 90 and switches the frequency dividing ratio α of the frequency dividing circuit 92. For example, the control unit 82 can be configured to include a microcomputer, and n corresponding to the frequency f _{P of the} receiving station is stored in advance in the storage unit, and according to the setting of the target receiving station from the user, The corresponding n can be read from the storage unit and set in the frequency dividing circuit 108. The control unit 82 controls the output level of the crystal oscillation circuit 78 via the oscillation level adjustment circuit 80. This level control will be described below.

In response to the tuning operation by the user, the control unit 82 normally performs processing for setting the frequency division ratio n of the frequency dividing circuit 108 to a value corresponding to the selected target receiving station, while the output of the crystal oscillation circuit 78 is set. The level is maintained at a normal level which is a relatively high level. On the other hand, when the frequency f _{P of} the selected target receiving station coincides with m times (m is an integer of 2 or more) the oscillation frequency f ₀ of the crystal oscillation circuit 78, or a value close thereto. Sets the frequency division ratio n of the frequency dividing circuit 108 and sets the output level of the crystal oscillation circuit 78 to a level lower than the normal level (suppression level). For example, when f ₀ = 20.5 MHz, in Japan, 82.0 MHz, which is four times the frequency of f ₀ , belongs to the FM broadcast band, and in the United States and the like, 102.5 MHz, which is five times the frequency of f ₀ , is FM. Belongs to the broadcast band. Therefore, the control unit 82 of the FM radio receiver 50 used in Japan, if _{f P} is 82.0MHz, can be configured to set the _{S 0} suppression level. The control unit 82 of the FM radio receiver 50 for use in the United States, etc. _can be _{f P} is the case of 102.5MHz, configured to set the _{S 0} suppression level.

For example, the setting level of the output intensity of the crystal oscillation circuit 78 is stored in advance in the storage unit of the microcomputer constituting the control unit 82 together with the frequency division ratio n of the frequency dividing circuit 108 in correspondence with the frequency f _{P of the} receiving station. I can keep it. Then, the control unit 82 reads the corresponding setting level and the frequency division ratio n from the storage unit according to the selection of the receiving station by the user, and interlocks with the operation for setting the frequency division ratio n to the frequency dividing circuit 108. The intensity of the crystal oscillation circuit 78 is controlled to the set level.

The suppression level is determined so that the harmonic component included in S ₀ is preferably prevented from entering the first mixing circuit 60. Thereby, beat disturbance is suppressed. At that time, the CN ratio is lowered, which may affect the operational stability of the receiver. Therefore, the suppression level is determined in consideration of the balance between the beats so that the beat is suitably suppressed and the stability is not excessively impaired.

Incidentally, the output level adjustment of the crystal oscillation circuit 78, the frequency _{f 0} is kept _constant, f _{IF1, f IF2,} etc. are not changed by the level switching. _Therefore, the bandwidth of the _{S IF2} is not changed at the normal time when the suppression level, the _{S IF2} at the set state to the suppression level, that usually more susceptible to the band limitation in IFBPF72 than _{S IF2} during That is, there is no particular increase in audio distortion. That is, according to the present invention, beat disturbance can be suitably suppressed. Further, when adjacent interference can occur, beat interference is suppressed while avoiding the adjacent interference and audio distortion.

  In the above-described embodiment, the reference oscillation signal is generated by the crystal oscillation circuit 78. However, the reference oscillation signal may be generated by another type of oscillation circuit. The present invention can also be applied to an AM radio receiver and other wireless reception devices.

It is a block diagram which shows the structure of the outline of the FM radio receiver which is embodiment of this invention. It is a block diagram which shows the circuit structure of the conventional FM radio receiver.

Explanation of symbols

  50 FM radio receiver, 52 IC, 54 antenna, 56 RF amplifier, 58 first local oscillator, 60 first mixing circuit, 62,66 BPF, 64,74 amplifier, 68 second local oscillator, 70 second mixing Circuit, 72 IFBPF, 76 FM detection circuit, 78 crystal oscillation circuit, 80 oscillation level adjustment circuit, 82 control unit, 84 crystal oscillator, 90 first oscillation circuit, 92, 94, 106, 108 frequency division circuit, 100 phase comparison Part, 102 loop filter, 104 VCO.

Claims (3)

A reference oscillator that generates a reference oscillation signal of a predetermined reference frequency;
Based on the reference oscillation signal, a local oscillation unit that generates a local oscillation signal having a frequency corresponding to a target reception frequency;
A mixing circuit that mixes a radio frequency input reception signal and the local oscillation signal to generate an intermediate frequency signal;
A control unit for controlling the intensity of the reference oscillation signal generated by the reference oscillator;
Have
The controller is
Usually, when the intensity of the reference oscillation signal is set to a normal level, the target reception frequency is set to a value corresponding to m times the reference frequency (m is an integer of 2 or more). Setting the intensity to a suppression level lower than the normal level;
A receiving circuit. The receiving circuit according to claim 1,
The reference oscillator is a crystal oscillation circuit using a crystal oscillator;
A receiving circuit. The receiving circuit according to claim 1 or 2,
The local oscillation unit is a PLL circuit that operates based on a phase difference between two input oscillation signals based on the reference oscillation signal and the local oscillation signal, and divides the local oscillation signal by a variable frequency division ratio n. A frequency dividing circuit that circulates and generates one of the input oscillation signals;
The controller is
A storage unit that stores the division ratio n of the reference oscillation signal and the setting level of the intensity in advance corresponding to the target reception frequency;
The division ratio n and the set level corresponding to the set target reception frequency are read from the storage unit, the operation for setting the division ratio n in the frequency divider circuit, and the reference oscillation signal based on the set level In conjunction with the intensity control operation of
A receiving circuit.

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