JPH09232756A - Manufacture of multilayered printed-wiring board - Google Patents

Manufacture of multilayered printed-wiring board

Info

Publication number
JPH09232756A
JPH09232756A JP3183496A JP3183496A JPH09232756A JP H09232756 A JPH09232756 A JP H09232756A JP 3183496 A JP3183496 A JP 3183496A JP 3183496 A JP3183496 A JP 3183496A JP H09232756 A JPH09232756 A JP H09232756A
Authority
JP
Japan
Prior art keywords
insulating layer
hydrogen fluoride
wiring board
inorganic filler
printed wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3183496A
Other languages
Japanese (ja)
Inventor
Koji Takagi
光司 高木
Shuji Maeda
修二 前田
Masayuki Ishihara
政行 石原
Hajime Sugiyama
肇 杉山
Shingo Yoshioka
慎悟 吉岡
Shinichi Iketani
晋一 池谷
Hiroaki Fujiwara
弘明 藤原
Katsuhiko Ito
克彦 伊藤
Kiyoaki Ihara
清暁 井原
Satoru Ogawa
悟 小川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP3183496A priority Critical patent/JPH09232756A/en
Publication of JPH09232756A publication Critical patent/JPH09232756A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufactuting a multilayered printed-wiring board of a build-up system, which makes the adhesion of an insulating layer to a conductor layer enhance and makes to provide the printed-wiring board with a high-adhesion conductor circuit. SOLUTION: An insulating layer consisting of a resin composition formed by dispersing an inorganic filler soluble to a hydrogen fluoride solution in a matrix resin refractory to the hydrogen fluoride solution is formed on the surface of a core board having a conductor circuit on its surface and thereafter, a perforating is conducted in the above insulating layer by a laser beam. Then, the surface of the insulating layer including the wall surface of the hole is subjected to a surface treatment with a hydrogen fluoride solution, then, a plated layer is formed on the surface of the insulating layer including the wall surface of the hole and moreover, a prescribed conductor circuit is formed on this plated layer.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、多層プリント配線
板の製造方法に関し、さらに詳しくは絶縁層上に回路パ
ターンを形成するビルドアップ方式の多層プリント配線
板の製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a multilayer printed wiring board, and more particularly to a method for manufacturing a build-up type multilayer printed wiring board in which a circuit pattern is formed on an insulating layer.

【0002】[0002]

【従来の技術】近年、電子・電気機器の小型化、軽量化
に伴い、多層プリント配線板の薄型化が要望されてい
る。この要望を満たすものとしてコア基板の表面に絶縁
層を介して回路パターンを積み上げて形成するビルドア
ップ方式の多層プリント配線板が注目されている。この
ビルドアップ方式の多層プリント配線板では、一括で多
層化した後スルホールにより各層の導体回路が接続され
る従来の多層プリント配線板に比べ、スルホールによっ
て配線が邪魔されないために配線ピッチが同じでも配線
密度が向上し、かつ絶縁層を薄く形成できるので多層プ
リント配線板の高密度化、薄型化が可能になる利点があ
る。そして、その製造方法としては下記の工程を順次行
う方法が知られている。 表面に導体回路を有するコア基板(多層化基板を含
む)の前記表面に樹脂組成物からなる絶縁層を形成す
る。 得られた絶縁層にビアホールを形成する。 デスミア処理によりビアホールを形成した絶縁層の表
面粗化を行う。 銅メッキ等の方法で絶縁層上に導体層を形成し、次い
でこの導体層に所定の回路パターンを形成する。この
際、ビアホールの壁面にも導体を付与し、この導体によ
りコア基板の導体回路と絶縁層上の導体回路を電気的に
接続する。 以下、上記の工程を繰り返して所望の多層プリント配
線板を製造する。
2. Description of the Related Art In recent years, as electronic and electric devices have become smaller and lighter, there has been a demand for thinner multilayer printed wiring boards. In order to meet this demand, a build-up type multilayer printed wiring board, in which a circuit pattern is stacked and formed on the surface of a core substrate via an insulating layer, has been receiving attention. In this build-up type multilayer printed wiring board, compared to the conventional multilayer printed wiring board in which the conductor circuits of each layer are connected after they are multilayered at once, the wiring is not obstructed by the through holes, so the wiring pitch is the same. Since the density is improved and the insulating layer can be formed thin, there is an advantage that the multi-layer printed wiring board can be made higher in density and thinner. As a manufacturing method thereof, a method of sequentially performing the following steps is known. An insulating layer made of a resin composition is formed on the surface of a core substrate (including a multilayer substrate) having a conductor circuit on the surface. A via hole is formed in the obtained insulating layer. The surface of the insulating layer in which the via hole is formed is roughened by the desmear treatment. A conductor layer is formed on the insulating layer by a method such as copper plating, and then a predetermined circuit pattern is formed on the conductor layer. At this time, a conductor is also provided on the wall surface of the via hole, and the conductor circuit of the core substrate and the conductor circuit on the insulating layer are electrically connected by this conductor. Hereinafter, the above steps are repeated to manufacture a desired multilayer printed wiring board.

【0003】なお、上記のビルドアップ方式の多層プリ
ント配線板の製造方法に関して、感光性樹脂を用いて絶
縁層を形成し、フォトリソグラフィー法でビアホールを
形成する方法(特開昭62-206899 号、特開平4-199783号
等)や、熱硬化性樹脂を用いて絶縁層を形成し、レーザ
ー加工によりビアホールを形成する方法(特開昭62-291
095 号、特開平3-233997号等)等が提案されている。
Regarding the method of manufacturing the above-mentioned build-up type multilayer printed wiring board, a method of forming an insulating layer by using a photosensitive resin and forming a via hole by a photolithography method (JP-A-62-206899, (JP-A-4-199783, etc.) or a method of forming an insulating layer using a thermosetting resin and forming via holes by laser processing (JP-A-62-291).
No. 095, JP-A-3-233997, etc.) have been proposed.

【0004】しかし、上記のビルドアップ方式の多層プ
リント配線板の製造方法では、熱硬化性樹脂を用いて絶
縁層を形成する場合、硬化した熱硬化性樹脂の表面に残
存する硬化剤の未反応成分や、硬化度合いのバラツキ
や、酸化雰囲気による熱硬化性樹脂の表面の酸化等の影
響によって、デスミア処理による絶縁層の表面粗化の程
度が場所によって不均一になるためと考えられるが、表
面粗化した絶縁層上に銅メッキ等の方法で形成した導体
層と絶縁層の密着力が不十分であるという問題があり、
その改善が求められていた。
However, in the above build-up method for manufacturing a multilayer printed wiring board, when the insulating layer is formed by using a thermosetting resin, the curing agent remaining on the surface of the cured thermosetting resin is not reacted. It is considered that the degree of surface roughening of the insulating layer due to desmear treatment becomes uneven depending on the location due to the influence of the components, the degree of hardening, and the oxidation of the surface of the thermosetting resin due to the oxidizing atmosphere. There is a problem that the adhesion between the conductor layer and the insulating layer formed by a method such as copper plating on the roughened insulating layer is insufficient,
The improvement was required.

【0005】[0005]

【発明が解決しようとする課題】本発明は上記のような
事情に鑑みてなされたものであって、その目的とすると
ころは、絶縁層と導体層との密着力が向上していて、従
って、密着力の高い導体回路を備える多層プリント配線
板が得られるビルドアップ方式の多層プリント配線板の
製造方法を提供することである。
SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to improve the adhesion between the insulating layer and the conductor layer. Provided is a method for manufacturing a build-up type multilayer printed wiring board, which can obtain a multilayer printed wiring board having a conductor circuit having high adhesion.

【0006】[0006]

【課題を解決するための手段】請求項1に係る発明の多
層プリント配線板の製造方法は、表面に導体回路を有す
るコア基板の前記表面に、フッ化水素系溶液に難溶なマ
トリックス樹脂中に、フッ化水素系溶液に可溶な無機フ
ィラーが分散している樹脂組成物からなる絶縁層を形成
した後、前記絶縁層にレーザーで孔あけし、次いで孔の
壁面を含む絶縁層の表面をフッ化水素系溶液で表面処理
し、次いで孔の壁面を含む絶縁層の表面にメッキ層を形
成し、次いでこのメッキ層に所定の導体回路を形成する
ことを特徴とする。
According to a first aspect of the present invention, there is provided a method for manufacturing a multilayer printed wiring board, comprising: a core resin having a conductor circuit on the surface thereof; After forming an insulating layer made of a resin composition in which an inorganic filler soluble in a hydrogen fluoride-based solution is dispersed, the insulating layer is laser-drilled, and then the surface of the insulating layer including the wall surface of the hole is formed. Is surface-treated with a hydrogen fluoride-based solution, then a plating layer is formed on the surface of the insulating layer including the wall surface of the hole, and then a predetermined conductor circuit is formed on this plating layer.

【0007】請求項2に係る発明の多層プリント配線板
の製造方法は、請求項1記載の製造方法において、フッ
化水素系溶液がフッ化水素アンモニウム又はフッ化水素
を含有する溶液であることを特徴とする。
According to a second aspect of the present invention, there is provided a method for producing a multilayer printed wiring board according to the first aspect, wherein the hydrogen fluoride-based solution is a solution containing ammonium hydrogen fluoride or hydrogen fluoride. Characterize.

【0008】請求項3に係る発明の多層プリント配線板
の製造方法は、請求項1又は請求項2記載の製造方法に
おいて、コア基板の表面に形成する絶縁層が2層からな
っていて、コア基板の表面に接する側の絶縁層の無機フ
ィラー含有割合がコア基板の表面から遠い側の絶縁層の
無機フィラー含有割合よりも低いことを特徴とする。
A method for manufacturing a multilayer printed wiring board according to a third aspect of the present invention is the method for manufacturing a multilayer printed wiring board according to the first or second aspect, wherein the insulating layer formed on the surface of the core substrate is composed of two layers. The content of the inorganic filler in the insulating layer on the side in contact with the surface of the substrate is lower than the content of the inorganic filler in the insulating layer on the side far from the surface of the core substrate.

【0009】請求項4に係る発明の多層プリント配線板
の製造方法は、請求項1から請求項3までのいずれかに
記載の製造方法において、無機フィラーがマイカ又はシ
リカであることを特徴とする。
According to a fourth aspect of the present invention, there is provided a method for producing a multilayer printed wiring board according to any one of the first to third aspects, wherein the inorganic filler is mica or silica. .

【0010】本発明において、フッ化水素系溶液に可溶
な無機フィラーが分散している樹脂組成物からなる絶縁
層を形成し、この絶縁層の表面をフッ化水素系溶液で表
面処理し、次いで絶縁層の表面にメッキ層を形成するこ
とは、絶縁層の表面に存在する無機フィラーがフッ化水
素系溶液で選択的に除去されるため、いわゆるアンカー
効果を生じさせて、絶縁層とメッキ層(導体層)との密
着力を向上させる作用がある。
In the present invention, an insulating layer made of a resin composition in which an inorganic filler soluble in a hydrogen fluoride solution is dispersed is formed, and the surface of the insulating layer is surface-treated with the hydrogen fluoride solution. Next, by forming a plating layer on the surface of the insulating layer, the inorganic filler present on the surface of the insulating layer is selectively removed by the hydrogen fluoride-based solution, so that a so-called anchor effect is generated, and the plating with the insulating layer is performed. It has the effect of improving the adhesion with the layer (conductor layer).

【0011】[0011]

【発明の実施の形態】本発明では、表面に導体回路を有
するコア基板の前記表面に、フッ化水素系溶液に難溶な
マトリックス樹脂中に、フッ化水素系溶液に可溶な無機
フィラーが分散している樹脂組成物からなる絶縁層を形
成する。本発明で使用する導体回路を有するコア基板と
しては、例えば、FR−4グレードやFR−5グレード
の銅張り積層板をエッチング加工して、導体回路を表面
に形成した基板を例示することができる。そして、ここ
でいうフッ化水素系溶液とは、実質的にSiO2 成分等
の無機成分をエッチング可能なフッ化水素成分を含有し
ている溶液を表していて、例えばフッ化水素アンモニウ
ムの水溶液やフッ化水素の水溶液(フッ酸)等を例示で
きる。また、フッ化水素系溶液に難溶なマトリックス樹
脂としては、特に限定するものではないが、FR−4グ
レードやFR−5グレードの銅張り積層板に使用される
エポキシ樹脂系の熱硬化性樹脂やポリイミド樹脂系の熱
硬化性樹脂等が例示でき、多層プリント配線板の使用温
度領域によって最適なマトリックス樹脂を選定すればよ
い。また、フッ化水素系溶液に可溶な無機フィラーとし
ては、特に限定するものではないが、破砕状のシリカ、
破砕状のマイカ、球状のシリカ等が例示でき、多層プリ
ント配線板に要求される特性によって最適なものを選定
すればよい。本発明で使用する無機フィラーの形状につ
いては短繊維状のものより、破砕状又は球状のものの方
が、絶縁層とメッキ層との密着力の向上のためには好ま
しい。無機フィラーの粒子径については、特に限定する
ものではないが、平均粒子径で2〜15μm程度のもの
が、絶縁層とメッキ層との密着力の向上のためには好ま
しい。また、絶縁層を形成する樹脂組成物中の無機フィ
ラーの含有率については、特に限定するものではない
が、5〜40重量%の範囲内であることが好ましい。5
重量%未満では絶縁層とメッキ層との密着力を向上させ
る効果が不十分となりやすく、40重量%を越えると絶
縁層の製膜性が損なわれる恐れがあるからである。
BEST MODE FOR CARRYING OUT THE INVENTION In the present invention, on a surface of a core substrate having a conductor circuit on its surface, an inorganic filler soluble in a hydrogen fluoride-based solution is contained in a matrix resin which is hardly soluble in the hydrogen fluoride-based solution. An insulating layer made of the dispersed resin composition is formed. Examples of the core substrate having a conductor circuit used in the present invention include a substrate having a conductor circuit formed on the surface by etching a copper-clad laminate of FR-4 grade or FR-5 grade. . The term "hydrogen fluoride solution" as used herein refers to a solution containing a hydrogen fluoride component capable of substantially etching an inorganic component such as a SiO 2 component, such as an aqueous solution of ammonium hydrogen fluoride or Examples thereof include an aqueous solution of hydrogen fluoride (hydrofluoric acid). Further, the matrix resin which is hardly soluble in the hydrogen fluoride-based solution is not particularly limited, but an epoxy resin-based thermosetting resin used for FR-4 grade or FR-5 grade copper-clad laminate Examples thereof include polyimide resin-based thermosetting resins, and an optimum matrix resin may be selected depending on the operating temperature range of the multilayer printed wiring board. The inorganic filler soluble in the hydrogen fluoride solution is not particularly limited, but crushed silica,
Examples include crushed mica and spherical silica, and the most suitable one may be selected according to the characteristics required for the multilayer printed wiring board. Regarding the shape of the inorganic filler used in the present invention, a crushed or spherical shape is preferable to a short fiber shape in order to improve the adhesion between the insulating layer and the plating layer. The particle size of the inorganic filler is not particularly limited, but an average particle size of about 2 to 15 μm is preferable for improving the adhesion between the insulating layer and the plating layer. Moreover, the content of the inorganic filler in the resin composition forming the insulating layer is not particularly limited, but is preferably in the range of 5 to 40% by weight. 5
If it is less than 40% by weight, the effect of improving the adhesion between the insulating layer and the plating layer tends to be insufficient, and if it exceeds 40% by weight, the film-forming property of the insulating layer may be impaired.

【0012】絶縁層をコア基板の表面に形成する方法と
しては、カーテンコータ方式、スプレー方式等が例示で
きるが、特に限定はない。そして、使用するマトリック
ス樹脂によっては、絶縁層を形成する樹脂組成物を塗布
した後、乾燥、硬化を行って硬化膜とすることもでき
る。さらに、コア基板の表面に形成する絶縁層を2層構
成とし、図1に示すように、コア基板1の導体回路2を
備える表面に接している側の絶縁層3aの無機フィラー
含有割合がコア基板の表面から遠い側の絶縁層3bの無
機フィラー含有割合よりも低くなるようにすると、コア
基板の表面と絶縁層の密着力が無機フィラーの存在によ
って低下する現象を防止できるので好ましい。また、2
層構成とする場合には、各層のマトリックス樹脂の種類
を異なるものとすることもできる。
As a method for forming the insulating layer on the surface of the core substrate, a curtain coater method, a spray method and the like can be exemplified, but there is no particular limitation. Then, depending on the matrix resin used, a resin composition for forming an insulating layer may be applied, followed by drying and curing to form a cured film. Furthermore, the insulating layer formed on the surface of the core substrate has a two-layer structure, and as shown in FIG. 1, the inorganic filler content ratio of the insulating layer 3a on the side in contact with the surface of the core substrate 1 on which the conductor circuit 2 is provided is the core. It is preferable to lower the content of the inorganic filler in the insulating layer 3b on the side farther from the surface of the substrate, because it is possible to prevent the adhesion between the surface of the core substrate and the insulating layer from decreasing due to the presence of the inorganic filler. Also, 2
In the case of a layered structure, the type of matrix resin of each layer may be different.

【0013】本発明では、上記のようにしてコア基板の
表面に形成した絶縁層に、レーザーで孔あけをする。な
お、レーザーを照射する位置のコア基板上にレーザーに
対する防御部となる導体回路が備わっていれば、レーザ
ーは導体回路で反射され、選択的に絶縁層のみが孔あけ
される。本発明で使用するレーザーとしては、特に限定
するものではないが、炭酸ガスレーザーを例示すること
ができる。本発明では、絶縁層にレーザーで孔あけした
後、孔の壁面を含む絶縁層の表面をフッ化水素系溶液で
表面処理する。使用するフッ化水素系溶液としては、前
記したように、フッ化水素アンモニウムの水溶液やフッ
化水素の水溶液(フッ酸)等を例示できるが、取扱い性
の点からフッ化水素アンモニウムの水溶液が好ましい。
フッ化水素系溶液には、基板の濡れ性を向上させるため
の界面活性剤等の添加剤を添加していてもよく、また、
40〜60℃程度に加温するようにしてもよい。
In the present invention, the insulating layer formed on the surface of the core substrate as described above is laser-drilled. If a conductor circuit serving as a protection portion against the laser is provided on the core substrate at the position where the laser is irradiated, the laser is reflected by the conductor circuit, and only the insulating layer is selectively perforated. The laser used in the present invention is not particularly limited, but a carbon dioxide gas laser can be exemplified. In the present invention, after the insulating layer is perforated with a laser, the surface of the insulating layer including the wall surface of the hole is surface-treated with a hydrogen fluoride-based solution. As the hydrogen fluoride-based solution to be used, an aqueous solution of ammonium hydrogen fluoride or an aqueous solution of hydrogen fluoride (hydrofluoric acid) can be exemplified as described above, but an aqueous solution of ammonium hydrogen fluoride is preferable from the viewpoint of handleability. .
An additive such as a surfactant for improving the wettability of the substrate may be added to the hydrogen fluoride-based solution,
You may make it heat to about 40-60 degreeC.

【0014】本発明では、絶縁層の表面をフッ化水素系
溶液で表面処理した後、孔の壁面を含む絶縁層の表面に
メッキ層を形成し、次いでこのメッキ層に所定の導体回
路を形成する。メッキ層を形成する方法としては、特に
限定はなく、無電解メッキを行った後電解メッキを行う
方法等で行えばよい。また、メッキ層への導体回路の形
成方法についても、特に限定はなく、エッチングレジス
トで非エッチング部を被覆した後、エッチングし、次い
でレジストを剥離する方法等で行えばよい。
In the present invention, after the surface of the insulating layer is surface-treated with a hydrogen fluoride-based solution, a plating layer is formed on the surface of the insulating layer including the wall surfaces of the holes, and then a predetermined conductor circuit is formed on the plating layer. To do. The method for forming the plating layer is not particularly limited, and a method of performing electroless plating followed by electrolytic plating may be used. The method of forming the conductor circuit on the plating layer is not particularly limited, and may be a method of covering the non-etched portion with an etching resist, etching the resist, and then peeling the resist.

【0015】[0015]

【実施例】以下の実施例及び比較例では絶縁層にレーザ
ーで孔あけする工程を省略して、メッキ層を形成し、こ
のメッキ層と絶縁層との密着力を評価するようにした。
EXAMPLES In the following Examples and Comparative Examples, the step of laser drilling in the insulating layer was omitted, a plating layer was formed, and the adhesion between the plating layer and the insulating layer was evaluated.

【0016】(実施例1〜3)臭素化ビスフェノールA
型エポキシ樹脂(ダウケミカル社製、商品名:DER5
11)70重量部、クレゾールノボラック型エポキシ樹
脂(東都化成社製、商品名:YDCN702P)30重
量部、ジシアンジアミド3.5重量部、2-エチル4-メチ
ルイミダゾール0.08重量部を有機溶媒に溶解して樹
脂ワニスAを調製した。この樹脂ワニスAに表1に示す
ように無機フィラーを添加し、混合して無機フィラー入
り樹脂ワニスを調製した。なお、表1に示す添加量は無
機フィラー入り樹脂ワニス全体の固形分中での重量%を
示している。
(Examples 1 to 3) Brominated bisphenol A
Type epoxy resin (Dow Chemical Co., trade name: DER5
11) 70 parts by weight, cresol novolac type epoxy resin (manufactured by Tohto Kasei Co., trade name: YDCN702P) 30 parts by weight, dicyandiamide 3.5 parts by weight, 2-ethyl 4-methylimidazole 0.08 parts by weight dissolved in an organic solvent Then, a resin varnish A was prepared. An inorganic filler was added to this resin varnish A as shown in Table 1 and mixed to prepare a resin varnish containing an inorganic filler. In addition, the addition amount shown in Table 1 shows weight% in the solid content of the whole resin varnish containing an inorganic filler.

【0017】[0017]

【表1】 [Table 1]

【0018】FR−4グレードの銅張り積層板に回路を
形成したコア基板の表面に、前記で得られた無機フィラ
ー入り樹脂ワニスをカーテンコータで塗布し、次いで、
120℃/20分+145℃/30分の多段加熱を施し
て、厚みが50μmの、無機フィラーが分散している樹
脂組成物からなる絶縁層を形成した。次に、形成した絶
縁層表面の酸化膜除去の目的で、デスミア処理を行う。
デスミア液としてはシプレイ社製の膨潤液(品番MLB
211)とKMnO4 液(品番MLB213)を用い、
各々の液で80℃/10分の処理を行った。次いで、絶
縁層の表面をフッ化水素系溶液を用いて、60℃/10
分の条件で表面処理して、絶縁層の表面にあった無機フ
ィラーを溶解除去した。フッ化水素系溶液としては、フ
ッ化水素を成分として含有しているメルテックス社製の
ガラスエッチ剤(商品名エンプレートMLB498と商
品名エンプレートMLBガラスエッチアディティブの混
合液)を使用した。次いで、絶縁層の表面に10μm厚
の銅膜からなるメッキ層を形成した。なお、メッキ層の
形成は、シプレイ社製のロッシェル塩タイプの無電解銅
メッキ液を使用して、無電解メッキ法で薄膜を形成した
後、硫酸銅系の電気メッキ液を使用して、1A/dmの
条件で60分間電気メッキをする方法で行った。
The resin varnish containing the inorganic filler obtained above was applied to the surface of a core substrate having a circuit formed on a FR-4 grade copper-clad laminate using a curtain coater, and then,
Multi-stage heating at 120 ° C./20 minutes + 145 ° C./30 minutes was performed to form an insulating layer having a thickness of 50 μm and made of a resin composition in which an inorganic filler was dispersed. Next, a desmear process is performed for the purpose of removing the oxide film on the surface of the formed insulating layer.
As the desmear liquid, a swelling liquid manufactured by Shipley (product number MLB
211) and KMnO 4 liquid (product number MLB213),
Each liquid was treated at 80 ° C for 10 minutes. Then, the surface of the insulating layer is treated at 60 ° C./10 with a hydrogen fluoride solution.
The inorganic filler on the surface of the insulating layer was dissolved and removed by performing the surface treatment under the condition of minutes. As the hydrogen fluoride-based solution, a glass etching agent (mixed liquid of trade name Enplate MLB498 and trade name Enplate MLB glass etch additive) manufactured by Meltex Co. containing hydrogen fluoride as a component was used. Then, a plating layer made of a copper film having a thickness of 10 μm was formed on the surface of the insulating layer. The plating layer is formed by using a Rochelle salt type electroless copper plating solution manufactured by Shipley Co., Ltd. and forming a thin film by an electroless plating method, and then using a copper sulfate-based electroplating solution. The electroplating was performed for 60 minutes under the condition of / dm.

【0019】次いで得られたメッキ層と絶縁層の密着力
をピ−ル強度で評価した。ピール強度の測定方法は、メ
ッキ層を形成したコア基板を切断して幅1cmの短冊を
作製し、メッキ層と絶縁層の間のL字ピ−ル強度を測定
した。なお、測定は1mm/分の引き剥がし速度で行っ
た。得られた結果を表2に示す。
Next, the adhesion between the obtained plated layer and the insulating layer was evaluated by the peel strength. The peel strength was measured by cutting the core substrate on which the plating layer was formed to form a strip having a width of 1 cm, and measuring the L-shaped peel strength between the plating layer and the insulating layer. The measurement was performed at a peeling speed of 1 mm / min. Table 2 shows the obtained results.

【0020】(実施例4)実施例1で使用したFR−4
グレードの銅張り積層板に回路を形成したコア基板を実
施例4でもコア基板として使用した。このコア基板の表
面に、前記の樹脂ワニスA(無機フィラー未添加)をカ
ーテンコータで塗布し、次いで、120℃/20分+1
45℃/30分の多段加熱を施して、厚みが25μm
の、無機フィラーが分散していない樹脂組成物からなる
下地の絶縁層を形成した。次に、下地の絶縁層の上に実
施例1で使用した無機フィラー入り樹脂ワニスをカーテ
ンコータで塗布し、次いで、120℃/20分+145
℃/30分の多段加熱を施して、厚みが25μmの、無
機フィラーが分散している樹脂組成物からなる表層の絶
縁層を形成した。このようにして2層構成の絶縁層をコ
ア基板の表面に形成した。次いで、実施例1と同様にし
て、デスミア処理、絶縁層の表面のフッ化水素系溶液に
よる表面処理、メッキ層の形成及びメッキ層と絶縁層の
密着力の評価を行った。得られた評価結果を表2に示
す。
Example 4 FR-4 used in Example 1
A core substrate having a circuit formed on a grade copper-clad laminate was also used as the core substrate in Example 4. On the surface of this core substrate, the above resin varnish A (without addition of inorganic filler) was applied with a curtain coater, and then 120 ° C./20 minutes + 1
The thickness is 25 μm after being subjected to multi-stage heating at 45 ° C / 30 minutes.
The underlying insulating layer made of the resin composition in which the inorganic filler was not dispersed was formed. Next, the resin varnish containing the inorganic filler used in Example 1 was applied onto the underlying insulating layer with a curtain coater, and then 120 ° C./20 minutes + 145.
By performing multi-step heating at 30 ° C./30 minutes, a surface insulating layer having a thickness of 25 μm and made of a resin composition in which an inorganic filler is dispersed was formed. In this way, a two-layer insulating layer was formed on the surface of the core substrate. Then, in the same manner as in Example 1, desmear treatment, surface treatment of the surface of the insulating layer with a hydrogen fluoride-based solution, formation of a plating layer, and evaluation of the adhesion between the plating layer and the insulating layer were performed. Table 2 shows the obtained evaluation results.

【0021】(比較例1)実施例1で使用した無機フィ
ラー入り樹脂ワニスの代わりに、無機フィラーを添加し
ていない樹脂ワニスAのみを使用して絶縁層を形成する
ようにした以外は、実施例1と同様にして絶縁層の形
成、デスミア処理、絶縁層の表面のフッ化水素系溶液に
よる表面処理、メッキ層の形成及びメッキ層と絶縁層の
密着力の評価を行った。得られた評価結果を表2に示
す。
(Comparative Example 1) In place of the resin varnish containing an inorganic filler used in Example 1, only the resin varnish A containing no inorganic filler was used to form the insulating layer. In the same manner as in Example 1, formation of an insulating layer, desmear treatment, surface treatment of the surface of the insulating layer with a hydrogen fluoride-based solution, formation of a plated layer, and evaluation of adhesion between the plated layer and the insulating layer were performed. Table 2 shows the obtained evaluation results.

【0022】[0022]

【表2】 [Table 2]

【0023】[0023]

【発明の効果】本発明では、表面に導体回路を有するコ
ア基板の表面に、フッ化水素系溶液に難溶なマトリック
ス樹脂中に、フッ化水素系溶液に可溶な無機フィラーが
分散している樹脂組成物からなる絶縁層を形成した後、
絶縁層の表面をフッ化水素系溶液で表面処理し、次いで
絶縁層の表面にメッキ層を形成するので、無機フィラー
無添加の樹脂組成物のみを用いて絶縁層を形成した場合
に比べ、絶縁層と導体層との密着力が向上する。従っ
て、本発明によれば、密着力の高い導体回路を備える多
層プリント配線板を製造することが可能になる。
According to the present invention, on the surface of a core substrate having a conductor circuit on its surface, an inorganic filler soluble in a hydrogen fluoride solution is dispersed in a matrix resin which is hardly soluble in the hydrogen fluoride solution. After forming the insulating layer made of the resin composition,
The surface of the insulating layer is surface-treated with a hydrogen fluoride-based solution, and then a plating layer is formed on the surface of the insulating layer. Therefore, compared with the case where the insulating layer is formed only by using the resin composition containing no inorganic filler, the insulating layer is insulated. The adhesion between the layer and the conductor layer is improved. Therefore, according to the present invention, it becomes possible to manufacture a multilayer printed wiring board including a conductor circuit having high adhesion.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施の形態を説明するための断面図
である。
FIG. 1 is a sectional view for explaining an embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1 コア基板 2 導体回路 3a、3b 絶縁層 1 core substrate 2 conductor circuit 3a, 3b insulating layer

───────────────────────────────────────────────────── フロントページの続き (72)発明者 杉山 肇 大阪府門真市大字門真1048番地松下電工株 式会社内 (72)発明者 吉岡 慎悟 大阪府門真市大字門真1048番地松下電工株 式会社内 (72)発明者 池谷 晋一 大阪府門真市大字門真1048番地松下電工株 式会社内 (72)発明者 藤原 弘明 大阪府門真市大字門真1048番地松下電工株 式会社内 (72)発明者 伊藤 克彦 大阪府門真市大字門真1048番地松下電工株 式会社内 (72)発明者 井原 清暁 大阪府門真市大字門真1048番地松下電工株 式会社内 (72)発明者 小川 悟 大阪府門真市大字門真1048番地松下電工株 式会社内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hajime Sugiyama 1048, Kadoma, Kadoma, Osaka Prefecture, Matsushita Electric Works Ltd. (72) Inventor, Shingo Yoshioka, 1048, Kadoma, Kadoma, Osaka Prefecture 72) Inventor Shinichi Ikeya, 1048, Kadoma, Kadoma City, Osaka Prefecture, Matsushita Electric Works Co., Ltd. (72) Hiroaki Fujiwara, 1048, Kadoma, Kadoma, Osaka Prefecture Matsushita Electric Works Co., Ltd. (72) Inventor, Katsuhiko Ito, Osaka Prefecture 1048 Kadoma, Kadoma City, Matsushita Electric Works Co., Ltd. (72) Inventor, Kiyoaki Ihara, 1048 Kadoma, Kadoma City, Osaka Prefecture Osaka, Ltd. (72), Satoru Ogawa, 1048 Kadoma, Kadoma City, Osaka Matsushita Denko stock company

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 表面に導体回路を有するコア基板の前記
表面に、フッ化水素系溶液に難溶なマトリックス樹脂中
に、フッ化水素系溶液に可溶な無機フィラーが分散して
いる樹脂組成物からなる絶縁層を形成した後、前記絶縁
層にレーザーで孔あけし、次いで孔の壁面を含む絶縁層
の表面をフッ化水素系溶液で表面処理し、次いで孔の壁
面を含む絶縁層の表面にメッキ層を形成し、次いでこの
メッキ層に所定の導体回路を形成することを特徴とする
多層プリント配線板の製造方法。
1. A resin composition in which an inorganic filler soluble in a hydrogen fluoride-based solution is dispersed in a matrix resin which is hardly soluble in the hydrogen fluoride-based solution, on the surface of a core substrate having a conductor circuit on the surface. After forming an insulating layer made of a material, the insulating layer is perforated with a laser, then the surface of the insulating layer including the wall surface of the hole is surface-treated with a hydrogen fluoride-based solution, and then the insulating layer including the wall surface of the hole is formed. A method for manufacturing a multilayer printed wiring board, comprising forming a plating layer on the surface and then forming a predetermined conductor circuit on the plating layer.
【請求項2】 フッ化水素系溶液がフッ化水素アンモニ
ウム又はフッ化水素を含有する溶液であることを特徴と
する請求項1記載の多層プリント配線板の製造方法。
2. The method for producing a multilayer printed wiring board according to claim 1, wherein the hydrogen fluoride-based solution is a solution containing ammonium hydrogen fluoride or hydrogen fluoride.
【請求項3】 コア基板の表面に形成する絶縁層が2層
からなっていて、コア基板の表面に接する側の絶縁層の
無機フィラー含有割合がコア基板の表面から遠い側の絶
縁層の無機フィラー含有割合よりも低いことを特徴とす
る請求項1又は請求項2記載の多層プリント配線板の製
造方法。
3. The insulating layer formed on the surface of the core substrate is composed of two layers, and the inorganic filler content of the insulating layer on the side in contact with the surface of the core substrate is the inorganic filler on the side far from the surface of the core substrate. The method for producing a multilayer printed wiring board according to claim 1 or 2, wherein the content is lower than the filler content.
【請求項4】 無機フィラーがマイカ又はシリカである
ことを特徴とする請求項1から請求項3までのいずれか
に記載の多層プリント配線板の製造方法。
4. The method for producing a multilayer printed wiring board according to any one of claims 1 to 3, wherein the inorganic filler is mica or silica.
JP3183496A 1996-02-20 1996-02-20 Manufacture of multilayered printed-wiring board Pending JPH09232756A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3183496A JPH09232756A (en) 1996-02-20 1996-02-20 Manufacture of multilayered printed-wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3183496A JPH09232756A (en) 1996-02-20 1996-02-20 Manufacture of multilayered printed-wiring board

Publications (1)

Publication Number Publication Date
JPH09232756A true JPH09232756A (en) 1997-09-05

Family

ID=12342106

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3183496A Pending JPH09232756A (en) 1996-02-20 1996-02-20 Manufacture of multilayered printed-wiring board

Country Status (1)

Country Link
JP (1) JPH09232756A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000068642A (en) * 1998-08-25 2000-03-03 Fujitsu Ltd Manufacture of multilayer circuit board
JP2007067217A (en) * 2005-08-31 2007-03-15 Sanyo Electric Co Ltd Circuit device and its manufacturing method
CN104039071A (en) * 2013-03-08 2014-09-10 揖斐电株式会社 Wiring Board And Method For Manufacturing The Same

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000068642A (en) * 1998-08-25 2000-03-03 Fujitsu Ltd Manufacture of multilayer circuit board
JP2007067217A (en) * 2005-08-31 2007-03-15 Sanyo Electric Co Ltd Circuit device and its manufacturing method
CN104039071A (en) * 2013-03-08 2014-09-10 揖斐电株式会社 Wiring Board And Method For Manufacturing The Same
US9538642B2 (en) 2013-03-08 2017-01-03 Ibiden Co., Ltd. Wiring board and method for manufacturing the same

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