JPH09232536A - Manufacture of semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve reliability of a ferroelectric capacitor without causing any increase in contact resistance or wiring resistance, by forming a second interlayer insulating film, opening a contact hole, and then performing annealing in a non-oxygen atmosphere. SOLUTION: After a contact hole 13 in a second interlayer insulating film 10 is etched, annealing is performed in a non-oxygen atmosphere. The annealing temperature is preferably not lower than 400 deg.C and not higher than 800 deg.C. The non-oxygen atmosphere is preferably a vacuum state, a nitrogen atmosphere, or an inert gas atmosphere, such as, Ar. Such atmosphere is used for the purpose of preventing secondary reaction between the atmosphere gas and the contact aperture or the ferroelectric material. A wiring layer is formed after this annealing. Thus, the leak current of the capacitor is reduced and reliability of the memory cell is improved. Also, the quantity of charges readable from the capacitor is increased and the read margin is increased.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor memory device, and more particularly to a method for manufacturing a semiconductor memory device using a ferroelectric capacitor as a charge storage capacitor.

[0002]

_2. Description of the Related Art Conventionally, SrBi ₂ Ta ₂ O ₉ , Pb has been used.
Non-volatile semiconductor memories using ferroelectrics such as (Zr, Ti) O ₃ and (Ba, Sr) TiO ₃ and dynamic random access memories (DRAM) have been researched and developed. These ferroelectrics are used as thin film capacitors that store charges. FIG. 6 is an example of a memory cell of a non-volatile semiconductor memory using a ferroelectric capacitor.
This memory cell comprises a ferroelectric capacitor 25 and a selection transistor 24 connected to one electrode of the capacitor 25.
Consists of. FIG. 7 shows an example of a manufacturing process of a memory having such a memory cell. First, as shown in FIG. 7A, the transistors of the memory cell portion and the peripheral circuit portion are formed by a normal LSI process. Next, FIG.
As described above, after the first interlayer insulating film 6, the lower electrode 7 of the ferroelectric capacitor, the ferroelectric layer 8, and the upper electrode layer 9 are sequentially formed,
The upper electrode layer 9, the ferroelectric layer 8 and the lower electrode layer 7 are processed by etching to form a capacitor. Next, as shown in FIG. 7C, the second interlayer insulating film 10 is formed, and the contact hole 13 is formed.
Open. Next, as shown in FIG. 7D, the wiring layer 14 of Al or the like is formed and etched. A sol-gel method, a CVD method, and a sputtering method have been developed as a method for manufacturing a ferroelectric thin film. The ferroelectric thin film is manufactured by these manufacturing methods in an atmosphere containing oxygen or oxygen because the ferroelectric is an oxide. This is because when oxygen deficiency occurs in a ferroelectric substance, for example, December 1990, Journal of Applied Physics, 68, 5783 (J.
own of Applied Physic
s, Vol. 68, p. 5783, 1990), which causes deterioration of electrical characteristics such as increase of leak current. Also, for example, April, 1990, Materials Research Society Symposium Proceedings, No. 200, p. 243 (Materiali).
ars Research Society Symp
osm Proceedings, Vol. 20
0, p. 243, April, 1990), it is also common practice to improve the electrical characteristics by annealing in a oxygen atmosphere after forming the ferroelectric thin film.

[0003]

However, when a memory using a ferroelectric capacitor is manufactured by the method described above, there are the following problems.
First, the electrical characteristics of the ferroelectric thin film are significantly deteriorated by a plurality of steps after forming the ferroelectric capacitor. FIG. 8 shows the IV characteristics of the capacitor after forming the capacitor (FIG. 8A) and after opening the contact hole (FIG. 8B) when using SrBi ₂ Ta ₂ O ₉ as the ferroelectric substance. . As described above, the leakage current is significantly increased after the contact hole is opened as compared with after the capacitor is formed. This is because the ferroelectric substance deteriorated due to the formation of the second interlayer insulating film and the contact hole etching process. In order to avoid the characteristics of the ferroelectric capacitor thus deteriorated, it is conceivable to anneal in oxygen as in the ferroelectric thin film forming method after the deterioration in the above steps. However, when annealing is performed in an atmosphere containing oxygen, there are the following problems. That is, first, after etching the contact hole, the Si substrate diffusion layer, polysilicon, silicide, etc. connected to the wiring are exposed. If annealing is performed in an oxygen atmosphere in such a state, the diffusion layer, polysilicon, silicide, etc. are oxidized and the contact resistance increases. In extreme cases, it will completely insulate. Secondly, if annealing is performed in an oxygen atmosphere after forming a wiring layer of Al or the like, the wiring metal such as Al is oxidized and the wiring resistance increases. There is also a problem that the fine shape changes due to the flow of Al.

An object of the present invention is to provide a method for manufacturing a semiconductor memory device with high yield, which improves the reliability of a ferroelectric capacitor without increasing the contact resistance and wiring resistance as described above. is there.

[0005]

In order to solve the above-mentioned problems, in the present invention, annealing is performed in a non-oxygen atmosphere after forming a second interlayer insulating film and opening a contact hole.

By performing the annealing in a non-oxygen atmosphere, problems such as oxidation of the contact hole opening and oxidation of the wiring layer do not occur, and the characteristics of the ferroelectric substance can be improved. Further, since the ferroelectric capacitor is covered with the second interlayer film, even if the ferroelectric capacitor is annealed in a non-oxygen atmosphere, there is no deterioration caused by oxygen defects.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a first embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a cross-sectional view after etching the contact hole 13 of the second interlayer insulating film 10. After that, annealing is performed in a non-oxygen atmosphere. 4 as annealing temperature
The temperature is preferably 00 ° C or higher and 800 ° C or lower. This is because the effect of annealing is small at 400 ° C. or lower, and the deterioration of the ferroelectric or the transistor due to the reaction between the second interlayer insulating film and the ferroelectric is caused at 800 ° C. or higher. The non-oxygen atmosphere is preferably vacuum, nitrogen atmosphere, or inert gas atmosphere such as Ar. This is because in these atmospheres, a secondary reaction between the atmospheric gas and the contact openings or the ferroelectric is not caused. After performing this annealing, a wiring layer is formed.

Next, a second embodiment of the present invention will be described with reference to the drawings.

FIG. 2 is a cross-sectional view after etching the contact hole 13 of the second interlayer insulating film 10 to form the barrier metal layer 12. After that, annealing is performed in a non-oxygen atmosphere as in the first embodiment. Ti, TiN or the like is used as the barrier metal layer. Since these barrier metals have high melting points, there is no problem that their shapes change even if they are annealed at a high temperature.

Next, a third embodiment of the present invention will be described with reference to the drawings.

FIG. 3 is a cross-sectional view after etching the contact hole 13 of the second interlayer insulating film 10 in the case where a stack type capacitor, which is generally used in DRAM as a memory cell structure, is used unlike the first embodiment. It is a figure. In this case, the plate line serves as the upper electrode 9 of the ferroelectric capacitor, and the contact hole 13 of the second interlayer insulating film 10 does not exist in the memory cell portion, but the contact hole 13 in the peripheral circuit portion.
To form After etching the contact hole 13 of the second interlayer insulating film 10 as described above, annealing is performed in a non-oxygen atmosphere as in the first embodiment.

[0013]

Embodiment An embodiment of the present invention will be described with reference to FIG. SrBi ₂ Ta ₂ O ₉ was used as the ferroelectric layer, Pt was used as the upper and lower electrodes, and a SiO ₂ sputtered film was used as the second interlayer insulating film. After opening the contact holes by dry etching, in N ₂ at 500 ° C. or 800 ° C., 5 mi
n annealed. FIG. 4A is a current-voltage diagram of the capacitor before annealing, and FIGS.
FIG. 7 is a current-voltage diagram after annealing at 800 ° C. and 800 ° C. As shown in FIG. 4, the leakage current of the capacitor was significantly reduced by the annealing. FIG. 5 shows before annealing and 500 ° C.
The measured value of 2Pr after annealing is shown. 2P by annealing
The r was increased and the variation was decreased. Since the signal charge amount of the memory cell in the ferroelectric non-volatile memory is proportional to 2Pr, the read margin is increased by annealing and the variation in the read charge between the memory cells is also reduced.

[0014]

As described above, according to the present invention, the following effects can be obtained.

As a first effect, the leakage current of the capacitor is reduced, so that the reliability of the memory cell is improved.

As a second effect, the amount of charge that can be read from the capacitor is increased and the read margin is increased.

As a third effect, the variation in capacitor characteristics is reduced, so that the yield is improved.

As a fourth effect, the cost per memory chip can be reduced. The reason is that the cell area can be reduced because the capacitor area can be reduced by increasing the amount of charge that can be read from the capacitor.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a semiconductor memory device showing a first embodiment of the present invention.

FIG. 2 is a cross-sectional view of a semiconductor memory device showing a second embodiment of the present invention.

FIG. 3 is a cross-sectional view of a semiconductor memory device showing a third embodiment of the present invention.

FIG. 4 is a current-voltage diagram of a ferroelectric capacitor according to an embodiment of the present invention.

FIG. 5 shows a ferroelectric capacitor 2 according to an embodiment of the present invention.
It is a distribution diagram of the measured value of Pr.

FIG. 6 is a circuit diagram showing a memory cell of a nonvolatile semiconductor memory using a ferroelectric capacitor.

FIG. 7 is a manufacturing process diagram of a nonvolatile semiconductor memory using a ferroelectric capacitor.

8 is a diagram illustrating a current of a ferroelectric capacitor according to the process of FIG.
Voltage diagram.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Inter-element isolation oxide film 3 Gate oxide film 4 Gate electrode 5 Impurity diffusion layer 6 First interlayer insulating film 7 Lower electrode layer 8 Ferroelectric layer 9 Upper electrode layer 10 Second interlayer insulating film 11 Contact plug 12 Wiring barrier metal layer 13 Contact hole 14 Wiring layer 21 Word line 22 Plate line 23 Bit line 24 Select transistor 25 Ferroelectric capacitor

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification number Agency reference number FI Technical indication location H01L 21/8247 29/788 29/792

Claims (2)

[Claims] 1. A method of manufacturing a semiconductor memory device using a ferroelectric capacitor as a charge storage capacitor, wherein an interlayer insulating film covering the ferroelectric capacitor is formed, and then the interlayer insulating film is etched to form a contact hole. A method of manufacturing a semiconductor memory device, comprising a step of annealing in a non-oxygen atmosphere after the step of opening the. 2. The method of manufacturing a semiconductor memory device according to claim 1, further comprising a step of annealing in a non-oxygen atmosphere after the step of forming the contact hole and thereafter forming a wiring barrier metal.