JPH09232431A - Method for forming connection hole of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To surely prevent degradation in breakdown voltage and occurrence of short-circuiting between a conductor area and a connection hole formed on a substrate. SOLUTION: Relating to a semiconductor device provided with an insulation layer 20 which is formed on a conductor area 15 formed on a substrate 10, a connection hole 27 is formed on the insulation layer 20 above the conductor area 15. Here, (a) a process wherein the etching speed of the surface of the insulation layer 20 except for the part where the connection hole 27 is formed is made slower than that of the insulation layer of the part where a connection hole is formed, (b) a process wherein such part of the insulation layer 20 as where the connection hole 27 is formed is removed, are contained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a connection hole in an insulating layer above a conductor region in a semiconductor device having an insulating layer formed on a conductor region formed on a substrate.

[0002]

2. Description of the Related Art With the miniaturization of semiconductor elements, a self-aligned contact hole forming technique which can eliminate a design margin of a photomask due to misalignment generated in a contact hole (connection hole) forming process has become important. There is. Also,
In order to reduce the size of the semiconductor element, as shown in a schematic partial cross-sectional view of FIG. 13, a contact hole is formed with a minimum size, and the contact hole is perpendicular to a conductive layer (for example, a gate electrode) below. Techniques for forming contact holes so that they overlap each other in the same direction have also been developed. In particular, in SRAMs, DRAMs, or semiconductor devices equipped with these memory elements, it is necessary to form self-aligned contact holes because it is desired to reduce the element area as much as possible.

An outline of a conventional method for forming a self-aligned contact hole will be described below with reference to FIGS.

[Step-10] First, after forming the gate insulating film 11 on the surface of the silicon semiconductor substrate 10, the gate electrode 12 having a polycide structure is formed. An offset oxide film 13 made of SiO ₂ is formed on the upper surface of the gate electrode 12. After that, by performing ion implantation of impurities, the low-concentration impurity regions 1 for the LDD structure are formed.
4 is formed, and then an insulating layer 100 made of, for example, SiO ₂ is formed on the entire surface by a CVD method (see FIG. 11A).

[Step-20] Next, the insulating layer 100 is etched back to form a gate side wall 101 made of SiO _{2 on} the side wall of the gate electrode 12 including the side wall of the offset oxide film 13. After that, impurities are ion-implanted into the silicon semiconductor substrate 10 to form the source / drain regions 15 (see FIG. 11B).

[Step-20] Next, an etching stopper layer 22 made of silicon nitride (SiN) is formed on the entire surface by CV.
After being deposited by the D method (see FIG. 11C), the second insulating layer 102 made of, for example, silicon oxide (SiO ₂ ).
Are formed on the etching stopper layer 22, and the second insulating layer 102 is planarized. Then, the second insulating layer 1
A resist 24 is applied onto the resist 02, and an opening is formed in the resist 24 above the portion where the contact hole is to be formed by using a photolithography technique. Then, using the patterned resist 24 as an etching mask, the second insulating layer 102 is selectively etched to form an opening 25 in the second insulating layer 102. The etching of the second insulating layer 102 is stopped by the etching stopper layer 22. This state is shown in a schematic partial cross-sectional view in FIG. In order to reduce the size of the semiconductor element, the opening 25 is formed so that the opening 25 vertically overlaps the lower gate electrode 12. In the case where the center of the opening 25 does not coincide with the center of the source / drain region 15 and the opening 25 is formed such that the opening 25 vertically overlaps the gate electrode 12 below. is there. Such a condition
It is caused by misalignment in the photolithography process when forming the opening 25.

[Step-30] Next, the etching stopper layer 22 at the bottom of the opening 25 is etched to expose the source / drain regions 15 at the bottom of the opening 25 (see FIG. 12B).

[Step-40] Finally, the second insulating layer 10 is formed.
A wiring layer 28 is formed on the wiring 2. The wiring layer 28 extends from the side wall of the opening 25 to the bottom of the opening 25 (see FIG. 13). As a result, the source / drain region 15 exposed at the bottom of the opening 25 is electrically connected to the wiring layer 28 on the second insulating layer 102, and the contact hole (connection hole) 27 is completed.

[0009]

[Problem to be Solved by the Invention] [Step-20]
In the step of etching back the insulating layer 100 to form the gate sidewall 101, the offset oxide film 13
The gate sidewall 101 is formed in a state where the insulating layer 100 in the shoulder portion of the offset oxide film 13 is thin due to the high etching rate in the shoulder portion of
The upper portion of the offset oxide film 13 is also etched (see FIG. 1).
1 (B)). Incidentally, when such a phenomenon does not occur and the insulating layer 100 is ideally etched back to form the gate sidewall, the cross-sectional shapes of the offset oxide film 13 and the gate sidewall are shown in FIG. ) Is indicated by a dotted line.

Further, in the above [Step-30],
When etching the etching stopper layer 22, the opening 25 is generally formed by the microloading effect.
The etching rate of the etching stopper layer 22 at the bottom of the is lower than the etching rates of other portions (for example, the etching stopper layer on the gate sidewall 101). Therefore, in order to completely remove the etching stopper layer 22 at the bottom of the opening 25, it is necessary to overetch.

In the above [Step-20], the insulating layer 100 on the shoulder portion of the offset oxide film 13 is thinned, and the upper portion of the offset oxide film 13 is etched. As a result of the over-etching, the offset oxide film 13 and the gate sidewall 101 are considerably etched. Incidentally, in order to clearly show this state, such a portion is shown by being surrounded by a circle in FIG. As a result, FIG.
As shown in, the breakdown voltage between the gate electrode 12 and the connection hole 27 deteriorates, and in the worst case, the gate electrode 12 and the connection hole 27 are short-circuited.

In order to avoid such a problem, when the amount of over-etching of the portion of the etching stopper layer 22 other than the bottom portion of the opening is reduced, the etching stopper layer 22 remains at the bottom of the opening 25. . S
The etching stopper layer made of iN is an insulating material. Therefore, if the etching stopper layer 22 remains at the bottom of the opening 25, the source / drain region 15 and the wiring layer 28 are not electrically connected.

Therefore, an object of the present invention is to provide a method of forming a connection hole in a semiconductor device, which can surely prevent a breakdown voltage from being deteriorated and a short circuit from occurring between a conductor region formed on a substrate and a connection hole. Especially.

[0014]

The above object is a method of forming a connection hole in an insulating layer above a conductor region in a semiconductor device having an insulating layer formed on a conductor region formed in a base. And (a) a step of making the etching rate of the surface of the insulating layer excluding the portion where the connection hole is to be formed slower than the etching rate of the insulating layer where the connection hole is to be formed; ) A step of removing an insulating layer in a portion where a connection hole is to be formed, can be achieved by the method for forming a connection hole in a semiconductor device of the present invention.

Incidentally, in the step (a), the region of the insulating layer to be subjected to the treatment for slowing down the etching rate does not have to be strictly the part other than the part where the connection hole is to be formed, and the connection hole should be formed. It may penetrate into the insulating layer.

In the method of forming a contact hole in a semiconductor device according to the present invention, the treatment for reducing the etching rate is preferably a silicon ion implantation method. As described above, by performing ion implantation into the insulating layer, the insulating layer becomes in a silicon-rich state, and it is possible to increase the etching selection ratio with respect to the region of the insulating layer in which ion implantation is not performed. In this case, in the step (a), after forming the insulating layer, a resist material is applied to the entire surface and the resist material is etched back to remove the resist material on the region of the insulating layer where ion implantation should be performed. Ion implantation of silicon is preferably performed on the exposed region of the insulating layer. Alternatively or alternatively, in the step (a),
After forming the insulating layer, while rotating the entire constituent material including the insulating layer, by ion-implanting silicon ions into the surface of the insulating layer from an oblique direction, the surface of the insulating layer excluding the portion where the connection hole is to be formed It is also possible to make the etching rate of the insulating film slower than the etching rate of the insulating layer in the portion where the connection hole is to be formed.

In the method of forming a connection hole in a semiconductor device of the present invention, following the step (b), (c) an etching stopper layer is formed on the entire surface, and then a second insulating layer is formed on the etching stopper layer. Forming process, (d)
A step of removing the second insulating layer and the etching stopper layer in the portion where the connection hole is to be formed and forming an opening;
(E) A step of burying a conductive material in the opening to form a connection hole can be further included.

Examples of the combination of the substrate and the conductor region in the present invention include a silicon semiconductor substrate and source / drain regions, a lower insulating layer and a lower wiring layer formed thereon. The connection hole is a general term for a contact hole, a via hole, and a through hole. As a material for forming the insulating layer, SiO ₂ , BPSG, PSG, BSG,
AsSG, PbSG, SbSG, NSG, SOG, LT
O (Low Temperature Oxide, low temperature CVD-SiO ₂ ),
Known insulating materials such as SiN and SiON, or laminated layers of these insulating materials can be used.

The method of forming a connection hole of the present invention can be applied to any semiconductor device. For example, a connection portion with a storage node of SRAM, a connection portion with a capacitor of DRAM, a power supply connection portion of SRAM or DRAM. And the formation of connection holes in the ground connection portion and the like.

In the present invention, since the etching rate of the surface of the insulating layer excluding the portion where the connection hole is to be formed is made slower than the etching rate of the insulating layer where the connection hole is to be formed, the connection hole is formed. When removing the insulating layer in the portion where the contact hole is to be formed, the insulating layer other than the portion where the connection hole is to be formed is less likely to be etched. As a result, for example, it is possible to prevent the insulating layer existing between the gate electrode and the connection hole from being thinned, and it is possible to obtain a connection hole having a desired shape or a shape close to the desired shape. It is possible to reliably prevent the breakdown voltage from being deteriorated and the occurrence of a short circuit between the region and the connection hole.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the invention (hereinafter, referred to as
The present invention will be described based only on the embodiment).

(First Embodiment) In the first embodiment, the process for reducing the etching rate is performed by a silicon ion implantation method. An offset oxide film is formed on the gate electrode. The insulating layer is made of SiO ₂ . Furthermore, the base and the conductor region are respectively composed of the silicon semiconductor substrate and the source / drain regions. Less than,
FIG. 1 is a schematic partial cross-sectional view of a silicon semiconductor substrate or the like.
5A to 5C, a method of forming the connection hole of the semiconductor device according to the first embodiment will be described.

[Step-100] First, after forming the gate insulating film 11 on the surface of the silicon semiconductor substrate 10 by a known method, a polycrystalline silicon layer is deposited on the entire surface by the CVD method, and then the polycrystalline silicon is formed. A tungsten silicide layer is deposited on the layer by sputtering. Then, CVD
An offset oxide film 13 made of SiO ₂ is deposited on the entire surface by the method. Then, the offset oxide film 13, the tungsten silicide layer and the polycrystalline silicon layer are etched by using the photolithography technique and the etching technique to form the gate electrode 12 including the tungsten silicide layer and the polycrystalline silicon layer. The gate electrode 12 has a so-called polycide structure, and the upper surface thereof is made of Si.
An offset oxide film 13 made of O ₂ is formed.
In the figure, the gate electrode 12 is shown as a single layer. After that, ion implantation of impurities is performed to form the low-concentration impurity regions 14 for the LDD structure.

[Step-110] Then, S is formed by the CVD method.
The insulating layer 20 made of iO ₂ is deposited on the entire surface. This state is shown in FIG.

[Step-120] After that, the resist material 21 is applied to the entire surface, and the resist material 21 is etched back under the conditions illustrated below to form the resist material 21 on the region of the insulating layer 20 where ion implantation should be performed. Are removed (see FIG. 1B). Equipment used: Parallel plate etching equipment Gas used: O ₂ = 100 sccm Pressure: 40 Pa RF power: 1 kW (380 kHz) Substrate heating temperature: 0 ° C

[Step-130] The etching rate of the surface of the insulating layer excluding the portion where the connection hole is to be formed is made slower than the etching rate of the insulating layer where the connection hole is to be formed. Specifically, silicon ions are implanted into the exposed region of the insulating layer 20 to make the surface of the exposed region of the insulating layer 20 rich in silicon to form a low etching rate region 20A ((A in FIG. 2). )reference). The direction of ion implantation was substantially perpendicular to the surface of the insulating layer 20. The conditions for ion implantation of silicon are exemplified below. The region of the insulating layer that is subjected to the treatment for reducing the etching rate slightly penetrates not only into the portion where the connection hole is to be formed but also into the portion of the insulating layer where the connection hole is to be formed. Dose amount: 1 × 10 ¹⁵ to 1 × 10 ¹⁷ / cm ² Accelerating voltage: 1 to 20 keV

[Step-140] Next, after removing the resist material 21 using fuming nitric acid, the insulating layer 20 on the silicon semiconductor substrate 10 is etched under the conditions exemplified below. Since the low etching rate region 20A is formed in the insulating layer 20 in [Step-130],
The insulating layer 20 below the region is not etched, and the insulating layer 20 in the portion where the connection hole is to be formed is removed. Equipment used: parallel plate etching equipment Gas used: CHF ₃ / CF ₄ / Ar = 40/40/600 sccm Pressure: 20 Pa RF power: 1.6 kW (380 kHz) Substrate heating temperature: 0 ° C

Thereafter, the exposed silicon semiconductor substrate 10
Impurities are ion-implanted into the substrate, and the ion-implanted impurities are activated to form the source / drain regions 15 (see FIG. 2B).

[Step-150] Next, the etching stopper layer 22 made of SiN is formed on the entire surface by the CVD method under the following conditions (see FIG. 3A). The combination of the materials forming the etching stopper layer 22 and the insulating layer 20 should be the same as the etching stopper layer 22 and the insulating layer 20.
The materials may be made of materials that have an etching selection ratio between and. Equipment used: LPCVD equipment Gas used: SiH ₂ Cl ₂ / NH ₃ / N ₂ = 50/200/200 sccm Pressure: 70 Pa Substrate heating temperature: 760 ° C

[Step-160] After that, a second insulating layer 23 made of BPSG is formed on the etching stopper layer 22 by the CVD method under the following conditions, and then 90
The second insulating layer 23 is subjected to a reflow treatment under the condition of 0 ° C. × 10 minutes to flatten the second insulating layer 23. Gas used: TEOS / TPM / TMB = 50/15/15 sccm and O ₂ = 1 g / min Pressure: Normal pressure Substrate heating temperature: 520 ° C.

Next, a resist 24 is formed on the second insulating layer 23.
2 above the portion where the connection hole is to be formed.
4, an opening is formed by using a photolithography technique.
Then, using the patterned resist 24 as an etching mask, the second insulating layer 23 is selectively etched to form an opening 25 in the second insulating layer 23. The etching of the second insulating layer 23 is stopped by the etching stopper layer 22. The etching conditions for the second insulating layer 23 are exemplified below. This state is shown in a schematic partial cross-sectional view in FIG. As described above, in order to reduce the size of the semiconductor element, the opening 25 is formed so that the connection hole vertically overlaps the lower gate electrode 12. In the case where the center of the opening 25 does not coincide with the center of the source / drain region 15 and the opening 25 is formed such that the opening 25 vertically overlaps the gate electrode 12 below. is there. Such a state is caused by misalignment in the photolithography process when forming the opening 25. Device used: Single wafer type magnetron RIE device Gas used: C ₄ F ₈ / CO / Ar = 8/60 / 200sccm Pressure: 5.3Pa RF power: 1.6kW Susceptor temperature: 20 ° C

[Step-170] Next, the etching stopper layer 22 is etched to form an opening 25 above the source / drain region 15, and the source / drain region 15 is exposed at the bottom of the opening 25 ( (See FIG. 4).
The etching conditions for the etching stopper layer 22 are exemplified below. Since the low etching rate region 20A is formed, it is possible to prevent the offset oxide film 13 and the insulating layer 20 from being significantly etched.
As a result, it is possible to surely prevent the breakdown voltage between the gate electrode 12 and the connection hole from being deteriorated and prevent the gate electrode 12 and the connection hole from being short-circuited. Equipment used: Single wafer type magnetron RIE equipment Gas used: CHF ₃ / O ₂ = 40/10 sccm Pressure: 2.7 Pa RF power: 1.0 kW Susceptor temperature: 20 ° C

[Step-180] After that, the wiring layer 28 made of tungsten silicide is formed on the second insulating layer 23 including the inside of the opening 25 by the CVD method under the following conditions. As a result, the conductive material made of tungsten silicide is embedded in the opening 25 and the connection hole 27 is formed. Gas used: WF ₆ / SiH ₄ / He = 10/1000/360 sccm Pressure: 27 Pa Substrate heating temperature: 360 ° C

(Second Embodiment) In the second embodiment, unlike the first embodiment, an offset oxide film is not formed on the gate electrode. Also in the second embodiment, the process of reducing the etching rate is performed by the ion implantation method of silicon. The insulating layer is made of SiO ₂ .
Furthermore, the base and the conductor region are respectively composed of the silicon semiconductor substrate and the source / drain regions. Hereinafter, a method of forming a connection hole of a semiconductor device according to the second embodiment will be described with reference to FIGS. 6 to 9 which are schematic partial cross-sectional views of a silicon semiconductor substrate and the like.

[Step-200] First, after forming the gate insulating film 11 on the surface of the silicon semiconductor substrate 10 by a known method, a polycrystalline silicon layer 12A is deposited on the entire surface by the CVD method, and then the polycrystalline silicon layer 12A is formed. A tungsten silicide layer 12B is deposited on the silicon layer 12A by a sputtering method. Unlike the first embodiment, the offset oxide film 13 is not deposited. Then, using the photolithography technique and the etching technique, the tungsten silicide layer 12 is formed.
B and the polycrystalline silicon layer 12A are etched to form the tungsten silicide layer 12B and the polycrystalline silicon layer 12
A gate electrode 12 made of A is formed. The gate electrode 12 has a so-called polycide structure. After that, ion implantation of impurities is performed to form the low-concentration impurity regions 14 for the LDD structure.

[Step-210] Then, S is formed by the CVD method.
The insulating layer 20 made of iO ₂ is deposited on the entire surface. This state is shown in FIG.

[Step-220] Then, while rotating the silicon semiconductor substrate 10, silicon ions are ion-implanted into the surface of the insulating layer 20 from an oblique direction (see FIG. 6B). As a result, the surface of the information insulating layer 20 region of the gate electrode 12 is made silicon-rich,
A low etching rate region 20A is formed. Gate electrode 1
Ion implantation is not performed on most of the region of the insulating layer 20 sandwiched between 2 and the gate electrode 12. As a result, the etching rate of the surface of the insulating layer excluding the portion where the connection hole is to be formed can be slower than the etching rate of the insulating layer where the connection hole is to be formed. The conditions for ion implantation of silicon ions can be the same as in [Step-130] of the first embodiment. Here, the region of the insulating layer that is subjected to the treatment for reducing the etching rate slightly penetrates not only into the portion where the connection hole is to be formed but also into the portion of the insulating layer where the connection hole is to be formed.

[Step-230] Next, the insulating layer 20 on the silicon semiconductor substrate 10 is etched under the same conditions as in [Step-140] of the first embodiment. The insulating layer 20 has a low etching rate region 2 in [Step-220].
Since 0A is formed, the insulating layer 20 below the region is not etched, and the insulating layer 20 in the portion where the connection hole is to be formed is removed.

Thereafter, the exposed silicon semiconductor substrate 10
Impurities are ion-implanted into the substrate, and the ion-implanted impurities are activated to form the source / drain regions 15 (see FIG. 7A).

[Step-240] Next, the etching stopper layer 22 made of SiN is formed on the entire surface under the same conditions as in [Step-150] of the first embodiment.

[Step-250] After that, a second insulating layer 23 made of BPSG is formed on the etching stopper layer 22 under the same conditions as in [Step-160] of the first embodiment, and then 900 ° C ×. The second insulating layer 23 under the condition of 10 minutes
Is subjected to a reflow treatment to planarize the second insulating layer 23.

Next, in the same manner as in [Step-160] of the first embodiment, the second insulating layer 23 is selectively etched to form the opening 25 in the second insulating layer 23. The etching of the second insulating layer 23 is performed by etching the etching stopper layer 22.
Stop by. This state is shown in a schematic partial cross-sectional view in FIG.

[Step-260] Subsequently, the etching stopper layer 22 is etched in the same manner as in [Step-170] of the first embodiment to form the opening 25 above the source / drain region 15 ( (See FIG. 8). Since the low etching rate region 20A is formed, it is possible to prevent the insulating layer 20 from being significantly etched. As a result, it is possible to surely prevent the breakdown voltage between the gate electrode 12 and the connection hole from being deteriorated and prevent the gate electrode 12 and the connection hole from being short-circuited.

[Step-270] Then, a conductive material is embedded in the opening 25 to form the connection hole 27 (see FIG. 9). In the second embodiment, tungsten is used as the conductive material. Specifically, first, a Ti layer and then a TiN layer are formed on the entire surface including the inside of the opening 25 by a sputtering method, the TiN layer is annealed, and then a tungsten layer is deposited on the entire surface by a CVD method. . Then, the tungsten layer, the TiN layer, and the Ti layer on the second insulating layer 23 are etched back to complete the connection hole 27 in which the conductive material made of tungsten is embedded in the opening 25. In addition, Ti
The layer is formed for the purpose of reducing the contact resistance between the connection hole 27 and the source / drain region 15 and improving the adhesion of tungsten. Also, the TiN layer is
When tungsten is deposited by the CVD method, it has a function as a barrier layer that prevents the tungsten from entering the source / drain regions 15. The barrier effect of the TiN layer is improved by annealing the TiN layer. Here, in FIG. 9, TiN layer / Ti
The layers were collectively represented by the underlayer 26. The sputtering conditions for the Ti layer and the TiN layer, the annealing treatment conditions for the TiN layer, the tungsten deposition conditions by the CVD method, the tungsten etchback conditions, the chemical etching conditions for the TiN layer / Ti layer, and the sputter etching conditions are illustrated below. Sputtering conditions for Ti layer Target: Ti working gas: Ar = 100 sccm Pressure: 0.4 Pa DC power: 5 kW Substrate heating temperature: 150 ° C Sputtering conditions for TiN layer Target: Ti working gas: N ₂ / Ar = 80/30 sccm pressure : 0.4 Pa DC power: 5 kW Substrate heating temperature: 150 ° C. Annealing condition of TiN layer Atmosphere: Nitrogen gas atmosphere Substrate heating temperature: 450 ° C. Time: 30 minutes Tungsten CVD condition Working gas: WF ₆ / H ₂ / Ar = 75/500/2800
Sccm pressure: 1.1 × 10 ⁴ Pa Substrate heating temperature: 450 ° C. Tungsten etch-back condition Gas used: SF ₆ / Ar / He = 140/110 / 25s
ccm pressure: 32 Pa RF power: 625 W Tungsten over-etching conditions Working gas: SF ₆ / Ar / He = 80/40/25 sccm Pressure: 22 Pa RF power: 250 W TiN layer / Ti layer chemical etching conditions Working gas: Cl ₂ / Ar / He = 30/30/10 sccm Pressure: 2.5 Pa RF power: 350 W Magnetic field: 2 × 10 ⁻³ T TiN layer / Ti layer sputter etching conditions Working gas: Cl ₂ / Ar / He = 10/30/10 sccm Pressure: 5.5Pa RF power: 600W

[Step-280] Finally, the second insulating layer 2
A wiring layer 28 made of Al-1% Si is formed on the wiring layer 3. Therefore, first, a wiring material layer made of Al-1% Si is formed on the second insulating layer 23 including the connection holes 27 by a sputtering method, and then wiring is formed by a photolithography technique and a dry etching technique. The material layer is patterned to obtain the wiring layer 28. The sputtering conditions for the wiring material layer made of Al-1% Si are exemplified below. Sputtering conditions of wiring material layer Target: Al-1% Si Working gas: Ar = 100 sccm Pressure: 0.4 Pa DC power: 5 kW Substrate heating temperature: 150 ° C

In this way, a semiconductor device whose schematic partial sectional view is shown in FIG. 9 can be obtained.

Although the present invention has been described based on the preferred embodiments of the present invention, the present invention is not limited thereto. After forming an insulating film having an etching selection ratio with respect to the insulating layer on the insulating layer formed on the conductor region formed on the substrate, the connection hole is formed by using the photolithography technique and the etching technique. The low etching rate region may be formed by leaving the insulating film on the surface of the insulating layer except the portion to be formed. Embodiment 1
Alternatively, the method of forming the connection hole described in the second embodiment can be applied to the second embodiment or the first embodiment, respectively.

In the embodiment of the invention, the combination of the base and the conductor region is the silicon semiconductor substrate and the source / drain regions, but it is also possible to use the lower insulating layer and the lower wiring layer formed thereon. A schematic partial cross-sectional view of the insulating layer 20 and the like in such a form is shown in FIG. The lower wiring layer 31 corresponding to the conductor region is formed on the lower insulating layer 30 corresponding to the base. An interlayer insulating layer 32 is formed on the lower wiring layer 31 and the lower insulating layer 30.

An intermediate wiring layer 33 is formed on the interlayer insulating layer 32, and the surface of the intermediate wiring layer 33 is covered with the insulating layer 2.
0 is covered. Insulating layer 20 above intermediate wiring layer 33
A low etching rate region 20A is formed in the.
The etching stopper layer 22 is formed on the interlayer insulating layer 32 including the insulating layer 20, and the second insulating layer 23 is formed thereon. A wiring layer 28 is provided on the second insulating layer 23.

Connection holes 27 are formed between the intermediate wiring layers 33. The connection hole 27 extends downward from the wiring layer 28 in the second insulating layer 23 and the interlayer insulating layer 32.
It extends inside and reaches the lower wiring layer 31.

Since such a structure shown in FIG. 10 can be obtained by a method substantially similar to that of the first and second embodiments, detailed description thereof will be omitted.

The formation of the Ti layer which constitutes the underlayer 26 is not limited to the sputtering method, but may be performed by the CVD method, for example. The conditions for forming the metal layer made of Ti by the ECR-CVD method are illustrated below. ECR-CVD conditions for Ti Working gas: TiCl ₄ / H ₂ = 10/50 sccm Microwave power: 2.18 kW Substrate heating temperature: 420 ° C Pressure: 0.12 Pa

The TiN layer forming the underlayer 26 is made of C
It can also be formed by the VD method. The conditions for forming TiN by the ECR-CVD method are illustrated below. ECR-CVD conditions for TiN Working gas: TiCl ₄ / H ₂ / N ₂ = 20/26/8 sccm Microwave power: 2.8 kW Substrate RF bias: -50 W Substrate heating temperature: 420 ° C Pressure: 0.12 Pa

In the second embodiment, the connection hole is formed by the so-called blanket tungsten CVD method. Alternatively, a copper layer may be formed by a CVD method to fill the opening with a refractory metal material made of copper to form a connection hole. The conditions for forming the copper layer by the CVD method are illustrated below. Note that HFA is an abbreviation for hexafluoroacetylacetonate. Copper CVD film forming conditions Gas used: Cu (HFA) ₂ / H ₂ = 10/1000 sccm Pressure: 2.6 × 10 ³ Pa Substrate heating temperature: 350 ° C. Power: 500 W

Alternatively, in some cases, the opening 25
A connection hole made of polycrystalline silicon may be formed therein, or the opening 25 may be filled with a wiring material layer also serving as a conductive material. In the latter case, in order to surely fill the inside of the opening 25 with the wiring material layer, Ti for reducing the contact resistance and improving the wettability is formed on the second insulating layer 23 including the inside of the opening 25. The layer is formed by the sputtering method, and further
A TiN layer that functions as a barrier layer is formed by sputtering. After that, the substrate heating temperature is set to about 500 ° C. under the so-called high temperature aluminum sputtering method ([step-190] sputtering condition of the wiring material layer) and the second insulating layer 2 is formed.
3 is a method in which the aluminum-based alloy deposited on 3 is made into a fluid state and the opening 25 is filled with the aluminum-based alloy),
In the aluminum reflow method ([step-190], the substrate heating temperature was set to 150 under the sputtering condition of the wiring material layer.
After the aluminum-based alloy is deposited on the second insulating layer 23 at about ° C, the substrate is heated to about 500 ° C to bring the aluminum-based alloy on the second insulating layer 23 into a fluid state. As a result, the opening 25 is filled with an aluminum-based alloy) or the high-pressure reflow method (aluminum reflow method) is used to deposit the aluminum-based alloy deposited on the second insulating layer 23 and then 10 ⁶ P
The second insulating layer 2 is heated by heating the substrate in a high pressure atmosphere of about a.
A connection hole made of an aluminum-based alloy can also be formed in the opening 25 by adopting a method of filling the inside of the opening 25 with the aluminum-based alloy by bringing the aluminum-based alloy on 3 into a fluid state. .

In the second embodiment, Al--Si is used as the aluminum-based alloy forming the wiring layer. Instead of this, pure aluminum or Al--Cu,
Various aluminum alloys such as Al-Si-Cu, Al-Ge, and Al-Si-Ge can also be used.

In the first and second embodiments, the bottom portion of the opening 25 is provided for the purpose of reducing the contact resistance.
For example, a metal silicide layer made of titanium silicide may be formed. In this case, [Step-
170] or [Step-260] of the second embodiment, the following steps may be performed. [Step-170] of the first embodiment or [Step-26] of the second embodiment.
0] to 0.5 nm to 5 nm at the bottom of the opening 25.
The etching stopper layer 22 having a thickness of nm may remain. In this case, the remaining etching stopper layer 22 is made silicon-rich, and the etching left on the bottom of the opening 25 is promoted in order to promote the reaction between the metal forming the metal layer and the silicon of the silicon semiconductor substrate 10. It is preferable to implant silicon ions into the stopper layer 22 under the following conditions. Dose amount: 1 × 10 ¹² to 1 × 10 ¹⁸ / cm ² Energy: 10 to 100 keV

First, a metal layer (for example, a Ti layer) is formed on the entire surface including the inside of the opening 25 by the above-described sputtering method or CVD.
Form by the method. Incidentally, as the metal layer, Zr,
It can be composed of a metal selected from the group consisting of Hf, Ta, Mo, W, Co, Ni, Pt, and Pd.

Next, heat treatment is performed to react the metal forming the metal layer at the bottom of the opening 25 with the silicon of the silicon semiconductor substrate 10, and the metal silicide layer (titanium silicide layer) is formed at the bottom of the opening 25. ) Is formed. Therefore, first, the first RTA at 650 ° C. for 30 seconds in an inert gas atmosphere such as Ar gas atmosphere.
(Rapid Thermal Annealing) processing is performed. Accordingly, when the etching stopper layer 22 remains at the bottom of the opening 25, the metal forming the metal layer at the bottom of the opening 25 and the silicon of the silicon semiconductor substrate 10 are interposed via the etching stopper layer 22. React with each other to form a metal silicide layer at the bottom of the opening 25.

Then, the unreacted metal layer is removed. Specifically, the metal layer made of unreacted Ti on the second insulating layer 23 or on the side wall of the opening 25 is formed by using ammonia hydrogen peroxide (NH ₄ OH / H ₂ O ₂ / H ₂ O). To remove.

After that, a _second RTA treatment is performed at 900 ° C. for 30 seconds in an inert gas atmosphere such as N ₂ gas atmosphere. By performing such a secondary RTA treatment, the crystal structure of the metal silicide layer becomes more stable.

After forming a metal layer on the silicon oxide film formed on the silicon semiconductor substrate, heat treatment is performed to separate the metal forming the metal layer and the silicon of the silicon semiconductor substrate into a silicon oxide film. React through
The technique for forming the metal silicide layer is, for example, “New Sil
icidation Technology by SITOX (Silicidation Throug
h Oxide) and Its Impact on Sub-half Micron MOS Dev
ices ", H. Sumi, et al., 1990 IEDM, pp 249-252.

[0063]

According to the present invention, since the low etching rate region is formed on the surface of the insulating layer except the portion where the connection hole is to be formed, the etching of the offset oxide film and the insulating layer is suppressed during the etching of the etching stopper layer. The breakdown voltage between the gate electrode and the connection hole may be deteriorated,
It is possible to reliably prevent a short circuit between the gate electrode and the connection hole.

[Brief description of drawings]

FIG. 1 is a schematic partial cross-sectional view of a silicon semiconductor substrate or the like for explaining a method of forming a connection hole in a semiconductor device according to a first embodiment of the invention.

FIG. 2 is a schematic partial cross-sectional view of a silicon semiconductor substrate or the like for explaining a method of forming a connection hole in the semiconductor device of the first embodiment of the invention, following FIG. 1;

FIG. 3 is a schematic partial cross-sectional view of the silicon semiconductor substrate or the like for explaining the method of forming the connection holes in the semiconductor device of the first embodiment of the invention, following FIG. 2;

FIG. 4 is a schematic partial cross-sectional view of the silicon semiconductor substrate or the like for explaining the method of forming the connection hole in the semiconductor device of the first embodiment of the invention, following FIG. 3;

FIG. 5 is a schematic partial cross-sectional view of the silicon semiconductor substrate or the like for explaining the method of forming the connection holes in the semiconductor device of the first embodiment of the invention, following FIG. 4;

FIG. 6 is a schematic partial cross-sectional view of a silicon semiconductor substrate or the like for explaining a method of forming a connection hole in a semiconductor device according to a second embodiment of the invention.

FIG. 7 is a schematic partial cross-sectional view of the silicon semiconductor substrate or the like for explaining the method of forming the connection hole in the semiconductor device of the second embodiment of the invention, following FIG. 6;

FIG. 8 is a schematic partial cross-sectional view of the silicon semiconductor substrate or the like for explaining the method of forming the connection hole in the semiconductor device of the second embodiment of the invention, following FIG. 7;

9 is a schematic partial cross-sectional view of the silicon semiconductor substrate or the like for explaining the method of forming the connection hole in the semiconductor device of the second embodiment of the invention, following FIG. 8;

FIG. 10 is a schematic partial cross-sectional view of a semiconductor device for explaining the structure of another semiconductor device obtained by the method of forming a connection hole in the semiconductor device of the present invention.

FIG. 11 is a schematic partial cross-sectional view of a silicon semiconductor substrate or the like for explaining a conventional method for forming a self-aligned contact hole.

12 is a schematic partial cross-sectional view of a silicon semiconductor substrate or the like for explaining a conventional method for forming a self-aligned contact hole, following FIG.

FIG. 13 is a schematic partial cross-sectional view of a silicon semiconductor substrate or the like for explaining the conventional method for forming a self-aligned contact hole, following FIG. 12;

[Explanation of symbols]

10 ... Silicon semiconductor substrate, 11 ... Gate insulating film, 12 ... Gate electrode, 13 ... Offset oxide film, 14 ... Low concentration impurity region, 15 ... Source ...
Drain region, 20 ... Insulating layer, 20A ... Low etching rate region, 21 ... Resist material, 22 ...
Etching stopper layer, 23 ... Second insulating layer, 2
4 ... Resist, 25 ... Opening part, 26 ... Underlayer, 27 ... Connection hole, 28 ... Wiring layer

Claims (4)

[Claims] 1. A method of forming a connection hole in an insulating layer above a conductor region in a semiconductor device provided with an insulating layer formed on a conductor region formed in a base, comprising: (a) connection hole A step of making the etching rate of the surface of the insulating layer excluding the portion where the connection hole is to be formed slower than the etching rate of the insulating layer of the portion where the connection hole is to be formed; A method of forming a connection hole in a semiconductor device, comprising the step of removing an insulating layer. 2. The method for forming a connection hole in a semiconductor device according to claim 1, wherein the treatment for reducing the etching rate is performed by a silicon ion implantation method. 3. In the step (a), after the insulating layer is formed, a resist material is applied on the entire surface, the resist material is etched back, and the resist material on the region of the insulating layer where ion implantation is to be performed is removed. The method of forming a connection hole in a semiconductor device according to claim 2, further comprising ion-implanting silicon into the exposed region of the insulating layer. 4. Following the step (b), (c) a step of forming an etching stopper layer on the entire surface and then forming a second insulating layer on the etching stopper layer, and (d) forming a connection hole. The method further includes: a step of removing the second insulating layer and the etching stopper layer at a portion to be formed to form an opening; and (e) a step of burying a conductive material in the opening to form a connection hole. The method of forming a connection hole in a semiconductor device according to claim 1, wherein