JPH09231161A - 直接メモリ・アクセス(dma)システム - Google Patents

直接メモリ・アクセス(dma)システム

Info

Publication number
JPH09231161A
JPH09231161A JP8307546A JP30754696A JPH09231161A JP H09231161 A JPH09231161 A JP H09231161A JP 8307546 A JP8307546 A JP 8307546A JP 30754696 A JP30754696 A JP 30754696A JP H09231161 A JPH09231161 A JP H09231161A
Authority
JP
Japan
Prior art keywords
cache
entry
list
mru
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8307546A
Other languages
English (en)
Japanese (ja)
Other versions
JPH09231161A5 (enExample
Inventor
Denny E Gentry
デントン・イー・ジェントリー
Rasoul M Oskouy
ラソウル・エム・オスコウィ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sun Microsystems Inc
Original Assignee
Sun Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sun Microsystems Inc filed Critical Sun Microsystems Inc
Publication of JPH09231161A publication Critical patent/JPH09231161A/ja
Publication of JPH09231161A5 publication Critical patent/JPH09231161A5/ja
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/20Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12Replacement control
    • G06F12/121Replacement control using replacement algorithms
    • G06F12/123Replacement control using replacement algorithms with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10Program control for peripheral devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Bus Control (AREA)
JP8307546A 1995-11-03 1996-11-05 直接メモリ・アクセス(dma)システム Pending JPH09231161A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/553041 1995-11-03
US08/553,041 US5875352A (en) 1995-11-03 1995-11-03 Method and apparatus for multiple channel direct memory access control

Publications (2)

Publication Number Publication Date
JPH09231161A true JPH09231161A (ja) 1997-09-05
JPH09231161A5 JPH09231161A5 (enExample) 2004-11-04

Family

ID=24207871

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8307546A Pending JPH09231161A (ja) 1995-11-03 1996-11-05 直接メモリ・アクセス(dma)システム

Country Status (3)

Country Link
US (1) US5875352A (enExample)
EP (1) EP0772131A3 (enExample)
JP (1) JPH09231161A (enExample)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002530778A (ja) * 1998-11-24 2002-09-17 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド 複数の仮想ダイレクトメモリアクセスチャネルをサポートするためのダイレクトメモリアクセスエンジン
JP2007080037A (ja) * 2005-09-15 2007-03-29 Fujitsu Ltd Dma転送システム
JP2007249816A (ja) * 2006-03-17 2007-09-27 Ricoh Co Ltd データ通信回路および調停方法

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US7188219B2 (en) * 2004-01-30 2007-03-06 Micron Technology, Inc. Buffer control system and method for a memory system having outstanding read and write request buffers
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002530778A (ja) * 1998-11-24 2002-09-17 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド 複数の仮想ダイレクトメモリアクセスチャネルをサポートするためのダイレクトメモリアクセスエンジン
JP2007080037A (ja) * 2005-09-15 2007-03-29 Fujitsu Ltd Dma転送システム
US7970959B2 (en) 2005-09-15 2011-06-28 Fujitsu Semiconductor Limited DMA transfer system using virtual channels
JP2007249816A (ja) * 2006-03-17 2007-09-27 Ricoh Co Ltd データ通信回路および調停方法

Also Published As

Publication number Publication date
EP0772131A2 (en) 1997-05-07
EP0772131A3 (en) 1998-02-04
US5875352A (en) 1999-02-23

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