JPH0922894A - Method of manufacturing compound semiconductor element - Google Patents

Method of manufacturing compound semiconductor element

Info

Publication number
JPH0922894A
JPH0922894A JP17061695A JP17061695A JPH0922894A JP H0922894 A JPH0922894 A JP H0922894A JP 17061695 A JP17061695 A JP 17061695A JP 17061695 A JP17061695 A JP 17061695A JP H0922894 A JPH0922894 A JP H0922894A
Authority
JP
Japan
Prior art keywords
etching
compound semiconductor
substrate
layer
type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP17061695A
Other languages
Japanese (ja)
Other versions
JP3881041B2 (en
Inventor
Hideki Asano
英樹 浅野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujifilm Holdings Corp
Original Assignee
Fuji Photo Film Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Photo Film Co Ltd filed Critical Fuji Photo Film Co Ltd
Priority to JP17061695A priority Critical patent/JP3881041B2/en
Publication of JPH0922894A publication Critical patent/JPH0922894A/en
Application granted granted Critical
Publication of JP3881041B2 publication Critical patent/JP3881041B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To control remaining thickness in selective etching with an excellent repeatability, in the method of manufacturing the compound semiconductor element by crystal growth with metal organic vapor phase growth. SOLUTION: After a gas etching a substrate (a clad layer 4 that is integrated with the substrate) selectively with organic V group materials having a dimethylamino group or a diethylamino group, in a reaction chamber, the compound semiconductor layers 9, 10 and 11 are crystal grown selectively on the gas etched region of the clad layer 4 with the metal organic vapor phase growth in the reaction chamber continuously.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は化合物半導体素子の
製造方法に関し、特に詳細には、基板のエッチング残厚
を精度良く制御できるようにした化合物半導体素子の製
造方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a compound semiconductor device, and more particularly to a method of manufacturing a compound semiconductor device capable of controlling the etching residual thickness of a substrate with high accuracy.

【0002】[0002]

【従来の技術】現在、多くの半導体発光素子においてビ
ーム品質の向上が望まれており、そのような要求を満た
す素子として単一横モード半導体レーザが挙げられる。
単一横モード半導体レーザとしては様々なものが知られ
ているが、最も代表的なものとして、屈折率導波型レー
ザが挙げられる。
2. Description of the Related Art At present, it is desired to improve the beam quality in many semiconductor light emitting devices, and a single transverse mode semiconductor laser can be cited as an element which meets such requirements.
Various types of single transverse mode semiconductor lasers are known, but the most typical one is a refractive index guided laser.

【0003】図4は、この屈折率導波型レーザの一例を
示すものである。図中の1はGaAs基板、2はn型A
lGaAsクラッド層、3は活性層、4はp型AlGa
Asクラッド層、7はp型GaAsコンタクト層、9は
p型InGaPブロック層、10はn型InGaPブロッ
ク層、13はp型電極、14はn型電極である。図示されて
いる通りこの種の屈折率導波型レーザは、活性層3の発
光領域に対応するクラッド層4の左右両側が、該クラッ
ド層4よりも屈折率の小さい半導体層(ブロック層9お
よび10)で埋め込まれた構造を有し、光が屈折率の大き
い層に集まる性質を利用して単一横モード発振させるも
のである。
FIG. 4 shows an example of this index guided laser. In the figure, 1 is a GaAs substrate, 2 is an n-type A
1 GaAs clad layer, 3 is an active layer, 4 is p-type AlGa
As cladding layer, 7 is a p-type GaAs contact layer, 9 is a p-type InGaP block layer, 10 is an n-type InGaP block layer, 13 is a p-type electrode, and 14 is an n-type electrode. As shown in the figure, in this type of refractive index guided laser, the left and right sides of the cladding layer 4 corresponding to the light emitting region of the active layer 3 have a semiconductor layer (block layer 9 and It has a structure embedded in 10) and utilizes the property that light gathers in a layer with a high refractive index to generate single transverse mode oscillation.

【0004】従来、この種の半導体素子を作製するに
は、まず活性層3の上に全面的にクラッド層4を形成し
た後、このクラッド層4の左右両側部分を上面から活性
層3の近傍までエッチングし、このエッチングされた部
分にブロック層9および10を埋め込み再成長させる方法
が採用されていた。
Conventionally, in order to fabricate this type of semiconductor device, first, a clad layer 4 is formed on the entire surface of the active layer 3, and then the left and right side portions of the clad layer 4 are arranged from the upper surface to the vicinity of the active layer 3. Up to this point, a method of burying and regrowth of the block layers 9 and 10 in the etched portion was adopted.

【0005】[0005]

【発明が解決しようとする課題】ここで、クラッド層の
エッチングによる残厚t、すなわち活性層から埋め込み
層までの厚さは一般に数十〜百nmとされ、この厚さが
素子特性に大きく影響する。このエッチングは通常ウェ
ットエッチングによってなされているが、その際のエッ
チング残厚tの制御は非常に難しく、このため、所望の
素子特性が得られ難くて、素子作製の歩留りが非常に低
くなっていた。
Here, the residual thickness t of the cladding layer due to etching, that is, the thickness from the active layer to the buried layer is generally several tens to hundreds of nm, and this thickness has a great influence on the device characteristics. To do. Although this etching is usually performed by wet etching, it is very difficult to control the etching residual thickness t at that time, and thus it is difficult to obtain desired device characteristics and the yield of device manufacturing is very low. .

【0006】本発明は上記の事情に鑑みてなされたもの
であり、選択エッチングによる残厚を再現性良く制御可
能な化合物半導体素子の製造方法を得ることを目的とす
るものである。
The present invention has been made in view of the above circumstances, and an object of the present invention is to obtain a method for manufacturing a compound semiconductor device capable of controlling the residual thickness by selective etching with good reproducibility.

【0007】[0007]

【課題を解決するための手段】本発明による化合物半導
体素子の製造方法は、有機金属気相成長により化合物半
導体を結晶成長させて半導体素子を製造する方法におい
て、反応装置内で基板(基板材料そのものも、また前述
のクラッド層など基板と一体化されたものも含むものと
する)の一部をジメチルアミノ基またはジエチルアミノ
基を有する有機V族原料を用いて選択的にガスエッチン
グした後、該反応装置内において引き続き、前記基板の
ガスエッチングされた部分の上に化合物半導体層を選択
的に結晶成長させることを特徴とするものである。
A method for producing a compound semiconductor device according to the present invention is a method for producing a semiconductor device by crystallizing a compound semiconductor by metalorganic vapor phase epitaxy to produce a semiconductor device. In addition, a part of the above-mentioned clad layer integrated with the substrate is also selectively gas-etched using an organic group V raw material having a dimethylamino group or a diethylamino group, and then, in the reactor. Then, the compound semiconductor layer is selectively crystal-grown on the gas-etched portion of the substrate.

【0008】なお上記有機V族原料の代表的なものとし
ては、例えばトリスジメチルアミノアルシン[((CH
3 2 N)3 As:以下、TDMAAと称する]が挙げ
られる。
A typical example of the above organic group V raw material is, for example, trisdimethylaminoarsine [((CH
3 ) 2 N) 3 As: hereinafter referred to as TDMAA].

【0009】[0009]

【発明の効果】TDMAAに代表される有機V族原料
は、熱分解によりジメチルアミノ基やジエチルアミノ基
を遊離し、それらの基は化合物半導体をエッチングする
ことが知られている。
It is known that the organic group V raw material represented by TDMAA liberates a dimethylamino group or a diethylamino group by thermal decomposition, and these groups etch a compound semiconductor.

【0010】そして本発明者の研究によると、このよう
な有機V族原料により化合物半導体基板をエッチングす
る際には、その流量や基板温度等とエッチング速度との
間に顕著な相関関係があることが判明した。そこで、こ
の有機V族原料を用いて基板をエッチングすれば、ガス
流量や基板温度等を制御することにより、再現性良くエ
ッチング量を(つまりはエッチング残厚を)制御可能と
なる。
According to the research conducted by the present inventor, when a compound semiconductor substrate is etched with such an organic group V source material, there is a significant correlation between the etching rate and the flow rate or the substrate temperature. There was found. Therefore, if the substrate is etched using this organic group V raw material, the etching amount (that is, the etching residual thickness) can be controlled with good reproducibility by controlling the gas flow rate, the substrate temperature, and the like.

【0011】また本発明では、エッチングから化合物半
導体層の選択成長までを、反応装置内で基板を大気中に
さらすことなく連続して行なうようにしているので、良
好な結晶界面、結晶性が得られて、素子特性が格段に向
上するという効果も得られる。
Further, in the present invention, since etching to selective growth of the compound semiconductor layer are continuously performed in the reaction apparatus without exposing the substrate to the atmosphere, good crystal interface and crystallinity can be obtained. As a result, it is possible to obtain an effect that the device characteristics are remarkably improved.

【0012】[0012]

【発明の実施の形態】以下、図面を参照して本発明の実
施の形態について説明する。図1は、本発明の第1の実
施の形態により化合物半導体素子を製造する様子を概略
的に示すものである。なおこの実施の形態は、屈折率導
波型の単一横モード半導体レーザを製造する場合に本発
明を適用したものである。
BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 schematically shows how a compound semiconductor device is manufactured according to the first embodiment of the present invention. In this embodiment, the present invention is applied to the case of manufacturing a refractive index guided single transverse mode semiconductor laser.

【0013】まずMOVPE装置で有機金属気相成長法
により、n型GaAs基板1の上にn型Al0.5 Ga
0.5 Asクラッド層2、活性層3、p型Al0.5 Ga
0.5 Asクラッド層4、p型GaAsコンタクト層7を
連続成長させる。続いて基板1をMOVPE装置から取
り出し、公知の膜形成技術により上記コンタクト層7の
上にSiO2 等の絶縁膜8を作製した後、図1(a)に
示すように、フォトリソグラフィ技術により、発光領域
から左右両側に外れている部分の絶縁膜8をエッチング
により除去する。
First, n-type Al 0.5 Ga is formed on the n-type GaAs substrate 1 by metalorganic vapor phase epitaxy using a MOVPE apparatus.
0.5 As clad layer 2, active layer 3, p-type Al 0.5 Ga
The 0.5 As clad layer 4 and the p-type GaAs contact layer 7 are continuously grown. Subsequently, the substrate 1 is taken out from the MOVPE apparatus, an insulating film 8 such as SiO 2 is formed on the contact layer 7 by a known film forming technique, and then, as shown in FIG. The insulating film 8 on the left and right sides of the light emitting region is removed by etching.

【0014】次に基板1を再びMOVPE装置内に入
れ、基板温度を600 ℃にしてTDMAAを流し、絶縁膜
8に覆われていない部分を上側からエッチングする。こ
のエッチングが完了した状態を図1(b)に示す。ここ
で、図2にTDMAA流量とGaAsのエッチング速度
との関係を示すが、このようにエッチング速度はガスの
流量により容易に制御可能であるので、エッチング時間
を制御することでエッチング量を、つまりは活性層3の
上のエッチング残厚tを再現性良く正確に制御できる。
Next, the substrate 1 is placed again in the MOVPE apparatus, the substrate temperature is set to 600 ° C., TDMAA is caused to flow, and the portion not covered with the insulating film 8 is etched from the upper side. A state in which this etching is completed is shown in FIG. Here, the relationship between the TDMAA flow rate and the GaAs etching rate is shown in FIG. 2. Since the etching rate can be easily controlled by the gas flow rate as described above, the etching amount can be controlled by controlling the etching time. Can accurately control the etching residual thickness t on the active layer 3 with good reproducibility.

【0015】このエッチングが完了した後、基板1をM
OVPE装置内に入れたまま、図1(c)に示すよう
に、p型InGaPブロック層9、n型InGaPブロ
ック層10、p型GaAsコンタクト層11を選択再成長さ
せる。次に基板1をMOVPE装置から取り出し、最後
に電極を形成して単一横モード半導体レーザ素子が得ら
れる。
After this etching is completed, the substrate 1 is
As shown in FIG. 1C, the p-type InGaP block layer 9, the n-type InGaP block layer 10, and the p-type GaAs contact layer 11 are selectively regrown while being placed in the OVPE apparatus. Next, the substrate 1 is taken out from the MOVPE apparatus, and finally electrodes are formed to obtain a single transverse mode semiconductor laser device.

【0016】上述したようにこの実施の形態では、活性
層3の上のエッチング残厚t、つまり活性層3から埋め
込み層であるp型InGaPブロック層9までの厚さを
正確に制御できるので、この厚さに左右される素子特性
を、容易に所望のものとすることができる。
As described above, in this embodiment, the etching residual thickness t on the active layer 3, that is, the thickness from the active layer 3 to the p-type InGaP block layer 9 which is the buried layer can be accurately controlled. The device characteristics that depend on this thickness can be easily made to be desired ones.

【0017】次に図3を参照して、本発明の第2の実施
の形態について説明する。なおこの第2の実施の形態
も、屈折率導波型の単一横モード半導体レーザを製造す
る場合に本発明を適用したものである。
Next, a second embodiment of the present invention will be described with reference to FIG. The second embodiment also applies the present invention to the case of manufacturing a refractive index guided single transverse mode semiconductor laser.

【0018】まずMOVPE装置で有機金属気相成長法
により、n型GaAs基板1の上にn型Al0.5 Ga
0.5 Asクラッド層2、活性層3、p型Al0.5 Ga
0.5 Asクラッド層4、p型GaAsコンタクト層7を
連続成長させる。続いて基板1をMOVPE装置から取
り出し、公知の膜形成技術により上記コンタクト層7の
上にSiO2 等の絶縁膜8を作製した後、図3(a)に
示すように、フォトリソグラフィ技術により、発光領域
から左右両側に外れている部分の絶縁膜8をエッチング
により除去する。
First, n-type Al 0.5 Ga is formed on the n-type GaAs substrate 1 by metalorganic vapor phase epitaxy using a MOVPE apparatus.
0.5 As clad layer 2, active layer 3, p-type Al 0.5 Ga
The 0.5 As clad layer 4 and the p-type GaAs contact layer 7 are continuously grown. Subsequently, the substrate 1 is taken out from the MOVPE apparatus, an insulating film 8 such as SiO 2 is formed on the contact layer 7 by a known film forming technique, and then, as shown in FIG. The insulating film 8 on the left and right sides of the light emitting region is removed by etching.

【0019】次に図3(b)に示すように、上記絶縁膜
8をマスクとしてドライエッチングにより、p型Al
0.5 Ga0.5 Asクラッド層4の途中までエッチングす
る。なおドライエッチング法では、エッチング速度をガ
ス流量や印加電圧により容易かつ安定に制御できるの
で、エッチング時間を制御することにより、エッチング
残厚t’を比較的容易に所望の値にすることが可能であ
る。
Next, as shown in FIG. 3B, p-type Al is formed by dry etching using the insulating film 8 as a mask.
The 0.5 Ga 0.5 As clad layer 4 is partially etched. In the dry etching method, since the etching rate can be easily and stably controlled by the gas flow rate and the applied voltage, the etching residual thickness t ′ can be relatively easily set to a desired value by controlling the etching time. is there.

【0020】ここでは、絶縁膜8を頭に垂直なリッジが
形成される。そのため、この形状のまま第1の実施の形
態におけるのと同様の選択埋め込み成長を行なうと、マ
スクのひさしが無いためにマスク近傍では異常成長が起
こり、図3(e)に示すようにマスク脇の部分だけ盛り
上がった形状になり、表面が平坦な素子が得られなくな
る。この盛り上がりは素子をヒートシンク等に融着する
際の妨げとなり、素子特性上問題となる。
Here, a vertical ridge is formed with the insulating film 8 as a head. Therefore, if the selective embedding growth similar to that in the first embodiment is performed with this shape, abnormal growth occurs in the vicinity of the mask because there is no eaves of the mask, and as shown in FIG. It becomes a shape that is raised only in the area of, and an element having a flat surface cannot be obtained. This bulge hinders the fusion of the element to a heat sink or the like, which causes a problem in element characteristics.

【0021】しかしここで、基板1を再びMOVPE装
置内に入れ、基板温度を600 ℃としてTDMAAを流
し、ガスによるエッチングを行なうことにより、図3
(c)に示すように絶縁膜8のひさしを形成することが
できる。
However, here, the substrate 1 is again placed in the MOVPE apparatus, the substrate temperature is set to 600 ° C., TDMAA is caused to flow, and etching is carried out with a gas.
As shown in (c), the eaves of the insulating film 8 can be formed.

【0022】そしてこのエッチングが完了した後、基板
1をMOVPE装置内に入れたまま、図3(d)に示す
ように、p型InGaPブロック層9、n型InGaP
ブロック層10、p型GaAsコンタクト層11を選択再成
長させる。次に基板1をMOVPE装置から取り出し、
最後に電極を形成して単一横モード半導体レーザ素子が
得られる。この場合は、TDMAAによるエッチングを
行なうことにより、上記マスク近傍での異常成長を防止
して、表面が平坦な埋め込み構造を形成することができ
る。
After this etching is completed, the p-type InGaP block layer 9 and the n-type InGaP are kept as shown in FIG. 3D while the substrate 1 is kept in the MOVPE apparatus.
The block layer 10 and the p-type GaAs contact layer 11 are selectively regrown. Next, the substrate 1 is taken out from the MOVPE device,
Finally, electrodes are formed to obtain a single transverse mode semiconductor laser device. In this case, by performing etching by TDMAA, abnormal growth in the vicinity of the mask can be prevented and a buried structure with a flat surface can be formed.

【0023】TDMAAを用いたエッチングにより上述
の効果が得られても、その際のエッチング残厚tを正確
に制御できなければ、所望の素子特性を得ることは難し
くなる。しかしこの場合も、TDMAAによるエッチン
グを行なう前のエッチング残厚t’は前述の通り所望値
に制御可能であるし、TDMAAによるエッチング後の
残厚tも、第1の実施の形態におけるのと同様にエッチ
ング時間を制御することで正確に制御できるから、容易
に所望の素子特性が得られるようになる。
Even if the above-mentioned effect is obtained by etching using TDMAA, it is difficult to obtain desired device characteristics unless the etching residual thickness t at that time is accurately controlled. However, also in this case, the etching residual thickness t'before etching by TDMAA can be controlled to a desired value as described above, and the residual thickness t after etching by TDMAA is the same as in the first embodiment. Since the etching time can be accurately controlled, the desired device characteristics can be easily obtained.

【0024】なお、以上説明した2つの実施の形態で
は、ガスエッチングにTDMAAを用いたが、その他の
有機V族原料、例えばトリスジメチルアミノホスフィ
ン、トリスジメチルアミノアンチモン、トリスジエチル
アミノアルシン等を用いても同様の効果が得られる。
Although TDMAA is used for gas etching in the above-described two embodiments, other organic group V raw materials such as trisdimethylaminophosphine, trisdimethylaminoantimony, and trisdiethylaminoarsine may be used. The same effect can be obtained.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第1の実施の形態による化合物半導体
素子の製造方法を説明する概略図
FIG. 1 is a schematic diagram illustrating a method for manufacturing a compound semiconductor device according to a first embodiment of the present invention.

【図2】TDMAA流量とエッチング速度との関係の一
例を示すグラフ
FIG. 2 is a graph showing an example of the relationship between the TDMAA flow rate and the etching rate.

【図3】本発明の第2の実施の形態による化合物半導体
素子の製造方法を説明する概略図
FIG. 3 is a schematic diagram illustrating a method for manufacturing a compound semiconductor device according to a second embodiment of the present invention.

【図4】屈折率導波型レーザの一例を示す概略立断面図FIG. 4 is a schematic vertical sectional view showing an example of a refractive index guided laser.

【符号の説明】[Explanation of symbols]

1 GaAs基板 2 n型Al0.5 Ga0.5 Asクラッド層 3 活性層 4 p型Al0.5 Ga0.5 Asクラッド層 7 p型GaAsコンタクト層 8 SiO2 絶縁膜 9 p型InGaPブロック層 10 n型InGaPブロック層 11 p型GaAsコンタクト層 13 p型電極 14 n型電極1 GaAs substrate 2 n-type Al 0.5 Ga 0.5 As clad layer 3 active layer 4 p-type Al 0.5 Ga 0.5 As clad layer 7 p-type GaAs contact layer 8 SiO 2 insulating film 9 p-type InGaP block layer 10 n-type InGaP block layer 11 p-type GaAs contact layer 13 p-type electrode 14 n-type electrode

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 有機金属気相成長により化合物半導体を
結晶成長させて半導体素子を製造する方法において、反
応装置内で基板の一部をジメチルアミノ基またはジエチ
ルアミノ基を有する有機V族原料を用いて選択的にガス
エッチングした後、該反応装置内において引き続き、前
記基板のガスエッチングされた部分の上に前記化合物半
導体層を選択的に結晶成長させることを特徴とする化合
物半導体素子の製造方法。
1. A method for producing a semiconductor device by crystallizing a compound semiconductor by metalorganic vapor phase epitaxy, wherein a part of a substrate is made of an organic group V raw material having a dimethylamino group or a diethylamino group in a reactor. A method for producing a compound semiconductor device, comprising selectively performing gas etching, and subsequently, selectively crystallizing the compound semiconductor layer on the gas-etched portion of the substrate in the reactor.
【請求項2】 前記有機V族原料がトリスジメチルアミ
ノアルシンであることを特徴とする請求項1記載の化合
物半導体素子の製造方法。
2. The method for producing a compound semiconductor device according to claim 1, wherein the organic group V raw material is trisdimethylaminoarsine.
JP17061695A 1995-07-06 1995-07-06 Method for manufacturing compound semiconductor device Expired - Fee Related JP3881041B2 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008172101A (en) * 2007-01-12 2008-07-24 Furukawa Electric Co Ltd:The Embedding method, semiconductor device manufacturing method, and semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008172101A (en) * 2007-01-12 2008-07-24 Furukawa Electric Co Ltd:The Embedding method, semiconductor device manufacturing method, and semiconductor device
JP4653124B2 (en) * 2007-01-12 2011-03-16 古河電気工業株式会社 Semiconductor device manufacturing method

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