JPH09223777A - Platinum thin film, semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor device having a fine storage device suitable for high level of integration, by adding elements forming oxide to a lower conductive film of a ferroelectic capacitor forming the ferroelectric film on the lower conductive film containing platinum as the main component, and segregating the elements into the grain boundary of the platinum thin film. SOLUTION: This device is provided with a substrate, a lower conductive film 62 which is formed on the substrate and contains platinum as the main component, and an upper conductive layer formed on the lower conductive film 62. The upper conductive film, the lower conductive film 62 and a ferroelectric film 63 constitute a capacitor. Elements for forming oxide are added to the lower conductive film 62, and segregated into the grain boundary of a platinum thin film. At the time of forming the ferroelectric thin film, or of heat treatment in an oxygen atmosphere necessary for crystallization, oxygen diffusion in the platinum film is mainly generated in the crystal grain boundary. The oxygen diffusion is captured by oxidizing iron or the like segregated into the crystal grain boundary of platinum, and oxygen diffusion of the platinum film itself is restrained, so that a conductive layer for preventing diffusion is not oxidized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a memory capacitor suitable for a large scale integrated circuit (LSI), a method for manufacturing the same, a platinum thin film and a method for manufacturing the same.

[0002]

2. Description of the Related Art A semiconductor device having an LSI such as a dynamic random access memory (DRAM) has a problem in that the area of a capacitor is increased and the structure is complicated due to high integration. Therefore, instead of the conventionally used silicon oxides and nitrides, it has been considered to use a ferroelectric substance having a very large relative dielectric constant of several hundreds to several thousands for the capacitor insulating film. It was
Further, since a ferroelectric substance has a spontaneous polarization and can reverse its direction by an external electric field, it has been attempted to form a nonvolatile memory by using this characteristic.
For a memory using a conventional ferroelectric substance, for example,
It is described in JP-A-63-201998.

As a ferroelectric thin film used in the above memory, an oxide ferroelectric such as lead zirconate titanate or strontium titanate is generally used. Most of the ferroelectrics
Since it has a crystallization temperature of 500 ° C or higher, a platinum electrode having heat resistance has been conventionally formed on a single crystal substrate of magnesium oxide or the like, and a ferroelectric thin film is formed on it for use. However, in order to apply it to a memory, it is necessary to form a capacitor made of an electrode such as platinum and a ferroelectric substance on a silicon substrate. Since platinum reacts with silicon to form silicide, it is impossible to have a structure in which the platinum electrode is in direct contact with the silicon substrate or polycrystalline silicon. Therefore, for example, 1989 IEE International Solid State Circuits Conference
Digest (IEEE Int. Solid-State Circuits Conf.
Digest) pp.242-243,
A ferroelectric capacitor is formed on the interlayer insulating film, and a MOS
The connection to the source or drain of the transistor has been made from outside the region of the capacitor using a conductive layer for wiring such as aluminum.

[0004]

However, it is difficult to reduce the memory cell area in the method of using a conductive layer for wiring such as aluminum for connecting to the source or drain of a MOS transistor, and it is highly integrated by using a ferroelectric material. The merits of becoming the same will be halved. In order to realize a more highly integrated memory, for example, as described in JP-A-3-256358, a semiconductor substrate on which a MOS transistor is formed is covered with an insulating material, and a ferroelectric capacitor is formed thereon. It is preferable that one electrode of the ferroelectric capacitor and the source or drain of the MOS transistor formed and connected to each other are made of a conductive material embedded in a contact hole formed in an insulating material.

In order to realize this structure, it is necessary to connect one electrode of the ferroelectric capacitor and the source or drain of the MOS transistor with a conductive material. Polycrystalline silicon is generally used for this conductive material. However, as described above, when platinum and silicon directly contact with each other, they react to form a silicide, or Si diffuses in platinum to form a Si oxide film on the platinum surface, which deteriorates the characteristics of the ferroelectric capacitor. In addition, the element that constitutes the ferroelectric is Si
Problems such as diffusion to the substrate occur. As a method for solving these problems, JP-A-4-14862 and JP-A-4-18176 are available.
As described in No. 6, between the platinum electrode and Si, T
There is a method of providing a diffusion preventing conductive layer of i, Ta, TiN or the like.

However, the above-mentioned JP-A-4-14862 and JP-A-414862.
The conventional technique described in −181766 has the following problems. That is, to form an oxide ferroelectric thin film,
It is necessary to form the film in a high temperature oxidizing atmosphere of 500 ° C. or higher, or to heat-treat the film formed at a low temperature in a high temperature oxidizing atmosphere. Oxidize layers to increase contact resistance,
There is a problem that the diffusion preventing conductive material is diffused in the platinum and is oxidized to generate series parasitic capacitance.

As a method for solving this problem, it is conceivable to make the platinum layer thick. However, in a fine capacitor, the aspect ratio becomes large, making it difficult to process platinum. In addition, when the ferroelectric film is formed, the leakage current increases and the dielectric strength voltage decreases at the side wall. Therefore, it is not appropriate to increase the thickness of the platinum layer.

A first object of the present invention is to provide a semiconductor device having a fine memory suitable for high integration by using a ferroelectric material for a capacitor insulating film.

A second object of the present invention is to provide a method of manufacturing such a semiconductor device.

A third object of the present invention is to provide a platinum thin film capable of suppressing the diffusion of oxygen.

A fourth object of the present invention is to provide a method for producing such a platinum thin film.

[0012]

In order to achieve the above first object, a semiconductor device of the present invention has a lower conductive film containing platinum as a main component on a substrate and a ferroelectric film provided thereon. A ferroelectric capacitor including a body thin film and an upper conductive film provided thereon is arranged, an element forming an oxide is added to the lower conductive film, and this element is added to the grain boundary of the platinum thin film. It is made to be segregated.

A diffusion preventing conductive layer made of at least one of Ti, Ta and TiN is preferably disposed between the substrate and the lower conductive film. The lower conductive film is
It is preferable to electrically connect to a desired region of the semiconductor element, for example, a source region or a drain region of a MOS transistor, through the diffusion preventing conductive layer.

Elements such as chromium, copper, iron, aluminum, cobalt and lanthanum can be used as the element forming the oxide. You may use 2 or more types of these elements simultaneously. Further, it is preferable that these elements are added in an amount not less than the solid solubility limit in platinum. Many of these additional elements are segregated at the grain boundaries.

For the ferroelectric film, it is preferable to use an oxide ferroelectric substance such as lead zirconate titanate, barium strontium titanate, lead barium zirconate titanate, and a bismuth-based layered ferroelectric substance.

In order to achieve the second object,
The platinum thin film of the present invention is formed by sputtering platinum in an inert gas atmosphere by using platinum to which an oxide-forming element is added as a target, platinum as a main component, and the above element segregated at grain boundaries. Then, a ferroelectric film is formed on the lower platinum film,
Further, an upper conductive film is further formed thereon, and the upper and lower conductive films and the ferroelectric film constitute a ferroelectric capacitor.

Prior to forming the lower platinum film, it is preferable that a diffusion preventing conductive layer is formed on the substrate, and the lower platinum film is formed on the diffusion preventing conductive layer. The lower conductive film can be electrically connected to, for example, the source or drain region of the MOS transistor via the diffusion preventing conductive layer.

In order to achieve the third object,
The platinum thin film of the present invention is one in which an element forming an oxide is added and segregated at grain boundaries. The elements forming the oxide are the above-mentioned elements, and it is preferable that these elements are added at the solid solution limit or more.

Further, in order to achieve the above-mentioned fourth object, in the method for producing a platinum thin film of the present invention, platinum and an element forming an oxide are sputtered or vapor-deposited at the same time so that the element is a platinum film grain. It is made to segregate in the field.

Alternatively, after forming a platinum film, a thin film made of an element forming an oxide is formed to an extremely thin thickness and then heat-treated in an inert atmosphere so that they segregate at the grain boundaries of the platinum film. It is a thing.

As described above, in order to form the ferroelectric capacitor, the ferroelectric film is formed on the lower conductive film containing platinum as a main component. Oxygen diffuses in the platinum film during formation of this ferroelectric thin film or during heat treatment in an oxygen atmosphere necessary for crystallization, and the diffusion mainly occurs at the crystal grain boundaries.

When the above-mentioned additives such as chromium and iron are added to platinum, a solid solution is formed in place of platinum atoms up to a certain atomic weight ratio. However, if the amount of addition is increased, more of the additive is precipitated at grain boundaries. Like When oxygen diffuses into such a platinum film, at the grain boundaries, which are the main diffusion paths,
The element forming the oxide is easily oxidized to form the oxide, which suppresses diffusion of oxygen in the platinum film itself. Therefore, when the additive is added, the diffusion barrier conductive layer is not oxidized because the oxygen permeability of the platinum film is low even if the platinum film thickness is reduced.

Since the platinum film itself is not oxidized, its conductivity is maintained and it can be used as an electrode film.

[0024]

BEST MODE FOR CARRYING OUT THE INVENTION Using TiN as a conductive layer for strengthening adhesion and preventing diffusion, and studying how much additive can be added to a platinum electrode formed thereon to prevent oxidation of a TiN underlayer. It was After forming a TiN film having a thickness of 100 nm on a low resistance silicon substrate, a desired amount of chromium or iron pellets is placed on a platinum target and is sputtered in an argon atmosphere to obtain about 3, 5, 10, 15, 20 respectively. A 100-nm-thick film containing platinum as a main component containing mol% of chromium or iron was formed. The sputtering conditions are as shown in Table 1.

[0025]

[Table 1] Sputtering conditions for platinum film Power 400W Sputtering gas Argon 100% Gas pressure 2Pa Substrate temperature 500 ° C When this platinum film was observed with a scanning Auger electron microscope, the concentration of chromium or iron was high along the grain boundaries. It has been confirmed that Further, a lead zirconate titanate thin film having a thickness of 100 nm was formed by the sol-gel method. The sol used was a reaction product of lead acetate, titanium isopropoxide, and zirconium isopropoxide in methoxyethanol. It was crystallized by rapid thermal annealing at 650 ° C. for 2 minutes in an oxygen atmosphere. Further, the lead zirconate titanate thin film was removed, and a thin film containing platinum as a main component and a TiN film were successively finely processed to 100 μm square by ion milling using a photomask.

The results of measuring the resistance between the platinum electrode and the substrate of this sample are shown in FIG. 1 (a). As can be seen from this figure, the resistance value decreases because the degree of oxidation of the underlying TiN layer decreases as the amount of chromium or iron added increases. Particularly, when the added amount of chromium is 5 mol% or more, and when the added amount of iron is 10 mol% or more, the effect is great. It is known that when the chromium content in platinum exceeds 2%, a compound with platinum precipitates, and the solid solution limit of iron is about 19%, so the resistance decreases at the solid solution limit. Is equivalent to.

Similar effects were observed with other additive elements such as cobalt, copper, aluminum and lanthanum.

A platinum layer containing 10% chromium was deposited to a thickness of 100 nm on the titanium nitride layer having a thickness of 100 nm by the above sputtering method.
A gold upper electrode was formed using a metal mask on a sample on which lead zirconate titanate having a thickness of 100 nm was formed by the sol-gel method described above, and a voltage was applied between the upper electrode and the substrate to obtain dielectric characteristics. Examined. As shown in FIG. 1B, a good hysteresis curve is obtained, and it can be seen that the diffusion prevention conductive layer is suppressed from being oxidized and power is supplied from the substrate.

Further, although the case where the platinum electrode is formed by the sputtering method has been described in the present embodiment, similar results were obtained also for the platinum electrode formed by the vacuum evaporation method.

An example in which a memory cell is formed by using the electrode film containing platinum as the main component will be described below.

2 to 6 are examples of memory cells using the present invention. In this embodiment, the memory cell structure described in JP-A-3-256356 is used, and the storage capacitor portion has a flat structure.

First, as shown in FIG. 2, a switch transistor is formed by a conventional MOSFET forming process. Here, 21 is a p-type semiconductor substrate, 22 is an element isolation insulating film, 23 is a gate oxide film, 24 is a word line to be a gate electrode, 25 and 26 are n-type impurity diffusion layers (phosphorus), 27.
Is an interlayer insulating film. Using a known CVD method on the entire surface, SiO ₂ 28 having a thickness of 50 nm and S having a thickness of 600 nm are formed.
i ₃ N ₄ 29 is deposited by the CVD method, respectively, and Si ₃ N ₄ having a film thickness is etched to fill the insulating film between the word lines. The SiO ₂ 28 serves as a base for processing the bit line in the next step, and has a function of preventing the substrate surface from being exposed and the inter-element isolation insulating film from being scraped.

Next, as shown in FIG. 3, a portion 25 where the bit line is in contact with the n-type diffusion layer on the substrate surface and a portion 26 where the storage electrode is in contact with the n-type diffusion layer on the substrate surface are known photolithography. Method and dry etching method are used to make openings. After depositing polycrystalline silicon containing n-type impurities with a thickness of 600 nm by using the CVD method, etching by the film thickness is performed to deposit polycrystalline silicon 31 inside the hole formed by the above-described etching. 32 is embedded.

Next, an insulating film 41 is deposited on the entire surface by a known CVD method, and the bit line is electrically connected to the diffusion layer 25 of the substrate. Therefore, the insulating film 41 above the polycrystalline silicon 31 is formed. Opening is performed by using the known photolithography method and dry etching method.

Next, the bit line 42 is formed as shown in FIG. A laminated film of metal silicide and polycrystalline silicon was used as the material of the bit line. On top of this, a thickness of 200n
m of SiO ₂ 43 is deposited. The SiO ₂ 43 and the bit line 42 are processed by the known photolithography method and dry etching method to form the bit line into a desired pattern.
Then, Si ₃ N ₄ having a film thickness of 150 nm is deposited by the CVD method and etched by the dry etching method to form the sidewall spacer 44 of Si ₃ N _{4 on} the side wall portion of the bit line to insulate the bit line. . The insulating film 41 above the polycrystalline silicon 32 is opened by the known photolithography method and dry etching method.

Next, as shown in FIG. 5, a silicon oxide film type insulating film 51 such as BPSG is deposited and flattened. The insulating film 51 needs to have a film thickness sufficient to flatten the substrate surface. In this embodiment, the insulating film 51 has a thickness of 50.
It was set to 0 nm. A method of depositing SiO ₂ on the surface of the substrate by the CVD method and flattening it by the etch back method may be used. Further, the opening is formed by using the known photolithography method and dry etching method. Next, the phosphorus-doped amorphous silicon film 52 for embedding is deposited by CVD to a thickness of 200 nm and then etched back by a dry etching method.
The contact hole was filled.

Next, as shown in FIG. 6, a diffusion barrier film 10 is formed.
A TiN film 61 of 0 nm is formed. Further, a platinum base electrode 62 is formed. In this embodiment, a target in which a titanium metal plate is placed on platinum is used, and DC sputtering is used.
A platinum-based film containing mol% titanium was deposited to a thickness of about 100 nm. 50 by DC sputtering method
nm TiN deposited, SF _{6 with} photoresist as a mask
The pattern is transferred to TiN by a dry etching method using, and the Pt film 62 is patterned by a sputter etching method using this TiN as a mask. After removing TiN used for the mask by the wet etching method, the ferroelectric thin film 63 is formed.

In this embodiment, the sol-gel method described above is used.
Lead zirconate titanate (Pb (Zr
After forming a _0.5 Ti _0.5 ) O ₃ ) thin film, perform 6 in an oxygen atmosphere.
Crystallization was performed by heat treatment at 50 ° C. for 120 seconds. A plate electrode 64 is deposited and patterned to complete the capacitor of the memory cell. However, in FIG.
Plate electrodes are not shown because of the complexity of the drawing.

The dielectric characteristics of this capacitor were measured in the same manner as that shown in FIG. Set the capacitor area to 0.2
When the samples changed up to 100 μm ² were examined, it was possible to feed power from the substrate, and good hysteresis curves were obtained.

Lead zirconate titanate (Pb (Zr _0.5 Ti
_{As a} method for forming the _0.5 ) O ₃ ) thin film, the high-frequency magnetron sputtering method was used, and the same characteristics were obtained even when the thin film was formed under the conditions shown in Table 2. Therefore, if the lower electrode is formed by the method shown in the present invention, there is a concern that the diffusion prevention film may be oxidized by either the method of crystallizing the amorphous ferroelectric by post annealing or the method of directly forming the crystallized film. There is no. Therefore, the reactive vapor deposition method or the CVD method may be used.

[0041]

[Table 2] Sputtering conditions High frequency power 200 W Sputtering gas Argon (90%)-Oxygen (10%) Gas pressure 10 Pa Substrate temperature 650 ° C. In the above example, lead zirconate titanate was used as the ferroelectric substance.
Showed _{(Pb (Ti x Zr 1-} x) O 3, when the x = 0.5) as an example, different lead zirconate titanate and barium strontium titanate compositions ((Ba _x Sr _1-x ) TiO
₃ (x = 0 to 1)), lead barium zirconate titanate, and a bismuth-based layered ferroelectric can be used to form a memory cell in the same manner.

[0042]

According to the present invention, in a ferroelectric capacitor in which a ferroelectric film is formed on a lower conductive film containing platinum as a main component, oxygen necessary for forming a ferroelectric thin film or for crystallization is required. During heat treatment in an atmosphere, oxygen diffusion in the platinum film that mainly occurs at the crystal grain boundaries is captured by oxidizing chromium, iron, etc. segregated at the crystal grain boundaries of platinum, and diffusion of oxygen in the platinum film itself. Is suppressed. Therefore, according to the present invention, even if the platinum film is thin, the oxygen permeability of the platinum film is low, so that the diffusion preventing conductive layer is not oxidized. This allows
It is possible to provide a fine memory suitable for high integration using a ferroelectric as a capacitor insulating film, or a semiconductor device having the fine memory as a constituent element.

[Brief description of drawings]

FIG. 1 is a measurement diagram showing the relationship between the amount of an additive element in platinum, the resistance between a substrate and an electrode, and a voltage and an electric charge for explaining the principle of the present invention.

FIG. 2 is a first cross-sectional view showing the manufacturing process of the memory cell according to the embodiment of the present invention.

FIG. 3 is a second cross-sectional view showing the manufacturing process of the memory cell according to the embodiment of the present invention.

FIG. 4 is a third cross-sectional view showing the manufacturing process of the memory cell according to the embodiment of the present invention.

FIG. 5 is a fourth cross-sectional view showing the manufacturing process of the memory cell according to the embodiment of the present invention.

FIG. 6 is a fifth cross-sectional view showing the manufacturing process of the memory cell according to the embodiment of the present invention.

[Explanation of symbols]

21 ... Semiconductor substrate, 22 ... Element isolation oxide film, 23 ... Gate oxide film, 24 ... Word line, 25 ... Impurity diffusion layer (portion where bit line contacts n-type diffusion layer on substrate surface), 26
... impurity diffusion layer (portion where the storage electrode contacts the n-type diffusion layer on the substrate surface), 27, 28 ... interlayer insulating film, 29 ... Si ₃
N ₄ film, 31, 32 ... Polycrystalline silicon (contact pad), 41 ... Interlayer insulating film, 42 ... Bit line, 43 ... Interlayer insulating film, 44 ... Si ₃ N ₄ film, 51 ... Interlayer insulating film, 52
... polycrystalline silicon (contact pads), 61 ... diffusion preventing conductive layer, 62 ... lower electrode Pt layer, 63 ... ferroelectric thin film, 64 ... plate electrode.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor ▲ Shinichiro Takatani 1-280 Higashi Koikekubo, Kokubunji City, Tokyo Inside Central Research Laboratory, Hitachi, Ltd. (72) Hiroshi Miki 1-280 Higashi Koikeku Ku, Tokyo Kokubunji City Stock Hitachi, Ltd. Central Research Laboratory (72) Inventor Yuichi Matsui 1-280, Higashi Koikeku, Kokubunji, Tokyo Inside Hitachi Research Center, Ltd. (72) Yoshihisa Fujisaki 1-280, Higashi Koikeku, Kokubunji, Tokyo Hitachi, Ltd. Chuo In the laboratory

Claims (21)

[Claims] 1. A substrate, a lower conductive film containing platinum as a main component provided on the substrate, a ferroelectric film provided on the lower conductive film, and a ferroelectric film provided on the ferroelectric film. An upper conductive film, and the upper and lower conductive films and the ferroelectric film constitute a capacitor, and the lower conductive film is not included in the ferroelectric film constituent elements, and an element forming an oxide is added. A semiconductor device characterized by being provided. 2. The semiconductor according to claim 1, wherein a MOS transistor is arranged on the substrate, and the lower conductive film is electrically connected to a source region or a drain region of the MOS transistor. apparatus. 3. The semiconductor device according to claim 1, wherein a diffusion preventing conductive layer is disposed between the substrate and the lower conductive film. 4. The semiconductor device according to claim 3, wherein the diffusion prevention conductive layer is made of at least one substance selected from the group consisting of Ti, Ta, and TiN. 5. The semiconductor device according to claim 1, wherein the element forming the oxide is any one of chromium, lanthanum, copper, iron, aluminum and cobalt. 6. The semiconductor device according to claim 1, wherein the element forming the oxide is segregated at the grain boundaries of the platinum thin film. 7. The semiconductor device according to claim 1, wherein the element forming the oxide is added in an amount not less than the solid solution limit to platinum. 8. The semiconductor device according to claim 1, wherein the ferroelectric thin film is made of an oxide ferroelectric material. 9. The semiconductor device according to claim 8, wherein the ferroelectric thin film is made of lead zirconate titanate. 10. The ferroelectric thin film is barium titanate.
9. The semiconductor device according to claim 8, which is made of strontium. 11. The semiconductor device according to claim 8, wherein the ferroelectric thin film is made of lead barium zirconate titanate. 12. The semiconductor device according to claim 8, wherein the ferroelectric thin film is made of a bismuth-based layered ferroelectric. 13. A step of simultaneously sputtering or vapor-depositing platinum and an element forming an oxide to form a lower conductive film containing platinum as a main component and containing the element forming the oxide on a substrate. The method has a step of forming a ferroelectric film on the lower conductive film and a step of forming an upper conductive film on the ferroelectric film, and the upper and lower conductive films and the ferroelectric thin film form a capacitor. A method of manufacturing a semiconductor device, which comprises forming the semiconductor device. 14. Before the step of forming the lower conductive film,
A step of forming a diffusion preventing conductive layer on the substrate,
The method of manufacturing a semiconductor device according to claim 13, wherein the lower conductive film is formed on the diffusion preventing conductive layer. 15. A step of forming at least a part of a MOS transistor on the substrate before the step of forming the diffusion preventing conductive layer, wherein the lower conductive film is a source region or a drain region of the MOS transistor. 15. The method for manufacturing a semiconductor device according to claim 13, wherein the semiconductor device is electrically connected to. 16. A platinum thin film, which is a metal not included in the constituent elements of the ferroelectric thin film and to which an element forming an oxide is added. 17. The platinum thin film according to claim 16, wherein the element forming the oxide is any one of chromium, lanthanum, copper, iron, aluminum and cobalt. 18. The platinum thin film according to claim 16 or 17, wherein the element forming the oxide is segregated at grain boundaries. 19. The oxide-forming element is added in an amount not less than the solid solution limit to platinum.
The platinum thin film according to any one of 6 to 18. 20. A method for producing a platinum thin film, which comprises simultaneously sputtering platinum and an element forming an oxide to form a platinum thin film in which the element is segregated at grain boundaries on a substrate. 21. A platinum thin film is formed on the substrate, and a layer of chromium, lanthanum, copper, iron, aluminum or cobalt is formed on the platinum thin film, and then, in a vacuum or oxygen-free atmosphere. The method for producing a platinum thin film according to claim 17, wherein heat treatment is performed.