JPH09223391A - Forced refresh device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable exact performance measurement by issuing a refresh instruction at arbitrary timing and suppressing the memory access instruction in a CPU. SOLUTION: When the refresh instruction 4 is issued, a request conversion circuit 5 delivers the same to a refresh control circuit 7 and delivers the same to a refresh state instructing circuit 6. This refresh state instructing circuit 6 sends a DRAM state instruction signal 15 to the CPU and suppresses the memory access instruction. On the other hand, the refresh control circuit 7 refreshes a DRAM 3 by the force refresh signal 11 from the request conversion circuit 5 or the refresh request 13 from a time measurement circuit 8. The DRAM 3 sends signals to the refresh control circuit 7 and the refresh state instructing circuit 6 to release the memory access instruction suppression when the refresh ends. As a result, the refresh instruction is issued at the arbitrary timing and the exact performance measurement is made possible.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a forced refresh device, and more particularly to a forced refresh device for refreshing a dynamic random access memory (hereinafter referred to as DRAM) at an arbitrary timing.

[0002]

2. Description of the Related Art In a DRAM, it is necessary to perform a refresh operation on a memory cell in order to retain the stored content.
Depending on the device, the number of refresh cycles required (provisionally N seconds) within a fixed time (provisionally N seconds)
Is stipulated.

As a refresh method, there are a distributed refresh method, a concentrated refresh method, and the like. The distributed refresh method is a method in which M cycles are evenly allocated during N seconds and refresh is performed once every N / M seconds. The centralized refresh method is a method of continuously refreshing M times every N seconds.

Conventionally, the refresh request section sends a refresh request signal so as to satisfy the refresh regulation, and starts the refresh operation. That is, the timing of sending the refresh request signal is determined by the central processing unit (C
(PU) is asynchronous, and further, the memory access request from the CPU is held during the memory refresh operation, and the memory access instruction cannot be processed until the refresh is completed.

Therefore, the CPU does not know when the memory refresh request is generated, or how many times the refresh is generated during the processing by the CPU.
It was not possible to know the effect of the refresh time on the processing of the CPU.

In particular, in the CPU, a refresh request signal may be generated during the performance measurement process. In this case, the refresh time is added to the execution time of the performance measurement point, and the performance of the measurement point is increased. Could not be measured accurately. The shorter the execution time of the performance measurement point, the greater the influence of this refresh time.

Among the conventional refresh methods described above,
In the distributed refresh method, one refresh time is short, but since the refresh interval is short, there is a possibility that the refresh operation may be performed multiple times during performance measurement, and it is likely to compete with the access request from the CPU to the memory. In addition, since the refresh interval in the centralized refresh method is longer than that in the distributed refresh method, the probability of a refresh request occurring during performance measurement is low, but the refresh time is long, so if a refresh request occurs during performance measurement, the performance will be affected. The impact will be greater.

FIG. 3 is a timing chart when a memory refresh occurs during performance measurement according to the prior art. In the figure, a timing R1 is a timing at which a refresh request is generated and the memory refresh is started, and a timing R2 is a timing at which the memory refresh is ended. When the time from the timing R1 to the next timing R1 is n seconds, n = N / M in the distributed refresh method and n = N in the concentrated refresh method.
become.

Timing 3A is a performance measurement start timing. The performance measurement is started from the timing 3A, the memory refresh request is generated at the timing 3B (timing R1), and the performance measurement process is interrupted. Then, it is assumed that the memory is refreshed for Tr seconds from timing 3B, the performance measurement processing suspended at timing 3C (timing R2) is restarted, and the performance measurement processing is terminated at timing 3D.

At this time, assuming that the performance measurement time from timing 3A to timing 3B is T1 seconds and the performance measurement time from timing 3C to timing 3D is T2 seconds,
The actual execution time of the performance measurement location is (T1 + T2) seconds, but the actual execution time becomes (T1 + T2 + Tr) seconds due to the occurrence of refresh at timing 3B. That is, the shorter the time (T1 + T2 = T), the greater the influence of the refresh time Tr.

According to Japanese Patent Laid-Open No. 3-104083, the refresh control method can be selected from the distributed refresh method and the centralized refresh method as needed. In both methods, particularly during a performance measurement, a short time is required. It is not possible to eliminate 100% of the influence of refresh during performance measurement at.

[0012]

As described above, in the conventional refresh method, when a refresh request is made during performance measurement in a short time, the refresh time is added to the execution time of the performance measurement point, and therefore the performance measurement is accurately performed. It may not be possible. Generally, there are two refresh methods. In the distributed refresh method, the refresh interval is short, so that it is likely to cause a conflict with the memory access request of the CPU. In the centralized refresh method, the refresh time is long and the CPU is long. Memory access request of the CPU is held for a long time when it conflicts with the memory access request of. That is, in both cases, there is a possibility that refresh may occur during performance measurement in the CPU for a short time.

The above situation is because the central processing unit and the memory are refreshed asynchronously, and the refresh request unit merely issues the refresh request so as to satisfy the refresh regulation.

By the way, in recent years, an inexpensive DRAM is often used as a memory element of a large computer. Especially when a DRAM is used as a memory element of a high-speed computer such as a super computer, if a memory refresh occurs during a short-time performance measurement, the execution time of a few milliseconds is compared with the refresh time of a few milliseconds. However, the performance may not be accurately measured.

An object of the present invention is to provide a forced refresh device which has a function of forcibly refreshing the memory immediately before the performance measurement so that the memory refresh request is not generated during the performance measurement in a short time. Especially.

[0016]

A forced refresh device of the present invention is a memory device having refresh means for periodically rewriting, and a refresh command for instructing a refresh operation is input to force the refresh means. A request conversion circuit for sending a forced refresh signal to be activated, and a refresh for instructing the request conversion circuit to display a refresh state of the memory device and displaying a non-refresh state of the memory device according to a refresh end signal from the refresh means. And a state indicating circuit.

Further, the forced refresh device of the present invention is
In a memory device having refresh means for periodically rewriting, in accordance with a refresh command for instructing a refresh operation, the operation cycle of the refresh means is ignored and the refresh operation is forcibly executed, and the refresh operation is executed. The processing subsequent to the refresh instruction is stopped while the refresh instruction is completed, and the processing subsequent to the refresh instruction is continued when the refresh operation is completed.

Further, the forced refresh device of the present invention includes a memory which needs to be refreshed periodically, and a refresh control circuit which is activated by an external signal to refresh the memory and sends a refresh end signal at the end of refresh. A time measurement circuit for measuring the cycle of refreshing the memory and activating the refresh control circuit; a request conversion circuit for sending a forced refresh signal according to a refresh command to activate the refresh control circuit at non-periodic timing; And a refresh state instruction circuit for displaying a refresh state of the memory according to a refresh signal and displaying a non-refresh state of the memory according to the refresh end signal.

That is, by preparing an instruction forcibly requesting the refresh of the memory element, issuing the instruction immediately before the performance measurement processing, converting the refresh request instruction into a forced refresh signal, and refreshing the memory. Therefore, it is possible to eliminate the measurement error due to the refresh when the performance is measured in a short time.

[0020]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure, the forced refresh device according to the present invention is a DRA that requires periodic refreshing.
A refresh control circuit 7 which is activated by M3 and a signal from the outside to refresh the DRAM and sends a refresh end signal 12 at the end of refresh.
And a main memory unit 2 including a time measuring circuit 8 for measuring the period for refreshing the DRAM and activating the refresh control circuit 7, and a forced refresh signal 11 according to a refresh command 4 to send out the refresh control circuit 7 asynchronously. Forced refresh including a request conversion circuit 5 activated at a timing of 5 and a refresh state instruction circuit 6 for displaying a refresh state of the DRAM according to the forced refresh signal 11 and displaying a non-refresh state of the DRAM according to the refresh end signal 12. And part 1.

Here, it is assumed that the DRAM 3 needs a refresh operation of M cycles in N seconds.

The refresh command (hereinafter referred to as RFL command) 4 is generated by software immediately before the start of performance measurement. When the RFL instruction 4 is issued, the request conversion circuit 5 converts it into a forced refresh signal 11 and sends it to the refresh control circuit 7 in the main memory 2 and also to the refresh state instruction circuit 6. .

The refresh state instruction circuit 6 turns the state ON when it receives the forced refresh signal from the request conversion circuit 5, and turns it OFF when it receives the refresh end signal 12 from the refresh control circuit 7.
The AM state instruction signal 15 is transmitted. Then, the CPU checks the refresh state instruction circuit 6 with the DRAM state instruction signal 15, and if the state is ON, the RFL
Issuance of the memory access instruction subsequent to the instruction is suppressed, and if the state is OFF, the subsequent memory access instruction is issued.

The refresh control circuit 7 receives the forced refresh signal 11 from the request conversion circuit 5, or the refresh request 13 from the time measuring circuit 8.
In response to this, the refresh operation of the DRAM 3 is started. The refresh control circuit 7 sends a reset signal 14 to the time measuring circuit 8 when the DRAM 3 is refreshed by receiving the forced refresh signal 11.

The time measuring circuit 8 uses the refresh request signal 1
When 3 is sent and when the reset signal 14 is received, the counter is reset to the initial state (probably set to 0) and then counting up is started, and the count value becomes L (defined by the memory element). At that time, the refresh request signal 13 is sent to the refresh control circuit 7.

Although it has been described here that the time measuring circuit 8 counts up with 0 as the initial state, it may be possible to send the refresh request signal 13 when the initial state is set to L and the countdown is performed to reach 0.

When the DRAM 3 finishes refreshing, it sends an end signal to the refresh control circuit 7, and the refresh control circuit 7 sends a refresh end signal 12 to the refresh state instruction circuit 6. When the refresh state instruction circuit 6 receives the refresh end signal 12, it turns the state OFF.

FIG. 2 is a timing chart showing the operation of the above-mentioned forced refresh device. In the figure, timing R1 is a timing at which a refresh request is generated and the memory refresh is started, and timing R2 is a timing at which the memory refresh is finished. Here, the timing R11 is the timing at which the time measuring circuit 8 reaches the specified value and the refresh request signal 14 is sent to the refresh control circuit 7 to start refreshing the DRAM 3. Timing R21 is the timing when the refresh of the DRAM 3 is completed and the completion signal is sent to the refresh control circuit 7.

If the RFL command 4 is not issued, the next refresh request signal 13 is generated after n seconds,
Refreshing is started (timing R1). In the distributed refresh method, n = N / M, and in the concentrated refresh method, n = N.

The RFL instruction 4 is generated by software immediately before the performance measurement is started, and the request conversion circuit 5 sends out the forced refresh signal 11 at the timing 2B. Then, the refresh control circuit 7 causes the DRAM 3 to start the refresh operation (timing R12). . At this time, the state of the refresh state instruction circuit 6 is turned on,
If the state of the refresh state instruction circuit 6 is checked when starting the performance measurement process, the state is ON, so the performance measurement process is suppressed. Then, Tr of timing 2B
After 2 seconds, the refresh operation of the DRAM 3 ends (timing R22), and the DRAM 3 causes the refresh end signal 12
To the refresh state instruction circuit 6 via the refresh control circuit 7, and when the refresh state instruction circuit 6 receives the refresh end signal 12, the state is turned off.

The performance measurement processing that has been suppressed starts the performance measurement processing when the refresh state instruction circuit 6 is turned off (timing 2A), and ends the measurement at timing 2D after T seconds. At the start of refresh (timing R12) by issuing the RFL command, the refresh control circuit 7 sends a reset signal 14 to the time measuring circuit 8 to set the time measuring circuit 8 to an initial value (0) and count up. When the count value reaches n, the refresh request signal 13 is sent to the refresh control circuit,
Start refreshing M3. (Timing R13)
When the execution time T of the performance measurement point is shorter than (n-Tr) seconds, no refresh request is generated during the performance measurement process, so the execution time (Tp) of the performance measurement point remains T seconds. An accurate performance value can be obtained.

Further, the execution time of the performance measurement point is (n-T
If it is larger than r) seconds, a refresh request for the DRAM 3 is generated during performance measurement, but since the execution time T is relatively longer than the refresh time Tr, the refresh time is an error when viewed from the overall execution time T. To the extent
The performance impact is negligible.

[0034]

As described in detail above, the forced refresh device of the present invention is a memory device having a refresh means for periodically rewriting, and the refresh means of the refresh means is operated in accordance with a refresh command instructing a refresh operation. Ignoring the operation cycle, forcibly executing the refresh operation, stopping the processing following the refresh instruction while the refresh operation is being executed, and processing following the refresh instruction when the refresh operation is completed I am trying to continue.
Therefore, by issuing a refresh command at an arbitrary timing and measuring the performance, it is possible to always measure the accurate performance. That is, in the performance measurement involving a very short time, the processing time can be measured during the refresh cycle without including the refresh time.

[Brief description of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a timing chart showing an example of the operation of the present invention.

FIG. 3 is a timing chart showing an operation of a conventional example.

[Explanation of symbols]

 1 forced refresh section 2 main memory section 3 DRAM 4 refresh command 5 request conversion circuit 6 refresh state instruction circuit 7 refresh control circuit 8 time measurement circuit 11 forced refresh signal 12 refresh end signal

Claims (3)

[Claims] 1. A request conversion circuit in a memory device comprising refresh means for periodically rewriting, for transmitting a forced refresh signal for inputting a refresh command instructing a refresh operation and forcibly starting the refresh means. And a refresh state instruction circuit for displaying a refresh state of the memory device instructed by the request conversion circuit and displaying a non-refresh state of the memory device according to a refresh end signal from the refresh means. Refresh device. 2. A memory device comprising refresh means for periodically rewriting, ignoring an operation cycle of the refresh means in accordance with a refresh command for instructing a refresh operation, forcibly executing the refresh operation, and performing the refresh operation. A forced refresh apparatus, wherein the process following the refresh command is stopped while the operation is being executed, and the process following the refresh command is continued when the refresh operation is completed. 3. A memory which needs to be refreshed periodically, a refresh control circuit which is activated by an external signal to refresh the memory and sends a refresh end signal at the end of refresh, and a cycle for refreshing the memory. A time measuring circuit for measuring and activating the refresh control circuit, a request conversion circuit for sending a forced refresh signal according to a refresh command and activating the refresh control circuit at non-periodic timing, and a refresh state of the memory according to the forced refresh signal And a refresh state instruction circuit for displaying the non-refresh state of the memory according to the refresh end signal.