JPH09219844A - Identification signal processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress malfunctions due to the timing deviation of line detection signals by providing a synchronizing signal correction circuit for correcting the omission part of synchronizing signals equivalent to the clock input signals of a counter circuit and detecting several lines in front and at the back of the line to which EDTV2 identification signals are inserted. SOLUTION: The counter circuit 6 starts counting synchronization correction signals J generated from half H elimination signals D by the synchronizing signal correction circuit 8 after being reset by vertical synchronization delay signals F. In this case, when the omission of signals is generated in the half H elimination signals D, the signals J detect that the omission part is present in the halt H elimination signals D when the next rise is not inputted within 65μs for instance from the rise of the half H elimination signals D by the circuit 8. Then, by adding pulses to the omission part of the signals D (65μs part from the final rise,) clock signals without the omission are obtained. Thus, the several lines in front and at the back of the line to which the BDTV2 identification signals are inserted are detected and the malfunctions are suppressed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to television broadcasting (N
Wide clear vision of TSC (EDTV2: Ext)
and an identification for identifying a video signal with an aspect ratio of 4: 3, a letterbox signal with an aspect ratio of 4: 3, and a squeeze (or full mode) signal with an aspect ratio of 16: 9. The present invention relates to a signal processing device.

[0002]

2. Description of the Related Art FIG. 11 is a block diagram of a conventional identification signal processing device. In the figure, 1 is a sync separation circuit for separating a sync signal from a video signal, 4 is a vertical sync separation circuit for separating a vertical sync signal from the sync signal, 6 is a vertical sync signal as a reference, and the sync signal is counted. ), A counter circuit that outputs a count value for line detection,
Reference numeral 7 denotes a line detection signal generation circuit that generates a line detection signal that limits the identification signal processing period from the output of the counter circuit.

Next, the operation will be described. 12 is an odd field signal waveform of each part in FIG.
Is the even field signal waveform of each part in FIG. The EDTV2 video signal A relating to wide clear vision broadcasting becomes a sync signal B that is input from the input terminal P1 and separated by the sync separation circuit 1, and is input to the counter circuit 6. On the other hand, the synchronization signal B becomes the vertical synchronization signal E separated by the vertical synchronization separation circuit A and is input to the counter circuit 6.

The counter circuit 6 counts the vertical synchronizing signal E as a reset signal and the synchronizing signal B as a clock input, and the EDTV2 identification signal is inserted 22.2.
Timing pulse F that rises at the beginning of line 85
The timing pulse B and H which rise at the end with G are output.

In the odd field, the timing pulse F: Go indicating the beginning of 22 lines rises at the count value 18 and the timing pulse B: Ho indicating the end thereof is:
The pulse rises when the count value is 19 and falls when the vertical synchronizing signal E is reset. In the even field, the timing pulse F indicating the start of line 285:
Ge rises at a count value of 18, and the timing pulse B: He indicating the end rises at a count value of 19 and falls when the vertical synchronization signal E is reset. The line detection signal generation circuit 7 multiplies the timing pulse F: G by the inverted signal of the timing pulse B: H to output the line detection signal I in which only the 22nd line and the 285th line are Hi.

In the block diagram thus constructed, if the counter circuit 6 makes an error in the count value of the synchronization signal B even if it is counted by one, the EDTV2 identification signal cannot be identified. Further, since the synchronization signal B which is the clock signal of the counter circuit 6 is directly input from the synchronization separation circuit 1, malfunction of the synchronization separation circuit 1 due to deterioration of the EDTV 2 video signal A or the like directly affects.

[0007]

Since the conventional EDTV2 identification signal processing apparatus is constructed as described above, it has the following problems. The first problem is the timing shift of the line detection signal due to omission or attenuation of the sync signal, and the second problem is the malfunction of the sync separation circuit in the case of an input signal with deteriorated S / N ratio in a weak electric field. It is the timing shift of the line detection signal due to the above. These things lead to deterioration of the stability of the identification result of the EDTV 2 as in the conventional example.

The present invention has been made to solve the above problems, and an object thereof is to improve the stability of an EDTV2 signal processing device. Still another object is to improve the identification accuracy of the EDTV2 signal processing device.

A first object of the present invention is to provide an identification signal processing device which can improve the stability of the signal processing device for wide clear vision broadcasting accurately and improve its identification accuracy.

A second object of the present invention is to obtain an identification signal processing device capable of more accurately improving the stability of the signal processing device for wide clear vision broadcasting and improving the identification accuracy thereof.

A third object of the present invention is to provide an identification signal processing device capable of improving the stability of the signal processing device for wide clear vision broadcasting more accurately and improving the identification accuracy thereof.

A fourth aspect of the present invention has an object to obtain an identification signal processing device capable of further accurately improving the stability of the signal processing device for wide clear vision broadcasting.

A fifth object of the present invention is to provide an identification signal processing device capable of more accurately improving the identification accuracy of the signal processing device for wide clear vision broadcasting.

[0014]

Means for Solving the Problems In the first invention,
First means for separating a synchronization signal from a video signal;
Second means for extracting a sync edge signal consisting of the leading edge of the sync signal separated by the means, and a half H removal signal obtained by removing the half H signal in the vertical blanking period from the sync edge signal extracted by the second means And a fourth means for separating the vertical synchronization signal from the synchronization signal separated by the first means, and a vertical synchronization delay obtained by delaying the vertical synchronization signal separated by the fourth means for a predetermined time. A fifth means for extracting a signal, and counting the half H removal signal extracted by the third means on the basis of the vertical synchronization delay signal extracted by the fifth means, an identification signal relating to a specific television broadcast is obtained. Sixth means for outputting a timing pulse for detecting the inserted line;
Seventh means for generating a line detection signal for limiting a signal processing period for identifying the identification signal from the timing pulse output by the means.

According to a second aspect of the present invention, there is provided a first means for separating a sync signal from a video signal, a second means for extracting a sync edge signal consisting of a leading edge of the sync signal separated by the first means, and Third means for extracting a half H removal signal obtained by removing the half H signal in the vertical blanking period from the synchronization edge signal extracted by the second means, and separating the vertical synchronization signal from the synchronization signal separated by the first means And a fifth means for extracting a vertical sync delay signal obtained by delaying the vertical sync signal separated by the fourth means for a predetermined time, and a vertical sync delay signal extracted by the fifth means as a reference. A timing for counting the half H removal signals extracted by the third means and detecting 22 lines (285 lines) in which an identification signal related to wide clear vision broadcasting is inserted. And a seventh means for generating a line detection signal for limiting a signal processing period for identifying a signal related to wide clear vision broadcasting from the timing pulse output by the sixth means. .

In the third invention, when a part of the half H-removed signal extracted by the third means is missing, the missing is detected and the half H-removed signal is corrected.
Means.

In the fourth invention, the half H removal signal extracted by the third means is counted based on the vertical synchronization delay signal extracted by the fifth means, and the identification signal for wide clear vision broadcasting is inserted. Several lines before and after 22 lines (285 lines) {22 lines (2
85th line)-[alpha] line to 22th line (285th line) + [beta] line} ([alpha] / [beta] is an integer) is included in the ninth means for outputting a timing pulse.

In the fifth aspect of the invention, when the identification result is determined to be "a signal related to wide clear vision broadcasting" for two or more lines within the detection period of the line detection signal generated by the ninth means, A tenth means for inverting the identification result is provided.

The embodiment of the present invention has the following concrete means. An EDTV2 signal processing device according to the present invention includes a sync signal correction circuit for correcting a sync signal omission, a line detection signal generation circuit for detecting several lines before and after a line in which an EDTV2 identification signal is inserted, and a line detection signal detection period. When EDTV2 signals of two or more lines are confirmed, a line correlation circuit for inverting the identification result is provided.

The embodiment of the present invention has the following specific actions. In the present invention, a synchronization signal correction circuit is provided in the preceding stage of the counter circuit, and several lines before and after the line in which the EDTV2 identification signal is inserted are detected by the line detection signal, and the line correlation is observed within that period to identify the EDTV2 The signal insertion portion can be detected stably, and the identification accuracy is improved.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1. FIG. 1 is a block diagram of an EDTV2 identification signal processing device of the present invention. In the figure, 1 is a sync separation circuit for separating a sync signal from a video signal, 2 is an edge detection circuit for extracting the leading edge of the sync signal, that is, the leading edge of the sync signal, and 3 is a vertical blanking period from the output signal of the edge detection circuit. , A half H removal circuit for removing the half H signal, a vertical sync separation circuit for separating the vertical sync signal from the sync signal, and a delay circuit for delaying the vertical sync signal for a predetermined time,
6 is a counter circuit that counts the output signal of the edge detection circuit based on the output signal of the delay circuit and outputs a count value for detecting 22 (285) lines. 7 is the EDTV2 identification signal processing from the output signal of the counter circuit. It is a line detection signal generation circuit that generates a line detection signal that limits the period.

Next, the operation will be described. 2 is an odd field signal waveform of each part in FIG. 1, and FIG. 3 is an even field signal waveform of each part in FIG. EDTV2 video signal A related to wide clear vision broadcasting is
It is input from the input terminal P1 and separated by the sync separation circuit 1 to become the sync signal B. The sync signal B is the edge detection circuit 2
The leading edge of the synchronizing signal, that is, the leading edge of the synchronizing signal becomes a synchronizing edge signal C, and the half H removal circuit 3
By prohibiting the reading of the sync edge signal C for a predetermined time (1 / 2H to 1H) from the sync signal part synchronized with the horizontal sync signal part to the sync signal part after 1H, the half H signal in the vertical blanking period Is removed and becomes a half H removal signal D of H period, which is input to the counter circuit 6.

On the other hand, the synchronizing signal B becomes the vertical synchronizing signal E separated by the vertical synchronizing separation circuit 4, and becomes the vertical synchronizing delay signal F delayed by 3 / 4H (48 μs) by the delay circuit 5 and input to the counter circuit 6.

The counter 6 counts the vertical sync delay signal F as a reset signal and the half H removal signal D as a clock signal, and a timing pulse F: G which rises at the beginning of the 22.285 line in which the EDTV2 identification signal is inserted. And timing pulse B which rises at the end:
H is output.

In the odd field, the timing pulse F: Go indicating the beginning of 21 lines rises at a count value of 15, and the timing pulse B: Ho indicating the end of 23 lines rises at a count value of 16 and the vertical synchronization delay signal F. It becomes a pulse that falls at the reset of. Also,
Also in the even field, the timing pulse F: Ge indicating the start of the 284 line rises at the count value of 15, and the timing pulse B: He indicating the end of the 286 line rises at the count value of 16 and the vertical synchronization delay signal F It is a pulse that falls at reset.

The line detection signal generation circuit 7 outputs the line detection signal I by calculating the timing pulse F: G and the timing pulse B: H. The line detection signal generation circuit 7 outputs the timing pulse F and the timing pulse B. The line detection signal I in which only the 22nd line and the 285th line are Hi is output by multiplying the inversion signal of.

In the block diagram thus constructed, S
When an EDTV2 video signal having a deteriorated / N ratio is input, the half separation circuit 1 can prevent malfunction of the sync separation circuit 1 due to noise during the read prohibition period of the half H removal circuit 3.
It is possible to suppress the deterioration of the stability of the EDTV2 identification signal processing due to the timing shift of the line detection signal I.

Embodiment 2 FIG. 4 shows the EDT of the present invention.
It is a block diagram of Embodiment 2 of a V2 identification signal processing device. The difference of this configuration from the block diagram of the first embodiment is that between the half H removal circuit 3 and the counter circuit 6,
A synchronization signal correction circuit 8 for detecting and correcting the loss of the half H removal signal is being added.

Next, the operation will be described. FIG. 5 is an odd field signal waveform of each part in FIG. The counter circuit 6 is reset by the vertical sync delay signal F and then starts counting the sync correction signal J generated from the half H removal signal D by the sync signal correction circuit 8. Here, when a signal is missing in the half H removal signal D, the synchronization correction signal J is a half H signal when the synchronization signal correction circuit 8 does not input the next rising edge within 65 μs from the rising edge of the half H removal signal D. It is detected that there is a missing portion in the removal signal D, and a pulse is added to the missing portion of the half H removal signal D (65 μs portion from the last rising edge) to form a clock signal without missing. Therefore, the timing pulse F: Go indicating the start of the 22nd line rises at the count value 15, the timing pulse B: Ho indicating the end rises at the count value 16, and the count value of the counter circuit 6 is the same as in the first embodiment. It will be the same value as. Other operations are the same as those in the first embodiment.

In the block diagram configured as described above, even when a signal is missing in the half H removal signal: D, the same stability as that of the first embodiment can be maintained.

Embodiment 3 FIG. 6 shows the EDT of the present invention.
It is a block diagram of Embodiment 3 of a V2 identification signal processing device. This configuration differs from the block diagram of the first embodiment described above in that the counter circuit includes several lines before and after the 22 (285) line in which the EDTV2 identification signal is inserted {22 (2
85) −α line to 22 (285) + β line}, which is the counter circuit 9 for outputting a timing pulse for detecting.

Next, the operation will be described. FIG. 7 is an odd field signal waveform of each part in FIG. Similar to the first embodiment, the counter 9 counts the vertical sync delay signal F as a reset signal and the half H removal signal D as a clock input, and ends the timing pulse F: K indicating the start of the EDTV2 identification signal processing period. , And the line detection signal generation circuit 7 outputs the line detection signal M by calculating the timing pulse F: G and the timing pulse B: H.

The operation of the counter circuit 9 will be specifically described by taking as an example the case where the detection period of the line detection signal I is set to 21 to 23 lines (odd field) and 284 to 286 lines (even field). α =
β = 1). The counter circuit 9 starts counting the half H removal signal D after being reset by the vertical synchronization delay signal F. In the odd field, the timing pulse F: Ko indicating the start of 21 lines rises at the count value 14 and the timing pulse B: L indicates the end of 23 lines.
o is a pulse that rises at the count value 17 and falls when the vertical synchronization delay signal F is reset. Further, in the even field, the timing pulse F: Ke indicating the start of the 284th line rises at the count value of 14 and becomes 28.
Timing pulse B: Le indicating the end of 6 lines is
It becomes a pulse that rises at the count value 17 and falls when the vertical synchronization delay signal F is reset. The line detection signal generation circuit 7 multiplies the timing pulse F and the inverted signal of the timing pulse B to detect a line in which only 21 to 23 lines (odd field) and 284 to 286 lines (even field) are Hi. The signal M is output. In the block diagram configured as described above, even when the counter circuit 9 makes an error of ± 1 count in the count value of the half H removal signal D, the stability equivalent to that of the first embodiment can be maintained.

Embodiment 4 FIG. 8 shows the EDT of the present invention.
It is a block diagram of Embodiment 4 of a V2 identification signal processing device. In the figure, 10 and 11 are flip-flops (hereinafter referred to as FFs) forming a shift register, and 12 is Q1 of the FF circuit 10 when the FF circuit 11 is in a set state.
AND circuit for dropping output to Lo, 13 is AND circuit 12
Is an FF circuit that latches the output of the.

Next, the operation will be described. FIG. 9 is a signal waveform of each part in FIG. The EDTV2 identification signal is inserted into 21 lines and 22 lines of the input video signal, and the case where the line detection period is from 21 lines to 23 lines (α = β = 1) will be specifically described as an example. The EDTV2 detection signal N indicating the detection result of the EDTV2 identification signal in each line is input to the input terminal P3.
In this case, the ED becomes the period Hi from the end of the EDTV2 identification signal to the next synchronization signal on the 21st and 22nd lines.
FF10 in which the TV2 detection signal N constitutes a shift register
Input as 11 clock signal. The rising edge of the 21st line of the EDTV2 detection signal N puts the FF 10 in the set state, and the rising edge of the 22nd line puts the FF 11 in the set state. The Q1 output P of the FF10 and the QB2 output Q of the FF11 become the AND output R which becomes Lo when the FF11 is in the set state by the AND circuit 12.
It becomes the data input of FF13.

On the other hand, the line detection signal B: O which is an inverted signal of the line detection signal M is input to the input terminal P4. In this case, the FF10.
The reset signal of 1 and the clock signal of the FF 13 are input. In the FF 13, the AND output R that is Lo is set to the data input, and the data (AND output) is latched at the rising edge (trailing edge) of the line detection signal B: O. As a result, Q3 output S of FF13 becomes Lo, and E
It is identified as not a DTV2 video signal.

In addition to the input signal used in the above-mentioned fourth embodiment, FIG. 10 shows a pattern of the input signal which is identified as not the EDTV2 video signal.

In the block diagram thus constructed, in the EDTV2 detection in each line in the line detection period,
When a video signal having a line correlation is erroneously recognized as an EDTV2 identification signal, the identification result obtained by inverting the EDTV2 detection result is output, so that a malfunction can be prevented and the identification accuracy is improved.

As described above, according to the embodiment of the present invention, the synchronization signal correction circuit for correcting the missing portion of the synchronization signal corresponding to the clock input signal of the counter circuit is provided, and the EDTV2 identification signal 22 inserted
Since several lines before and after the (285) line are detected,
It suppresses malfunctions due to the timing shift of the line detection signal,
Stability is improved.

[Brief description of drawings]

FIG. 1 is a block diagram of a first embodiment of an EDTV2 identification signal processing device according to the present invention.

FIG. 2 is a diagram showing an odd field signal waveform of each part of the first embodiment of the present invention.

FIG. 3 is a diagram showing an even field signal waveform of each part of the first embodiment of the present invention.

FIG. 4 is a block diagram of a second embodiment of an EDTV2 identification signal processing device according to the present invention.

FIG. 5 is a diagram showing an odd field signal waveform of each part of the second embodiment of the present invention.

FIG. 6 is a block diagram of a third embodiment of an EDTV2 identification signal processing device according to the present invention.

FIG. 7 is a diagram showing an odd field signal waveform of each part of the third embodiment of the present invention.

FIG. 8 is a block diagram of a fourth embodiment of an EDTV2 identification signal processing device according to the present invention.

FIG. 9 is a diagram showing an odd field signal waveform of each part of the fourth embodiment of the present invention.

FIG. 10 is an EDTV according to a fourth embodiment of the present invention.
It is a figure which shows the input waveform which is not discriminate | determined from 2 video signals.

FIG. 11 is a block diagram of a conventional EDTV2 identification signal processing device.

FIG. 12 is a diagram showing an odd field signal waveform of each part in the conventional EDTV2 identification signal processing device.

FIG. 13 is a diagram showing an even field signal waveform of each part in the conventional EDTV2 identification signal processing device.

[Explanation of symbols]

1 sync separation circuit, 2 edge detection circuit, 3 half H
Removal circuit, 4 Vertical sync separation circuit, 5 Delay circuit, 6
Counter circuit, 7 line detection circuit, 8 sync signal correction circuit, 9 counter circuit, 10 flip-flop, 11 flip-flop, 12 AND circuit, 13
flip flop.

Claims (5)

[Claims] 1. A first means for separating a sync signal from a video signal, a second means for extracting a sync edge signal comprising a leading edge of the sync signal separated by said first means, and said second means.
Third means for extracting a half H removal signal obtained by removing the half H signal in the vertical blanking period from the synchronization edge signal extracted by the means; and a third means for separating the vertical synchronization signal from the synchronization signal separated by the first means. 4 means, 5th means for extracting a vertical sync delay signal obtained by delaying the vertical sync signal separated by said 4th means for a predetermined time, and said 5th means based on the vertical sync delay signal extracted by said 5th means Sixth means for counting the half H removal signals extracted by the three means and outputting a timing pulse for detecting a line in which an identification signal relating to a specific television broadcast is inserted; and the sixth means for outputting. And a seventh means for generating a line detection signal for limiting a signal processing period for identifying the identification signal from the generated timing pulse. No. processing apparatus. 2. A first means for separating a sync signal from a video signal, a second means for extracting a sync edge signal comprising a leading edge of the sync signal separated by said first means, and said second means.
Third means for extracting a half H removal signal obtained by removing the half H signal in the vertical blanking period from the synchronization edge signal extracted by the means; and a third means for separating the vertical synchronization signal from the synchronization signal separated by the first means. 4 means, 5th means for extracting a vertical sync delay signal obtained by delaying the vertical sync signal separated by said 4th means for a predetermined time, and said 5th means based on the vertical sync delay signal extracted by said 5th means The half H removal signal extracted by the 3 means is counted, and the identification signal related to wide clear vision broadcasting is inserted. 2
A sixth means for outputting a timing pulse for detecting two lines (285 lines) and a signal processing period for identifying a signal related to wide clear vision broadcasting from the timing pulse output by the sixth means are limited. An identification signal processing device, comprising: a seventh means for generating a line detection signal. 3. An eighth means for detecting a missing part of the half H removal signal extracted by the third means and correcting the half H removal signal when the signal is missing. The identification signal processing device according to claim 1 or 2. 4. The 22 lines in which the half H removal signals extracted by the third means are counted based on the vertical sync delay signal extracted by the fifth means, and the identification signal for wide clear vision broadcasting is inserted. (285 lines)
Several lines before and after {22 lines (285 lines) -α line to 22 lines (285 lines) + β line} (α ·
The identification signal processing device according to any one of claims 1 to 3, further comprising a ninth means for outputting a timing pulse for detecting (β is an integer). 5. The identification result is inverted when it is determined that the identification result is two or more lines "a signal related to wide clear vision broadcasting" within the detection period of the line detection signal generated by the ninth means. The identification signal processing device according to claim 4, further comprising: a tenth means for causing the identification signal processing device.