JPH09218281A - Time-measuring apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a time measuring apparatus which can measure a time interval between each of a plurality of signals to be measured and a measurement reference signal and hold each measuring result even when the plurality of signals are generated at considerably close time points each other. SOLUTION: The apparatus is provided with four signal-processing parts 6a-6d. Each processing part 6a-6d takes in a delay signal DY0-DYn output in accordance with a transmission position of a measurement start signal PA from a signal delay line 4 which delays and transmits the measurement start signal PA, with a timing of a measurement end signal PBi (i=1-4), and outputs digital data corresponding to a time interval of the signals PA and PBi as a measuring value DAi. Since the signal PBi and measuring value DAi are input/output through respective individual signal lines, the signals PBi never interfere with each other at however close time points the signals PBi are generated. Neither the measuring value DAi is rewritten subsequent to a succeeding measurement.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time measuring device capable of measuring a minute time interval with a delay time of a delay element as a resolution.

[0002]

2. Description of the Related Art Conventionally, an apparatus for detecting a phase difference (that is, a time interval) between two signals with a gate delay time as a resolution is disclosed in, for example, JP-A-3-220814 and JP-A-6-283984. , A pulse circulation circuit in which a plurality of delay elements are connected in a ring shape is activated by a first pulse input at an arbitrary timing to circulate a pulse signal, and the number of circulations is counted by a counter circuit, At the input timing of the second pulse that is input with an arbitrary phase difference from the first pulse, the orbiting position of the pulse signal that orbits the pulse orbiting circuit and the number of turns counted by the counter circuit are specified, and the orbiting position is determined. A pulse phase difference encoding circuit for detecting a phase difference (that is, a time difference) between the first and second pulses based on the number of turns and the number of turns and encoding the digital data is disclosed. To have.

Further, in Japanese Patent Laid-Open No. 5-308263, a first pulse input at an arbitrary timing is input to a delay line formed by connecting a plurality of delay elements in series, and Discloses a digital phase comparator which latches the output of the delay element at the input timing of the second pulse input with an arbitrary phase difference and outputs the latched output as digital data corresponding to the phase difference.

Further, Japanese Patent Laid-Open Nos. 5-48663 and 6-51003 include a ring oscillator in which a plurality of delay elements are connected in a ring shape, and an input signal input at any timing is provided. The output of each delay element that constitutes the ring oscillator is latched by and the circulating position of the pulse signal that circulates in the ring oscillator is specified based on the latched signal. An apparatus for identifying the phase relationship of is disclosed.

That is, these devices transmit a pulse signal transmitted by a delay line formed by connecting delay elements in series, or a pulse circulating circuit (ring oscillator) formed by connecting delay elements in a ring shape. The position is the signal to be measured (i.e.
2nd pulse and input signal) input timing,
The identified data is output as it is or after being subjected to processing such as further encoding, as data representing the phase difference from the signal serving as the measurement reference (that is, the first pulse or the reference clock).

[0006]

However, in these devices, the measurement result is held by latching the output of the delay line or the pulse circulation circuit by the signal to be measured (hereinafter referred to as the measurement signal). Therefore, if multiple measurement signals are used for continuous measurement, and the generation times of the measurement signals are extremely close, all the subsequent processing devices that perform processing using the measurement results of these devices are There is a problem that the measurement result cannot be effectively used for the measurement signal.

That is, if the next measurement signal is generated before the measurement result of the previously generated measurement signal is read by the processing device in the subsequent stage, the measurement result is rewritten. The measurement result of the signal cannot be used. Also, especially when two measurement signals occur at intervals shorter than the pulse width of the measurement signals,
These two measurement signals interfere with each other and become one,
Since the timing information of the measurement signal generated later is lost, there is also a problem that the measurement result cannot be obtained even for each measurement signal.

The present invention has been made in order to solve the above problems.
Even if there are multiple signals to be measured and the generation times of those signals are very close, the time interval between all signals and the reference signal is measured and the measurement result is retained. The purpose is to provide a possible time measuring device.

[0009]

In the time measuring device according to claim 1 of the present invention made to achieve the above object, when a start signal is input, the signal delaying means causes the signal delaying means to have a plurality of delay elements. Are transmitted in series while sequentially delaying the pulse signal on the signal delay line connected in series.

After that, when the end signal is input from the input line, the position detecting means holds the output signal of each delay element and transmits the pulse signal in the signal delay line based on the held output signal. The position is specified, and digital data corresponding to this transmission position is generated.

The digital data from the position detecting means is output to the output line as a measurement value obtained by measuring the time interval from the input of the start signal to the input of the end signal. In the present invention, a plurality of input lines for inputting the end signal are provided, and the position detection means and the output line are provided for each of the input lines, and each position detection means is independent of each other according to different end signals. To output the measured value to each output line.

As described above, according to the time measuring device of the present invention, since each end signal is input from a different input line, no matter how close the generation intervals of the end signals are, the end signal is generated. Without interfering with each other, for all termination signals input to each input line, it is possible to reliably obtain a measurement value, and since each measurement value is output from each individual output line, The measured values based on other measured signals are not rewritten, and as a result, all measured values can be reliably delivered to the subsequent processing device that performs processing using the measured values of the device.

Next, in the time measuring device according to the second aspect of the present invention, the signal delay means is composed of a pulse circulating circuit formed by connecting signal delay lines in a loop shape, and when the signal delay means is activated by input of a start signal, The pulse signal circulates in the pulse circulation circuit, and the counting means counts the number of circulations.

When the end signal is input, the position detecting means holds the output signal of each delay element as described above, and the lap number holding means holds the count result of the counting means. As a result, from the output line, a plurality of bits of digital data, in which the digital data from the position detecting means operating by the same end signal is the lower bit and the digital data from the cycle number holding means is the upper bit, are output as measured values. .

Therefore, according to the time measuring device of the present invention,
As compared with the case where the signal delay line is simply connected in series as the signal delay unit, the number of delay elements forming the signal delay line is sequentially increased by 1 each time the number of counting stages of the counting unit is increased by 1 bit. Since it can be set to / 2, the circuit configuration can be downsized, and longer time intervals can be measured with the same circuit scale.

Next, in the time measuring device according to the third aspect, when the end signal is input to the number-of-turns holding means,
The first holding circuit immediately holds the output of the counter circuit according to the end signal, and the second holding circuit holds the output of the counter circuit at a timing delayed according to the end signal delayed by the delay circuit.

Then, the selection circuit selects either the first holding circuit or the second holding circuit based on the circulating position of the pulse signal detected by the position detecting means which operates with the same end signal as that of the rotating frequency holding means. One of the outputs is selected and used as the output of the number-of-turns holding means. Therefore, according to the time measuring device of the present invention, stable time measurement can be performed no matter what timing the end signal occurs.

That is, the counter circuit has a certain amount of time (hereinafter referred to as "end") from the input of the end signal until the output is stabilized.
Since an undefined time is required, if the output of the counting means is held during the undefined time, an incorrect value will be held, but the counter circuit operates only once each time the pulse signal circulates. Therefore, by holding the output of this counter circuit twice with the timing shifted within the circulation time of the pulse signal, at least one of them can always hold the fixed output of the count circuit. In addition,
In the selection circuit, for example, when the circulating position of the pulse signal exists between the delay elements connected as the count clock of the counter circuit and the delay elements that are half the number before the total number of elements, the first holding circuit is set. Selected, otherwise second
A holding circuit may be selected. However, the switching timing of the selection by the selection means needs to be appropriately set in consideration of the delay time in the device of the count clock for driving the count means and the end signal for driving the first and second holding circuits. .

Next, in the time measuring device according to the fourth aspect, the counting means comprises a plurality of counter circuits,
Each counter circuit operates using the outputs of delay elements different from each other in the pulse circulation circuit as count clocks. When the end signal is input to the number-of-turns holding means, the holding circuit provided for each counter circuit holds the values of the outputs of the respective counter circuits all at once in accordance with the end signal.

Then, the selection circuit selects one of the plurality of holding circuits based on the pulse position of the pulse signal which circulates the pulse circulation detected from the output of the level retaining means, and selects the output of the circulation number retaining means. To do. Therefore, according to the time measuring device of the present invention, similar to the time measuring device according to the third aspect, stable time measurement can be performed regardless of the timing of the end signal.

That is, since each counter circuit performs a counting operation at different timings, and there is a counter circuit whose output is always stable, the selection circuit
By selecting the output of the holding circuit that holds the output of the counter circuit, the fixed output of the counting circuit can be reliably obtained.

Next, in the time measuring device according to the fifth aspect, the end signal generating means comprises a plurality of comparing circuits,
Each comparison circuit compares the pulsed input signal input to the end signal generation means with a preset comparison level, and when the signal level of the input signal reaches the comparison level, generates a predetermined end signal. And input to the input line.

Then, the measured value calculating means obtains the time interval from the start signal to the input signal based on the measured value output from each output line corresponding to the end signal.
Thus, according to the time measuring device of the present invention, since the input signal is measured at a plurality of points, it is possible to recognize the waveform of the input signal from the measured value, and based on the recognized waveform, By calculating the measured value, the time interval from the start signal to the input signal can be obtained,
Even if the waveform of the input signal varies depending on the measurement conditions, it is possible to always obtain stable and highly reliable measurement results.

That is, for example, when the rising and falling edges of the input signal are large, if the measurement is performed at only one comparison level, the measured value may be greatly different depending on the set comparison level, or the amplitude of the input signal may be measured. If it varies from time to time, even if the comparison level is fixed, the comparison conditions (that is, what percentage of the amplitude the comparison level is, etc.) differ depending on the waveform of the input signal, and stable measurement values can be obtained. However, since the waveform of the input signal can be recognized from the measured value in the present invention, by appropriately calculating the measured value, the measurement result corresponding to the measurement under the same condition can be obtained.

Next, in the time measuring device according to the sixth aspect of the present invention, the end signal generating means includes a pair of comparison circuits for comparing the input signals at the same comparison level when one of them is rising and the other is falling. Therefore, the measurement value calculation means obtains the average value of the measurement values from the pair of measurement values obtained based on the end signal generated by the pair of comparison circuits.

Therefore, according to the time measuring device of the present invention,
The time interval from the start signal to the input signal can be measured with reference to the center position of the input signal, regardless of the waveform and the peak value of the input signal. Next, in the time measuring device according to claim 7, the end signal generating means includes two or more comparing circuits for comparing the signal levels at the time of rising at different comparison levels, and the measurement value calculating means is the above-mentioned. The rising slope of the input signal is obtained from the measurement values obtained corresponding to the end signals generated by two or more comparator circuits, and the rising start time of the input signal is obtained from the obtained rising slope. .

Therefore, according to the time measuring device of the present invention,
It is possible to accurately measure the time interval from the start signal to the rising start of the input signal, that is, from the beginning of the input signal.

[0028]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit configuration diagram showing the overall configuration of the time measuring device 2 of the first embodiment that measures the time interval from the input of the measurement start signal PA to the input of each of the measurement signals PB1 to PB4. .

As shown in FIG. 1, the time measuring device 2 of the present embodiment transmits a signal delay line 4 which delays an input measurement start signal PA and a transmission position of the measurement start signal PA from the signal delay line 4. Delay signals DY0 to D output according to
Measurement start signal PA and each measurement end signal PB based on Yn
It is composed of four signal processing units 6a to 6d that output a measurement value DAi representing a phase difference (time interval) with i (i = 1 to 4).

Among them, the signal delay line 4 is formed by connecting in series n inverters INV1 to INV for inverting and outputting an input signal, and the input DY of the first-stage inverter INV1.
0, and outputs DY1 to D of the inverters INV1 to 30
Buffers BF0 to BFn for reducing parasitic capacitance are connected to the signal line for taking out Yn to the outside.

On the other hand, the signal processing units 6a to 6d have exactly the same configuration, and the outputs DY0 to DY0 of the signal delay line 4 are used.
D-type flip-flops (D) that latch DYn at the rising timing of the measurement end signal PBi (i = 1 to 4), respectively.
FF) circuits Fi0 to Fin, and a latch output of n + 1 bits latched by these DFF circuits Fi0 to Fin is output as a measurement value DAi.

In the time measuring device 2 thus constructed, the measurement start signal PA is input and the inverter I of the first stage is connected.
When the NV1 performs the inversion operation, the inversion operation is sequentially propagated to the inverters INV2 to 30 of the next stage and thereafter, and in the inverter INVj corresponding to the transmission position of the measurement start signal PA,
Its input and output have the same signal level.

Therefore, the transmission position of the measurement start signal PA can be specified by detecting the location where two adjacent bits have the same value from the measurement value DAi which is the value latched by the measurement end signal PBi. Further, it is possible to specify the time interval from the measurement value DAi to the rise of the measurement start signal PA to the rise of the measurement end signal PBi.

The time measuring device 2 of this embodiment is configured as an IC circuit integrally formed on a semiconductor substrate,
In particular, the signal lines for transmitting the measurement start signal PA, the measurement end signal PB, and the outputs DY0 to DYn of the signal delay line 4 are metal-wired. This is because the parasitic capacitance of the signal line that transmits the timing signal related to the time measurement is reduced as much as possible, the rounding of the signal waveform is prevented, and a steep waveform is secured to enable stable time measurement.

As described above, in the time measuring device 2 of this embodiment, the measurement start signal is generated based on the outputs DY0 to DYn from the signal delay line 4 which operates by the measurement start signal PA and the measurement end signal PBi. Four signal processing units 6a to 6d that output measurement values DAi corresponding to the time interval from PA to the measurement end signal PBi (i = 1 to 4) are provided in parallel, and each measurement end signal PBi and measurement value DAi are The signal processing units 6a to 6d are configured to be input and output by individual signal lines.

Therefore, according to the time measuring device 2 of the present embodiment, even if the measurement end signals PBi are generated so as to overlap each other at extremely close times to each other, the measurement end signals PBi are different from each other as in the conventional device. The plurality of measurement end signals PBi do not interfere with each other to be recognized as one signal, and the measured value DA
Since i is also output through a separate signal line, the measured value DAi of the measurement end signal PBi generated earlier is not overwritten by the measured value DAi of the measurement end signal PBi generated later, and As a result, the measurement for each measurement end signal PBi can be reliably performed.

In this embodiment, the signal processing units 6a to 6a are used.
Although d outputs the outputs of the DFF circuits Fi0 to Fin as the measurement values DAi as they are, the DFF circuits Fi0 to F
An encoder may be provided for converting the measurement start signal PA into binary digital data representing the number of stages passed through the inverter INV, based on the transmission position of the measurement start signal PA specified from the output of in.

In this case, in the subsequent processing device which performs processing using the output of the device 2, the measured value DAi can be used as it is for arithmetic processing etc. without being processed.
Next, FIG. 2 is a block diagram showing the overall configuration of the time measuring device 10 of the second embodiment.

As shown in FIG. 2, the time measuring device 10 of the present embodiment is activated by the measurement start signal PA, and the pulse circulation circuit 1 as a signal delay means for circulating the pulse signal.
2, a 4-bit counter circuit 14 as a counting means that uses a circulation signal output every time the pulse signal circulates in the pulse circulation circuit 12 as a count clock CK, and a pulse signal from the pulse circulation circuit 12 to a circulation position of the pulse signal. Based on the delay signals DY0 to DY30 output in response to the count value CO from the counter circuit 14, the measurement start signal PA
And four measurement end signals PBi (i = 1 to 4) are phase-coded (time intervals) into 9-bit digital data, and the four signal processing units 16a to 16d are output as measured values DAi.
It is composed of

FIG. 3 is a circuit configuration diagram of each part of the time measuring device 10. The signal processing units 16a to 16d are
Since all have the same configuration, here, the signal processing unit 16
Only a will be described. First, the pulse circulation circuit 12
Is a NAND circuit NAND that operates by receiving a start signal PA at one input terminal and 30 inverters INV1 to INV3.
0 and 0 are connected on a ring, and each of these inverting circuits (that is, a NAND circuit NAND and inverters INV1-3
0) output DY0 to DY30 are output to the signal line through buffers BF0 to BF0 for reducing parasitic capacitance.
The BFs 30 are respectively connected.

The final stage of the inverting circuit (inverter IN
The output of V30) is input to the counter circuit 14 as the count clock CK, and the counter circuit 14 counts at both the rising and falling edges of the count clock CK. Next, the signal processing unit 16a
Output DY0 to DY30 of the inverting circuit to the measurement end signal PB
DFF circuit F that latches at the rising edge of 1
Latch group 18 including 0 to 30 and each DFF circuit F0 to
Based on the output signal from 30, the circulating position of the pulse signal circulating in the pulse circulating circuit 12, that is, the position where the same signal level continues is detected, and it is the inversion circuit of the first stage (NAND circuit NAND). If there is 0, if it is the last inverting circuit (inverter INV30), 30 (11110)
H) such as 5 bit binary digital data E
An encoder 20 that encodes D, a first latch circuit 22a that latches the output CO of the counter circuit 14 at the rising timing of the measurement end signal PB1, and a measurement end signal P
A delay line 24 for delaying B1 by a time substantially half the circulation time of the pulse signal in the pulse circulation circuit 12, and a delay line 2
The second latch circuit 22b that latches the output CO of the counter circuit 14 at the rising timing of the delay signal PB1a delayed by 4 and the most significant bit M of the encoder output ED.
Based on SB, if MSB = 0, the first latch circuit 22a
Based on the multiplexer 26 which selects and outputs the output of the second latch circuit 22b if MSB = 1, the 5-bit encoder output ED and the 4-bit multiplexer output MD, the measurement start signal PA is measured from the rising edge thereof. The time interval until the rise of the end signal PB1 is converted into 9-bit binary digital data with the delay time of the inverting circuit forming the pulse circulation circuit 12 as a unit, and the measured value DA1 is obtained.
And a register 28 for outputting as.

The latch group 18 and the encoder 20 correspond to the position detecting means described above, and the first latch circuit 22a,
The second latch circuit 22b, the delay line 24, and the multiplexer 26 correspond to the number-of-turns holding means, and the signal line for taking out the output of the register 28 corresponds to the output line.

In the register 28, the encoder output ED is the lower 5 bits and the multiplexer output MD is the upper 4 bits.
A value obtained by subtracting a 4-bit digital value composed of the multiplexer output MD from the 9-bit digital value composed of bits is output as the measured values DA0 to DA8.

When the value of the multiplexer output MD represented by a decimal number is N and the delay time of the inverting circuit is 1, the value of the multiplexer output MD represents 31 × N, which is the measured value as it is. This is for correcting the error because it cannot be used as the upper 4 bits of DA. For details, see Japanese Patent Laid-Open No. 3-2.
No. 20814, so further explanation is omitted here.

In the first latch circuit 22a and the second latch circuit 22b, the output CO of the counter circuit 14 is latched by shifting the timing by half of the circulation time, and the most significant bit MSB of the encoder output ED is latched. The multiplexer 26 selects either one of the outputs based on the
Is taken in with the signal level thereof fixed.

That is, since the counter circuit 14 requires a finite time (indefinite time) from the input of the count clock CK until its output CO is determined, if this output CO is latched during the indefinite time, Although an erroneous value will be latched, the counter circuit 14 operates only once for each revolution time of the pulse signal, and thus, the counter circuit 14 shifts by half the revolution time and latches twice. As a result, at least one of the counter circuits 14
Output CO can be latched in a state where its signal level is fixed. And the encoder output E
If the MSB of D is 1, the pulse signal is in one of the latter half stages (inverters INV16 to 30) of the inverting circuit, and when the measurement end signal PB1 is input, the counter circuit 14 makes at least one revolution from the previous operation. Since more than half of the time has elapsed and its output CO is definitely determined, in this case, the output of the first latch circuit 22a may be selected, and in other cases (MSB = 0) Is to select the output of the second latch circuit 22b.
Since the details of this are described in JP-A-6-283984, further description will be omitted here.

The time measuring device 10 of the present embodiment thus constructed is constructed as an IC circuit integrally formed on the semiconductor substrate, and like the first embodiment,
Measurement start signal PA, measurement end signal PB, and outputs DY0 to DY30 of each inverting circuit forming the pulse circulation circuit 12.
Each signal line for transmitting is a metal wiring.

The time measuring device 10 configured as described above
In the above, when the start signal PA rises, the pulse circulation circuit 12 starts the circulation operation of the pulse signal, rotates the pulse signal while the pulse signal PA is at the high level, and the number of circulations is counted by the counter circuit 14. .

When the measurement end signal PB1 rises, the latch group 18 latches the outputs DY0 to DY30 of each inverting circuit of the pulse circulation circuit 12 and the first latch circuit 22a latches the output CO of the counter circuit 14. Then, after a half of the circulation time of the pulse signal has passed, the second latch circuit 22b again causes the counter circuit 14 to
Latch output CO of.

Then, the encoder 20 causes the latch group 18
Based on the output of the pulse signal, the circulating position of the pulse signal is detected and converted into binary digital data corresponding to the circulating position, and this is input to the register 28 as the encoder output ED. On the other hand, the multiplexer 26 outputs the encoder output ED. Either the output of the first latch circuit 22a or the second latch circuit 22b is input to the register 28 as the multiplexer output MD according to the value of the most significant bit MSB.

Then, the register 28, based on the encoder output ED and the multiplexer output MD, determines the number of rounds and the rounding position of the pulse signal in the pulse rounding circuit 12, that is, from the rise of the measurement start signal PA to the measurement end signal PB.
Convert the time interval until the rise of 1 into binary digital data with the delay time of the inverting circuit as a unit, and measure the measured value D
Output as A1.

FIG. 4 is an explanatory view showing the overall operation of the time measuring device 10. As shown in FIG. 4, as the measurement start signal PA, a signal that rises at the time when the measurement is started and is at the High level for at least the maximum time interval at which measurement can be performed is input. In addition, the measurement end signals PB1 to
As PB4, a signal that rises at the time when the measurement ends is input.

As a result, from the time measuring device 10, the time interval T1 from the rise of the measurement start signal PA to the rise of the measurement end signal PB1 is 9 bits with the inverting circuit constituting the pulse circulation circuit 12 as a unit. Similarly, as the measurement value DA1 represented by binary digital data, the time interval T2 until the rise of the measurement end signal PB2 is the measurement value DA2, and the time interval T3 until the rise of the measurement end signal PB3 is the measurement value DA3. Measurement end signal PB4
The time interval T4 until the rising edge of is output as the measured value DA4.

As described above, in the time measuring device 10 of this embodiment, as in the first embodiment, four signal processing units 16a to 16d are provided in parallel, and each measurement end signal PBi and the measured value. Since DAi is configured to be input / output to / from each of the signal processing units 16a to 16d through individual signal lines, the same effect as in the first embodiment can be obtained.

Further, according to the time measuring device 10 of the present embodiment, the output CO of the counter circuit 14 is set to the measurement end signal PB.
It is latched at the timing i and is separately latched at the timing delayed by half the circulation time, and the output CO of the counter circuit 14 is output according to the circulation position of the pulse signal.
Since the latched one is selected when the signal level of is determined and is used as the data representing the number of turns of the pulse signal, the highly reliable measured value DA
i can be obtained.

In this embodiment, the entire time measuring device 10 is constructed as an IC circuit, but the pulse circulation circuit 1
2, counter circuit 14, and signal processing units 16a to 16d
Of the latch group 18, the first latch circuit 22a, and the second latch circuit 22b are formed by an IC circuit.
The outputs of the first latch circuit 22a and the second latch circuit 22b may be fetched by a well-known microcomputer, and the encoder 20, the multiplexer 26, and the register 28 may be configured as a process executed by the well-known microcomputer.

In addition, in this embodiment, the encoder output ED and the multiplexer output MD are set by the register 28.
Although it is converted into binary digital data with the delay time of the inverting circuit as a unit, it is output as the measured value DAi.
The encoder output ED may be simply output as the lower 5 bits and the multiplexer output MD may be output as the upper 4 bits. In this case, the upper 4 bits may be treated as a coarse measurement value of the delay time.

Furthermore, the encoder 20 may be omitted, and the data latched by the latch group and the multiplexer output MD may be directly output as the measurement value DAi. Next, the time measuring device 1 of the third embodiment
0a will be described.

Only the parts different in structure from the time measuring device 10 of the second embodiment will be described. As shown in FIG. 5, the time measuring device 10a of the present embodiment is provided with two counter circuits 14a and 14b for counting the number of circulations of the pulse signal in the pulse circulation circuit 12, and one counter circuit is provided. The output of the inverting circuit (inverter INV15) located at the substantially central stage of the pulse circulation circuit 12 is input to 14a as the count clock CKa, and the other counter circuit 14b is the inverting circuit located at the final stage (inverter INV30). Output of count clock CKb
Has been entered as.

Then, the first latch circuit 22a outputs the output COa of the counter circuit 14a, and the second latch circuit 22b.
Are configured to latch the output COb of the counter circuit 14b at the rising timing of the measurement end signal PB1. That is, in the second embodiment, the output of the single counter circuit 14 is changed to the two latch circuits 22a and 22a.
Although b is latched at different timings, in the present embodiment, the outputs of the two counter circuits 14a and 14b operating at different timings are output to the two latch circuits 22a and 22a.
By making 22b latch at the same timing, at least one of the latch circuits 22a, 22b
The outputs COa and COb of the counter circuits 14a and 14b are
It is latched when the signal level is fixed.

Therefore, according to the time measuring device 10 of the present embodiment, it is possible to obtain the highly reliable measurement value DAi just as in the case of the second embodiment. Next, a fourth embodiment will be described. FIG. 6 is a block diagram showing the overall configuration of the optical round-trip time measuring apparatus 50 of the present embodiment, which emits laser light, receives reflected light from a predetermined target T, and measures the round-trip time of the light. .

As shown in FIG. 6, the optical round-trip time measuring apparatus 50 of the present embodiment measures the time when the light is emitted / received by the encoder 10 which is the time measuring apparatus of the second embodiment and the laser light. Start signal PA, measurement end signal PB1 when receiving light
A signal generation unit 30 that generates PB4 and inputs it to the encoding unit 10, and digital data DA1 that the encoding unit 10 outputs.
.About.DA4, a predetermined arithmetic operation is executed, and a data processing unit 40 as an arithmetic means for outputting the arithmetic results DAL and DAH.

When a measurement start switch (not shown) is operated, the signal generator 30 outputs a drive signal DS having a predetermined pulse width and rises at the same time as the drive signal DS so that at least the device can measure. A drive signal generation circuit 32 that outputs a measurement start signal PA that is at a High level for a maximum time interval, an LD drive circuit 34 that causes a laser diode LD to emit light in response to a drive signal DS from the drive signal generation circuit 32, and a laser. A PD drive circuit 36 that causes the photodiode PD to receive the laser light emitted from the diode LD, reflected by the target T, and returned, and amplifies and outputs the received light signal, and a PD drive circuit 36.
And the comparator 38a that outputs the measurement end signal PB1 when the received signal RS reaches the first comparison level LV1 when the amplified received light signal (hereinafter referred to as the received signal) RS rises, and also the received signal RS rises. When the reception signal RS reaches the second comparison level LV2 (> LV1), the comparator 38b that outputs the measurement end signal PB2 and the reception signal RS when the reception signal RS falls are the second comparison level LV.
When reaching 2, the comparator 38 which outputs the measurement end signal PB3
Similarly, when the received signal RS falls, the received signal RS
Reaches the first comparison level LV1, the measurement end signal PB4
And a comparator 38d that outputs

The measurement start signal PA and the measurement end signals PB1 to PB4 are input to the encoding unit 10 via buffers BF40 to 44 for reducing the parasitic capacitance of the wiring. Further, here, the comparators 38a to 38d correspond to the above-mentioned end signal generating means.

On the other hand, as shown in FIG. 7, the data processing unit 40 includes an adder 42 for adding the measured value DA1 and the measured value DA4, an adder 44 for adding the measured value DA2 and the measured value DA3, and an adder Shift register 4 for shifting the operation result of the device 42 to the lower side by 1 bit (that is, dividing by 2)
6 and a shift register 48 for shifting the operation result of the adder 44 to the lower side by 1 bit. The output of the shift register 46, that is, the measured values DA1, D
The arithmetic average of A4 is output as the processed value DAL, and the output of the shift register 48, that is, the arithmetic average of the measured values DA2 and DA3 is output as the processed value DAH.

Since the encoding unit 10 is constructed in exactly the same way as in the second embodiment, its explanation is omitted.
The optical round-trip time measuring device 5 of the present embodiment configured as described above
At 0, when the command switch is operated, the laser diode LD is driven according to the drive signal DS, and the target T
A laser beam is output toward and the measurement start signal P
According to A, the encoding unit 10 starts operation.

After that, when the photodiode PD receives the reflected light from the target T, the received signal RS output from the PD drive circuit 36 according to the received light is compared with the comparator 38a.
.About.38d generate the measurement end signals PB1 to PB4 by comparing with the respective predetermined levels.

That is, as shown in FIG. 8, when the signal level of the received signal RS starts to rise and reaches the first comparison level LV1, the comparator 38a generates the measurement end signal PB1 and the signal level is further increased. When it rises and reaches the second comparison level LV2, the measurement end signal PB2 is generated by the comparator 38b. After that, the peak of the signal level of the reception signal RS passes, the signal level starts to decrease, and the second comparison level LV
When it reaches 2, the comparator 38c generates the measurement end signal PB3, and when the signal level further decreases to reach the first comparison level LV1, the comparator 38d outputs the measurement end signal PB3.
4 is generated.

Then, the encoder 10 to which the measurement end signals PB1 to PB4 have been input, determines the time T1 to T4 from the rise of the measurement start signal PA to the rise of each of the measurement end signals PB1 to PB4. Is converted into binary digital data in units of the delay time of the inverting circuit and output as measured values DA1 to DA4, and the data processing unit 40, based on these measured values DA1 to DA4, calculates two added average values {( T1 + T4) / 2, (T2 + T3) 2}
And output as processed values DAL and DAH.

As described above, according to the optical round trip time measuring apparatus 50 of the present embodiment, the time required for the received signal RS to reach a certain signal level (here, LV1 and LV2) is determined when the signal rises and when it falls. And the average of the measurement start signal is calculated to obtain the time interval from the rise of the measurement start signal to the central position where the amplitude of the received signal RS is substantially peaked. Stable measurement can be performed without being affected by. That is, the amount of attenuation of the laser light received by the photodiode PD greatly differs depending on the state of the reflecting surface of the target T and the conditions on the optical path, and as a result, the amplitude of the reception signal RS greatly changes depending on the measurement conditions. However, normally, even if the amplitude fluctuates in this way, the peak position of the amplitude of the received signal RS does not shift only by increasing or decreasing as a whole,
Therefore, by measuring the time to the peak position, stable measurement can be performed irrespective of fluctuations in the amplitude of the received signal RS, and consequently fluctuations in the measurement conditions.

Further, according to this embodiment, the processed values DAL and DAH are respectively calculated based on the two comparison levels LV1 and LV2.
Therefore, when the amplitude of the received signal RS is larger than the second comparison level LV2, the processed value D based on the measurement at the comparison level LV2 closer to the peak of the amplitude is obtained.
AH is adopted, and if the amplitude of the received signal RS is smaller than the second comparison level LV2 and the measurement at the second comparison level LV2 cannot be performed, the processed value DAL based on the measurement at the first comparison level LV1 is adopted. By doing,
Even if the amplitude of the received signal RS varies greatly, the measurement can always be performed with a minimum error.

The optical round trip time measuring apparatus 50 of this embodiment is used.
The processed values DAL and DAH, which are the outputs of, can be used, for example, to calculate the distance from the target T. Further, in the present embodiment, the data processing unit 40 is composed of the adders 42 and 44 and the shift registers 46 and 48, but the measured values DA1 to DA4 are loaded into a well-known microcomputer, and this microcomputer is used. It may be configured to be realized by arithmetic processing by a computer.

Further, in the present embodiment, the signal generator 30 outputs four reception end signals PB1 from one reception signal RS.
~ PB4 is generated and the time interval between the measurement start signal PA and the reception signal RS is precisely measured.
In the signal generator 30, for example, reflected lights from different directions are individually received, and the received signals are measured end signals PB.
1 to PB4 may be directly input to the encoding unit 10 and the time intervals between the measurement start signal PA and a plurality of received signals may be simultaneously measured. In addition,
In this case, the data processing unit 40 is omitted.

Next, the optical round trip time measuring apparatus of the fifth embodiment will be described. Optical round trip time measuring device 50 of the present embodiment
Is different from the fourth embodiment only in the configurations of the comparators 38a to 38d and the data processing unit 40, and only the different configurations will be described.

First, in the comparators 38a to 38d, the conditions for outputting the measurement end signals PB1 to PB4 are changed, that is, as shown in FIG. 9, the signal level of the reception signal RS starts to rise. Then, when the first comparison level LV1 is reached, the comparator 38a outputs the measurement end signal PB1, and the signal level further rises to the second comparison level LV2 (> LV1).
Is reached, the comparator 38b outputs the measurement end signal PB2, and the signal level further rises to the third comparison level LV3.
When (> LV2) is reached, the comparator 38c causes the measurement end signal P
B3 is output, and when the signal level further rises and reaches the fourth comparison level LV4 (LV3), the comparator 38d outputs the measurement end signal PB4.

That is, the rise of the received signal RS is measured in detail. On the other hand, in the data processing unit 40, based on the measured values DA1 to DA4 obtained at the timings of the measurement end signals PB1 to PB4, first, the slope of the reception signal RS is calculated, and on the straight line having this slope, It is configured to calculate a point (time) at which the signal level becomes zero.

As a result, according to the optical round-trip time measuring apparatus 50 of this embodiment, the rising start time of the received signal RS can be accurately obtained regardless of the waveform of the received signal RS. It is possible to perform stable measurement regardless of the waveform.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram showing an overall configuration of a time measuring device according to a first embodiment.

FIG. 2 is a block diagram showing an overall configuration of a time measuring device according to a second embodiment.

FIG. 3 is a circuit configuration diagram of each unit of the time measuring device.

FIG. 4 is an explanatory diagram showing the operation of the time measuring device.

FIG. 5 is a circuit configuration diagram of each part of the time measuring device according to the third embodiment.

FIG. 6 is a block diagram showing the overall configuration of an optical round trip time measuring apparatus of a fourth embodiment.

FIG. 7 is a block diagram showing a configuration of a data processing unit.

FIG. 8 is an explanatory diagram showing the operation of the optical round-trip time measuring apparatus of the fourth embodiment.

FIG. 9 is an explanatory diagram showing the operation of the optical round-trip time measuring apparatus of the fifth embodiment.

[Explanation of symbols]

2, 10 ... Time measuring device (encoding unit) 4 ... Signal delay lines 6a to 6d, 16a to 16d ... Signal processing unit 12 ... Pulse circulation circuit 14, 14a, 14b ... Counter circuit 18 ... Latch group 20 ... Encoder 22a ... First latch circuit 22
b ... Second latch circuit 24 ... Delay line 26 ... Multiplexer 28 ... Register 30 ... Signal generator 32 ... Drive signal generator 34
LD drive circuit 36 PD drive circuits 38a to 38d Comparator 4
0 ... Data processing unit 42, 44 ... Adder 46, 48 ... Shift register 50 ... Optical round-trip time measuring device

Claims (7)

[Claims] 1. A time measuring device for measuring a time interval from a start signal to an end signal, the signal measuring device having a signal delay line in which a plurality of delay elements are connected in series, the pulse signal being activated by input of a start signal. A signal delay means for transmitting while sequentially delaying on the signal delay line, a plurality of input lines to which the end signal is individually input, and an end signal which is provided for each input line and is input to the input line. According to the above, while holding the output signal of each delay element, based on the held output signal, the transmission position of the pulse signal in the signal delay line is detected, and the digital data corresponding to the transmission position is obtained. Generated position detecting means and digital data from the position detecting means which is provided for each of the input lines and operates according to an end signal input to the input lines is output as a measurement value. Time measuring apparatus characterized by comprising: a power line, a. 2. The time measuring device according to claim 1, wherein the signal delay means causes the pulse signal to circulate when the signal delay lines are connected in a loop and activated by input of a start signal. A counting circuit for counting the number of circulations of the pulse signal in the pulse circulation circuit and outputting it as digital data, and a counting means which is provided for each input line and which receives an end signal input to the input line. And the number of turns holding means for holding the output of the counting means, wherein the output line outputs the digital data from the position detecting means operating with the same end signal to the lower bit, A time measuring device characterized by outputting a plurality of bits of digital data having digital data as upper bits as a measurement value. 3. The time measuring device according to claim 2, wherein the counting means comprises a single counter circuit operated by an output of any delay element of the pulse circulation circuit, and the circulation number holding means. A first holding circuit which holds the output of the counter circuit by the end signal, a delay circuit which delays the end signal by a time period during which the pulse signal makes a half cycle around the pulse circulation circuit, and a delay circuit which delays the end signal. A second holding circuit that holds the output of the counter circuit with the generated end signal, and the circulating position of the pulse signal detected by the position detecting means that operates with the same ending signal as the circulating frequency holding means. A time measuring device comprising: a selection circuit for selecting the output of either the first holding circuit or the second holding circuit. 4. The time measuring device according to claim 2, wherein the counting means is composed of a plurality of counter circuits that operate by outputs of different delay elements of the pulse circulation circuit, and the circulation frequency holding means includes: A holding circuit which is provided for each counter circuit and holds the output of the counter circuit in accordance with the end signal, and the pulse signal which is detected by the position detecting means which operates with the same end signal as the number-of-turns holding means. A time measuring device comprising: a selection circuit that selects one of the outputs of the plurality of holding circuits based on a circulating position. 5. The time measuring device according to any one of claims 1 to 4, further comprising: for each input line that generates the end signal by comparing the input signal with a preset comparison level. An end signal generating means including a plurality of comparison circuits provided, and the start signal and the input signal based on the measurement value output from each output line according to the end signal generated by the end signal generating means. A time measuring device comprising: a measurement value calculating means for determining a time interval between 6. The time measuring device according to claim 5, wherein the input signal is a signal having a predetermined pulse width, and the end signal generating means outputs one of the input signals at the same comparison level. The measurement value calculating means includes a pair of comparison circuits for comparing the other at the time of rising with the other at the time of falling. A time measuring device characterized by determining. 7. The time measuring device according to claim 5, wherein the end signal generating means includes two or more comparing circuits that compare the signal levels of the input signal at the rising edge with different comparing levels. The measured value calculation means obtains a rising slope of the input signal from a measured value obtained based on end signals generated by the two or more comparison circuits, and further calculates a rising start time of the input signal from the slope. A time measuring device characterized by seeking.